JPH0591494A - High efficiency encoder - Google Patents

Abstract

PURPOSE:To shorten processing time. CONSTITUTION:A request signal A is outputted from a prestage processing area to a poststage processing area when the processing in the processing area at the prestage has been completed, in each processing area of a DCT processing area 10, a quantitization processing area 20 and a variable length encoding processing area 30. In response to the request signal A, when the poststage processing area gets ready for operation, a response signal R is transmitted from the poststage processing area to the prestage processing area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency encoder which compresses and encodes a video signal for output, and is suitable for application to, for example, a so-called video conference or video telephone system.

[0002]

2. Description of the Related Art As a high-efficiency encoder for compressing and outputting a video signal, for example, a so-called video conference or a video telephone system, for example, H.264 in the so-called CCITT (International Telegraph and Telephone Consultative Committee) recommendation. There is a H.261 standard system.

This H.264 In the H.261 standard, the CIF format (intermediate signal format) is 360 pixels x 2
88 lines × 29.97 Hz, Y, C _B , C _R according to the non-interlaced method. In addition, the video source coding method is a hybrid coding in which the basic algorithm is motion compensation inter-frame prediction + orthogonal transform (DCT). Here, in the motion compensation, one vector is transmitted to a macro block of 16 × 16 pixels, and the search range is ± 1.
With 5 pixels x ± 15 lines, the color signal has no motion compensation, and the transform coding is DC with a block size of 8 x 8 (pixels).
T (discrete cosine transform), the applied quantization is selected from a maximum of 8 types of scans, the maximum number of quantizers is 32, and the in-loop filter is applied to the predictive code block (8 × 8) and 121 low pass types are applied. Is becoming In the video multiplex coding, the data structure has a four-layer structure of a frame, GOB, macroblock, and block. The macroblock type defines 10 types according to the inter / intra coding mode, motion compensation (MC) presence / absence, DCT coefficient presence / absence, quantizer change presence / absence, and filter presence / absence. The motion vector information is encoded by 32 code by encoding the difference vector and folding back the vector value. The coding of DCT coefficients is a two-dimensional coding for zero coefficient runs and non-zero coefficient values. Furthermore, the transmission format is
Bit rate is p × 64 kbit / sec, p = 1 to 3
It becomes 0. In buffering, the maximum number of bits in one encoded frame is 256 kbits in CIF, QCIF ((1
/ 4) CIF) results in 64 kbits.

FIG. 5 shows the above H.264. The structure of the encoding device in the H.261 standard is shown. The encoding apparatus of FIG. 5 uses an input video signal (input video signal) or a differential signal described later as a DC signal.
T (discrete cosine transform) is performed, the DCT-processed data is quantized, and then the quantized data is variable-length coded to realize compression coding of the input video signal. That is, the encoding apparatus of FIG. 5 makes a determination of so-called inter-frame predictive encoding (inter-frame predictive encoding) / intra-frame predictive encoding (intra-frame predictive encoding), and according to this determination, the input video signal To DCT
(Intra coding mode) or DC
T (inter coding mode).

First, the case of the intra coding mode will be described. That is, in FIG. 5, the H.V. A video signal (digital video signal) of a block format of 261 standard is supplied.
This video signal is sent to a CPU (Central Processing Unit) 8 which will be described later.
A switched signal from 0 (switching signal according to the intra coding mode of the inter / intra coding mode) supplies the switched terminal a to the discrete cosine transform (DCT) circuit 83 through the selected selector 82. The DCT circuit 83 outputs a frequency component obtained by subjecting the input video signal to the discrete cosine transform process. This DCT
The output of circuit 83 is sent to quantizer 84.

The quantizer 84 has its quantization step controlled by the CPU 80, and quantizes the frequency component from the DCT circuit 83. The output of the quantizer 84 (quantization output index q of the transform coefficient) is the terminal 74.
Via a variable length coding (VLC) process such as Huffman coding which adaptively uses so-called run length coding.

The data variable-length coded by the variable-length coding circuit 91 is serially output to the communication line side via the output terminal 77.

In the inter coding mode, the output of the quantizer 84 is sent to the predictive coding processing unit with motion compensation. That is, this predictive coding processing section is composed of the respective components after the inverse quantizer 85, and the output of the quantizer 84 sent to the predictive coding processing section is first the inverse quantizer. The quantizer 85 performs a process (inverse quantization process) opposite to the quantization process of the quantizer 84, and thereafter, an inverse discrete cosine process that is a process opposite to the discrete cosine transform in the DCT circuit 83. It is stored in an image memory (frame memory) 88 having a variable delay function for motion compensation through an IDCT circuit 86 which performs conversion processing and further through an adder 87. Note that the processing up to the frame memory 88 is performed even in the intra coding mode.

The input video signal of the current frame is supplied to the input terminal 70 and sent to the subtractor 81. At this time, the output of the frame memory 88 (data of the previous frame with respect to the current frame) is sent to the subtractor 81 via the loop filter 89 for noise removal. Therefore, the output of the subtractor 81 becomes difference data between the current frame and the previous frame. The output of the subtracter 81 passes through the path of the DCT circuit 83, the quantizer 84, the dequantizer 85, and the IDCT circuit 86 via the selector 82 whose terminal b is selected according to the inter-encoding mode. It is then supplied to the adder 87.

At this time, in the adder 87, the data of the previous frame stored in the frame memory 88 is passed through the loop filter 89, and further the switching signal (inter-encoding) from the CPU (central processing unit) 80. Selector 9 whose selected terminal b is selected by a switching signal according to the mode)
It is supplied via 0. That is, the adder 87 works in accordance with the inter / intra coding mode, and the output of the adder 87 is the difference data between the previous frame and the current frame obtained from the subtractor 81 and the data of the previous frame. It becomes the added data (that is, the data of the current frame). The data of the current frame from the adder 87 is again stored in the frame memory 88.

As described above, whether to use the inter coding mode or the intra coding mode depends on the above C.
It is controlled by the PU 80. Specifically, the CPU 8
At 0, the energy of the difference data is compared with the energy of the input video data of the current frame. For example, when the energy of the input video data of the current frame becomes larger, the selector 82 performs the processing in the inter coding mode. , 9
0 is controlled, and in the opposite case, the selectors 82 and 90 are controlled so that the processing in the intra coding mode is performed.

Further, the quantizer 84 is provided with a buffer memory (not shown) which is normally connected to the output terminal 77 after the output terminal 77 in order to adjust the difference between the transmission rate inside the encoding device and the transmission rate of the communication line. The quantization step is controlled in order to prevent (omitted) overflow and the like. That is,
The CPU 80 is supplied with accumulated amount data indicating the accumulated amount of the buffer memory from the buffer memory, and the CPU 80 controls the quantizing step of the quantizer 84 based on the accumulated amount data. There is.

In FIG. 5, an inter / intra coding mode identification flag p is output from the terminal 71 to the subsequent structure, and a transmission / non-transmission identification of whether or not to transmit a signal is performed from the terminal 72. The flag t is output and the terminal 73
Outputs the quantization characteristic designation data qz, which is the control information of the quantization step in the quantizer 84, from the terminal 75.
Outputs the motion vector data v from the frame memory 88 having a variable delay function for motion compensation, and the terminal 76 outputs data f indicating ON / OFF of the filter processing in the loop filter 89.

Further, each processing in the above-mentioned encoding device is performed by a block of 8 × 8 pixels or a macroblock consisting of four blocks of 8 × 8 pixels (that is, 16 blocks).
X16 pixel unit).

[0015]

By the way, the above H. Two
In the high-efficiency coding apparatus to which the 61 standard is applied, as described above, for example, the compression coding processing of the video signal is performed through each step of the DCT processing, the quantization processing, the variable length coding processing and the like. There is. However, the above D of the encoding device is
Region for CT processing (component for DCT processing), region for quantization processing (component for quantization processing), region for variable length coding (component for variable length coding), motion In each processing area such as an area to be compensated, the time required to process the 8 × 8 pixel block or the 16 × 16 pixel macroblock is
It varies depending on the data of the block (macro block) or the position of the block (macro block) on the screen.

For example, in the case of motion compensation, a short processing time is required for a block (macroblock) in contact with a frame (screen edge) of the screen, and, for example, the quantization level of a region to be quantized is controlled. The processing time and the like in the CPU 80 will vary depending on the data to be processed.

From the above, in the above-described conventional coding apparatus, it is possible to process, for example, the processing time of each block (macroblock) originally different in each processing area at a fixed timing. Alternatively, the blocks (macroblocks) are processed at timings that are variable but fixed according to the positions of the blocks (macroblocks).

For example, in the case of processing at the fixed length timing, it is necessary to make the timing of each processing region in accordance with the case where the processing time is the longest. In this case, in practice, it is necessary to shorten the processing time in the processing area where the processing time is long, so the processing area must be increased by increasing the hardware, improving the software, or increasing the clock speed. I try to shorten the time. However, in reality, although the hardware is increased, the software is improved, the clock speed is increased, etc., the amount of reduction in the processing time is small, and conversely, there is more time in the processing area with the shorter processing time. Such an imbalance has occurred. Further, at the fixed variable length timing, the processing time of each block (macroblock) is different, so that a bypass mode such as so-called loopback is required, for example. However, in this case, for example, a FIFO (first-in-first-out) memory or the like is required, which makes it difficult to configure the loopback, or causes the timing generator to be complicated.

In the case of the conventional apparatus shown in FIG. 5, for example, the CPU 80, the quantizer 84 (that is, the area for performing the quantization process), and the frame memory 88 are used.
(That is, a region for motion compensation) and the variable length coding circuit 9
That is, the processing time in each processing area of No. 1 is not constant (the time when data passes through each processing area is not constant). Therefore, each of these processing areas and the DCT circuit 8 for example
The processing time in 3 is not the same.

Therefore, the present invention has been proposed in view of the above situation, and it is possible to shorten the processing time of the entire high-efficiency coding apparatus without increasing the size of the structure. It is an object of the present invention to provide an efficiency coding device.

[0021]

The high-efficiency coding apparatus of the present invention is proposed in order to achieve the above-mentioned object, and divides a processing step of compressing and coding a video signal into a plurality of steps. A high-efficiency coding apparatus having a plurality of processing areas for performing processing for each of the divided steps, wherein the preceding stage is performed at the stage where the processing in the preceding processing area of at least two of the above processing areas is completed. Request signal is output from the processing region of the latter stage to the processing region of the latter stage, and when the processing region of the latter stage becomes ready to start operation in response to the request signal, the processing region of the latter stage becomes the processing region of the preceding stage. A response signal is sent to.

[0022]

According to the present invention, signals are exchanged between the front-stage processing region and the rear-stage processing region according to the processing status (that is, communication such as so-called handshake is performed), and the front-stage processing region is performed. In this case, the request signal is output to the subsequent processing area when the processing is completed, and the response signal is sent from the latter processing area to the previous processing area when the operation is ready to start. Therefore, the waiting time in each processing area can be reduced.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

The high-efficiency coding apparatus of the embodiment of the present invention is shown in FIG.
As shown in FIG. The processing steps in the high-efficiency coding apparatus as shown in FIG. 5 for compressing and outputting the video signal according to the H.261 standard, for example, DCT
It is divided into a plurality of steps such as a DCT processing step for performing orthogonal transformation such as (discrete cosine transformation), a quantization processing step, a variable length coding processing step, etc., and the processing for each divided step is performed. The high-efficiency coding apparatus has a plurality of processing areas such as a DCT processing area 10, a quantization processing area 20, a variable length coding processing area 30 and the like.

Here, in the encoding apparatus of this embodiment,
Of the at least two processing areas, when the processing in the preceding processing area is completed, the request signal (acknowledge signal) A is output from the preceding processing area to the succeeding processing area, and the request signal A is output. In response, a response signal (ready signal) R is sent from the subsequent processing area to the preceding processing area when the latter processing area is ready to start operation.

That is, in FIG. 1, the input terminal 1
Is supplied with an output signal (input video signal or differential signal) from the selector 82 having the configuration shown in FIG.
An input signal from the input terminal 1 is subjected to discrete cosine transform in the DCT processing area 10 and the quantization processing area 20
After the frequency component from the DCT processing area 10 is quantized by the variable length coding processing, variable length coding such as Huffman coding which adaptively uses run length coding is performed in the variable length coding processing area 30 to output the output terminal. It is output from 4.

When the processing is completed in the DCT processing area 10, the request signal A _DCT is output to the quantization processing area 20 in the subsequent stage. In addition, the quantization processing area 20 moves from the quantization processing area 20 to the preceding stage when the quantization processing is ready to start operation in response to the request signal A _DCT from the DCT processing area 10. A response signal R _Q is sent to the DCT processing area 10.

In the same manner, the above quantization processing area 20
When the processing is completed in, the request signal A _Q is output to the variable length coding processing area 30 in the subsequent stage. Further, the variable length coding processing area 30 is the quantization processing area 2
In response to the request signal A _Q from 0, the variable length coding processing area 30 sends a response signal R to the quantization processing area 20 when the variable length coding processing operation can be started. Send _VLC .

A response signal R is sent from the DCT processing area 10 to a further upstream structure (not shown) via a terminal 5, and the DCT processing area 10 is provided with a terminal 6 from the previous structure. The request signal A is sent through the request signal.

FIG. 2 shows a timing chart of the operation of each section in the configuration of FIG. Hereinafter, the operation of the configuration of FIG. 1 will be described step by step with reference to the timing chart of FIG.

First, when the DCT processing area 10 completes the processing of, for example, the first block # 1 of the 8 × 8 pixel block or the 16 × 16 pixel macro block, the DCT processing area 10 is removed from the DCT processing area 10. The request signal A _DCT is output to the quantization processing area 20 (time t ₁ ).

At this time, since the quantization processing area 20 is in an empty state, it outputs the response signal R _Q to the DCT processing area 10 as soon as it receives the request signal A _DCT (time t ₂ ). At the same time, the quantization process of the first block # 1 that has been subjected to the DCT process is started.

Further, in the DCT processing area 10, the next second block # 2 is supplied, and this block # 2 is supplied.
The DCT process is started for.

In the quantization processing area 20, the first
Th the quantization process of block # 1 is completed, the quantization processing region 20 outputs a request signal A _Q with respect to the variable length coding region 30.

At this time, the variable length coding processing area 30
Is a vacant state, it outputs the response signal R _VLC to the quantization processing area 20 (time t ₃ ) as soon as it receives the request signal A _Q , and the quantized first signal is output.
The variable-length coding process of the th block # 1 is started.

At this time, since the quantization processing of the second block # 2 has not been completed in the DCT processing area 10, the request signal A _DCT from the DCT processing area 10 is still quantized. It is not output to the processing area 20. Therefore, the quantization processing area 20 enters the waiting state.

The DCT processing area 10 outputs the request signal A _DCT when the processing of the second block # 2 is completed. Quantization processing area 2 in the waiting state
0 outputs the response signal R _Q to the DCT processing area 10 as soon as it receives the request signal A _DCT (time t
₄ ) and the quantization processing for the supplied second block # 2 is started.

The third block # 3 is then supplied to the DCT processing area 10, the processing of the third block # 3 is completed, and the request signal A _DCT is sent to the quantization processing area 20. Output (time t ₅ ). However, at this time, since the processing of the second block # 2 is being executed in the quantization processing area 20, the DCT
The processing area 10 enters a waiting state for the response signal R _Q from the quantization processing area 20.

When the quantization processing area 20 finishes the processing of the second block # 2, the quantization processing area 20 outputs the request signal A _Q to the variable length coding processing area 30. .. At this time, since the variable length coding processing area 30 is in the waiting state, the response signal R _VLC is immediately output to the quantization processing area 20 (time t ₆ ) and the second Th block # 2
The process of is started.

At the same time, the quantization processing area 20 outputs a response signal R _Q to the DCT processing area 10 and starts the processing of the third block # 3 from the DCT processing area 10. In the DCT processing area 10, the response signal R _Q supplied from the quantization processing area 20.
In response to this, the processing of the fourth block # 4 is started.

When the quantization processing area 20 finishes processing the third block # 3, it outputs the request signal A _Q to the variable length coding processing area 30 (time t ₇ ). However, at this time, since the processing of the second block # 2 is being executed in the variable length coding processing area 30, the quantization processing area 20 is in the response signal from the variable length coding processing area 30. Wait state until R _VLC is supplied.

When the DCT processing area 10 finishes the processing of the fourth block # 4, the request signal A _DCT is output to the quantization processing area 20 (time t ₈ ).
At this time, since the quantization processing area 20 is in a waiting state, the response signal R _Q is transmitted from the quantization processing area 20.
Is not obtained, and therefore the DCT processing area 10 is also in the waiting state.

The variable length coding processing area 30 is the second
When the processing of the second block # 2 is completed, the response signal R _VLC is output to the quantization processing area 20 (time t ₉ ) and the third block # from the quantization processing area 20 is output. The process of 3 is started. Since the quantization processing area 20 is in the waiting state, it immediately outputs the response signal R _Q to the DCT processing area 10 (time t ₉ ). Since the DCT processing area 10 is also in the waiting state, the processing of the fifth block # 5 is immediately started.

FIG. 3 shows a more specific structure of the structure shown in FIG.

That is, the configuration of FIG. 3 has a DCT circuit 11 for performing DCT processing, a quantization circuit 21 including a quantizer and a CPU, and a variable length coding circuit 31, and each of these processes. One processing unit (one block or one macroblock unit) between the circuits 11, 21 and 31
Buffers (for example, FIFO memories) 2 and 3 are inserted and connected, and further, a control (handshake) for outputting the above-mentioned request signal A and response signal R provided corresponding to each processing circuit 11, 21, 31 respectively. Control; HC
TL) circuits 12, 22, 32 are connected.

Here, the control circuit 22 provided corresponding to the quantizing circuit 21 is the DCT circuit 1 of the preceding stage.
The request signal A _DCT and the response signal R _Q are input / output to / from the control circuit 21 provided corresponding to 1, and the control circuit 32 provided corresponding to the variable length coding circuit 31 in the subsequent stage. The request signal A _Q and the response signal R _VLC are input and output between the input and output terminals. The control circuit 12 communicates request signals and response signals with further circuits not shown in the figure through terminals 5 and 6.

Further, the control circuits 12, 22,
When receiving the response signal R, the reference numeral 32 outputs a processing operation start signal S for starting an operation to each corresponding processing circuit 11, 21, 31 and
It receives the processing operation end signal E from the corresponding processing circuits 11, 21, 31 and outputs the request signal A.

By the way, in the configuration shown in FIG. 4 described above, the FIFO memories 2 and 3 of one processing unit (one block or one macroblock) are provided between the respective processing circuits 11, 21 and 31, and the FIFO memories 2 and 3 respond to the control circuit in the subsequent stage. Although the configuration is such that the signal R is output and the request signal A is sent to the control circuit at the preceding stage, the present embodiment is not limited to the configuration shown in FIG. 4 and other configurations are possible. ..

That is, for example, the response signal R (a signal indicating that processing is possible in this case) to the control circuit in the preceding stage is output, and the request signal A is returned to the succeeding stage.

Further, for example, each processing circuit 11, 21, 3
The capacity of the FIFO memories (buffers) 2 and 3 between 1 can be made larger than that of the above-mentioned one processing unit. In this case, the request signal A to the control circuit at the subsequent stage does not cause the processing circuit corresponding to the control circuit at the subsequent stage to start the operation, but the processing is performed depending on whether or not the FIFO memory (buffer) is full. You will decide to start. The advantage of this example is that the amount of processing determined by the capacity of the buffer is large, so that the time in which each processing circuit is in the waiting state is reduced, and the time can be used more effectively.

Further, for example, each processing circuit 11, 21, 31
It is also possible not to insert and connect a buffer (FIFO memory) between the two, and to connect the buffer only to the processing circuit where the processing time varies greatly. In the case of the example of FIG. 3 described above, since the processing time of the DCT in the DCT circuit 11 is constant, F between the DCT circuit 11 and the quantization circuit 21 is F.
The IFO memory 2 is removed and only the FIFO memory 3 between the quantization circuit 21 and the variable length coding circuit 31 is used. That is, in the case of this example, there is an advantage that the FIFO memory becomes smaller than that of the configuration of FIG. However, in this case, the request signal A from the control circuit 22 corresponding to the quantizing circuit 21 is sent to the configuration further upstream of the control circuit 12 corresponding to the DCT circuit 11, but in order to use the time effectively. In consideration of the processing delay in the DCT circuit 11, it is necessary to output the request signal A to be sent to the circuit configuration of the preceding stage of the DCT circuit 11 earlier.

When the configuration shown in FIG. 3 is actually realized, any one of the above three examples or a combination thereof may be used depending on whether the amount of hardware is reduced or the processing time is shortened. desirable.

FIG. 4 shows the control circuits 12 and 2 described above.
2 and 32 show more specific configuration examples.

Here, in FIG. 4, the request signal A from the control circuit at the preceding stage is supplied to the terminal 41,
The response signal R from the terminal 44 to the control circuit of the previous stage
Is output. Further, the terminal 43 is supplied with the response signal R from the control circuit in the subsequent stage, and the terminal 46 outputs the request signal A to the control circuit in the subsequent stage. Further, the processing operation end signal E from the processing circuit corresponding to the control circuit is supplied to the terminal 42, and the terminal 4
From 5, the processing operation start signal S is output to the processing circuit corresponding to the control circuit. For example, taking the control circuit 22 as an example, the request signal A _DCT from the control circuit 12 is supplied to the terminal 41,
From 4, the response signal R _Q to the control circuit 12 is output. Further, the response signal R _VLC from the control circuit 32 is supplied to the terminal 43, and the request signal A _Q to the control circuit 32 is output from the terminal 46. Further, the processing operation end signal E from the quantization circuit 21 is supplied to the terminal 42, and the processing operation start signal S to the quantization circuit 21 is output from the terminal 45.

The terminal 41 is connected to the input terminal of the NOT gate 51, and the output terminal of the NOT gate 51 is A
It is connected to one input terminal of the ND gate 52. The terminal 42 is connected to one input terminal of the OR gate 53,
The other input terminal of the OR gate 53 is connected to the output terminal of the AND gate 52. This OR gate 5
3 is connected to the input terminal of the flip-flop 54, and the output terminal of the flip-flop 54 is the terminal 4
4 and the other input terminal of the AND gate 52. Further, the terminal 41 is OR
It is connected to one input terminal of the gate 57, and the output terminal of the OR gate 57 is connected to the input terminal of the flip-flop 58. The output terminal of the flip-flop 58 is connected to one input terminal of the AND gate 59, and the other input terminal of the AND gate 59 is connected to the terminal 43. The output terminal of the AND gate 59 is connected to the terminals 45 and 46. Also, the above OR
The other input terminal of the gate 57 is connected to the output terminal of the AND gate 56 to which the output of the flip-flop 58 is supplied to one input terminal. Furthermore, this AN
The other input terminal of the D gate 56 is connected to the AND gate 5 described above.
The output of 9 is connected to the output terminal of the NOT gate 55 whose input terminal is supplied.

That is, in the configuration of FIG. 4, when the input of the terminal 42 is "H" (when the processing operation end signal E is supplied), the output of the OR gate 53 is "H".
Therefore, the output of the flip-flop 54 also becomes "H" (the response signal R is output to the control circuit at the preceding stage). Next, the input of the terminal 41 is "H".
If (when the pulse of the request signal A from the control circuit of the preceding stage is input), the output of the NOT gate 51 becomes "L", and therefore the output of the AND gate 52 also becomes "L". .. At this time, if the input to the terminal 42 is "L" (when the processing operation end signal E is not supplied), the flip-flop 54 also becomes "L" (response to the control circuit at the previous stage). Signal R
Is not output). Also, the input of the terminal 41 is "H".
At this time, the output of the OR gate 57 becomes "H", and therefore the output of the flip-flop 58 also becomes "H". At this time, if the input to the terminal 43 becomes "H" (if the response signal R is supplied from the control circuit at the latter stage), the output of the AND gate 59 becomes "H".
Therefore, the processing operation start signal S and the request signal A to the control circuit in the subsequent stage are output from the terminal 45. Further, if the input of the terminal 43 becomes "L" (when the response signal R from the control circuit in the subsequent stage is not supplied), the output of the AND gate 59 becomes "L". If the output of the AND gate 59 is "H", the output of the NOT gate 55 becomes "L" and the output of the AND gate 56 also becomes "L". At this time, if the input to the terminal 41 is "L", the output of the NOT gate 57 also becomes "L", and therefore the output of the flip-flop 58 also becomes "L".

That is, as shown in FIG. 4, each of the control circuits 12, 22, and 32 in FIG. 3 can be realized by only a simple gate circuit or flip-flop, so that the structure does not become large. ..

As described above, according to the high efficiency coding apparatus of this embodiment, the DCT processing area 10 and the quantization processing area 2 are provided.
0, of the processing areas of the variable length coding processing area 30, when the processing in the preceding processing area is completed, the request signal A is output from the preceding processing area to the subsequent processing area,
In response to the request signal A, the response signal R is sent from the subsequent processing region to the preceding processing region when the subsequent processing region is ready to start operation, that is, each processing region. By configuring so that the data exchange between them is performed at variable timing like the so-called handshake type, data processing can be performed independently between each processing area, and blocks (macro blocks) with a long processing time can be processed. Even if you come to the front and back buffer (FIFO
As long as there is a free space in the memories 2, 3), the process proceeds (if there is no free space, it will be in a waiting state). Therefore, it is possible to reduce the processing time of the entire high-efficiency coding apparatus of this embodiment.

Further, according to the present embodiment, since the utilization of time is improved, the processing time of the CPU is increased and it is possible to use an inexpensive CPU. Furthermore, each processing area is related only to the processing areas before and after,
A configuration that passes through the processing areas, such as so-called loopback, is unconditionally possible, and the timing generator for exchanging data is also common to the processing areas.
Furthermore, since each processing area (LSI) is wired only in the adjacent processing area, the layout when actually designing the board is also advantageous.

[0060]

As described above, in the high-efficiency coding apparatus of the present invention, the processing steps for compressing and coding the video signal have a plurality of processing areas for performing a plurality of processing steps, and the preceding processing When the processing in the area is completed, a request signal is output to the processing area in the subsequent stage, and when the processing area in the subsequent stage becomes ready to start operation in response to the request signal, a response signal is sent to the processing area in the previous stage. By sending the, it becomes possible to shorten the processing time of the entire high-efficiency coding apparatus without increasing the size of the configuration.

Further, according to the present invention, since the utilization of time is improved, it is possible to increase the margin in the processing time of the CPU and use an inexpensive CPU. Further, since each processing area is related only to the processing areas before and after, it is possible to unconditionally pass the processing areas like a so-called loopback, and the timing generator for exchanging data is also required. It is common to the processing areas. Furthermore, each processing area (for example, composed of an LSI or the like) is wired only in the adjacent processing area, so that the layout when actually designing the board is also advantageous.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a basic configuration of a high-efficiency encoding device according to an embodiment.

FIG. 2 is a timing chart showing the operation of each unit of the high efficiency coding apparatus according to the present embodiment.

FIG. 3 is a block circuit diagram showing a specific configuration of the high-efficiency encoding device according to the present embodiment.

FIG. 4 is a circuit diagram showing a specific configuration of a control circuit of a specific example.

5: H. It is a block circuit diagram which shows the structure of the high efficiency encoding device corresponding to the H.261 standard.

[Explanation of symbols]

 10: DCT processing area 20: Quantization processing area 30: Variable length coding processing area

Claims (1)

[Claims] 1. A high-efficiency coding apparatus having a plurality of processing regions in which a processing step of compressing and coding a video signal is divided into a plurality of steps, and processing of each of the divided steps is performed. Of the processing areas, when the processing in the processing area in the previous stage is completed, the request signal is output from the processing area in the preceding stage to the processing area in the subsequent stage, and the processing area in the subsequent stage operates in response to the request signal. A high-efficiency coding device, characterized in that a response signal is sent from the subsequent processing area to the preceding processing area when the processing can be started.