JPH0590929A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent fluctuation of a turn-on voltage and the increase of transmission delay time by providing a series connection circuit comprising a forward connection diode and a current limiting resistor between power supplies. CONSTITUTION:Power terminals VDD, VSS, an input terminal I and an output terminal O are connected to an internal circuit C and diodes D1-D4 are connected between the input terminal I and the outpout terminal O in opposite polarity. Moreover, a power supply Zener diode ZD5 whose reverse turn-on voltage is neawrly 10V and a series circuit comprising a forward diode D6 and a current limit resistor R are connected between the power terminals VDD, VSS. Thus, an overvoltage applied between the input terminal I and the output terminal O is clamped nearly at a maximum of 10.8V even when the circuit is compatible with live line insertion/removal. Then the increase in the fluctuation of the turn-on voltage and the transmission delay time is avoided due to the application of an overvoltage of nearly 20V and generation of hot carrier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in semiconductor integrated circuits. The present invention relates to a semiconductor integrated circuit that can effectively perform input and output without delay with respect to voltage stress of several tens of volts.

[0002]

2. Description of the Related Art Conventionally, the input and output of a semiconductor integrated circuit are constructed as shown in FIG. 4 (NEC high speed CMO).
S Digital IC Data Book 1990 pp 623).
This semiconductor integrated circuit includes an input terminal I and a power supply terminal V _DD ,
Reverse direction diodes D1 to D4 are connected between V _{SS and} between the output terminal O and the power supply terminals V _DD and V _SS , and the protection circuit IC
And OC are configured.

In the protection circuits IC and OC of this type, the diodes D1 and D2 of the protection circuit IC are OF since the voltage applied to the input terminal I is within the power supply voltage in a normal use state.
It is F and has no influence on the function of the integrated circuit. Further, when an overvoltage of several 100 V or more due to static electricity is applied between the power supply terminal V _SS and the input terminal I and the polarity thereof is negative, the forward ON voltage of the diode D1 is positive, and when the polarity is positive, (the forward ON voltage of D2 + Zener diode ZD5 for power supply protection
No voltage is applied to the circuit (gate of the MOS transistor) not shown in the figure that is clamped by the ON voltage in the opposite direction) and connected to the subsequent stage. The same applies when an overvoltage is applied between the power supply terminal V _DD and the input terminal I.

Recently, power off the board unit or chip unit for hot swapping and power saving, it is necessary to introduce, in the case shown in FIG. 3, when the power supply terminal V _DD becomes 0V diodes D2, D4 signal is In the case of H, there is a problem that the signal is turned on to lower the signal level, so that the configuration without the diodes D2 and D4 is used as shown in FIG. In this case, when an overvoltage is applied between the power supply terminal V _SS and the input terminal I, it is clamped by the forward or reverse ON voltage of the diode D1, and further the power supply terminal V _DD and the input terminal I.
When an overvoltage is applied between them, the applied voltage is clamped by the forward and reverse direction ON of the power protection Zener diode ZD5 and the diode D1.

[0005]

As described above, the conventional input and output protection circuit is effective against static electricity of several hundreds of volts or more, but as the MOS transistor becomes finer, the voltage of several tens of volts is applied to the input terminal. Is applied and clamped by the reverse ON voltage of the protection diode (for example, 20 V), the miniaturized MOS transistor generates hot carriers at this voltage, which causes fluctuations in the turn-on voltage V _T and increases the transmission delay time. I have a problem to do.

The present invention solves such a problem, and it is possible to prevent the turn-on voltage V _T from fluctuating and the propagation delay time from increasing due to the generation of hot carriers due to the application of overvoltage. An object is to provide an integrated circuit.

[0007]

According to the present invention, there is provided a semiconductor integrated circuit having an input protection circuit and an output protection circuit between an input terminal and an output terminal, and a power supply protection circuit having one Zener diode between the power supply terminals. In the circuit, the power supply protection circuit includes a series connection circuit of a forward diode and a current limiting resistor connected in parallel to the Zener diode.

Each of the input protection circuit and the output protection circuit is composed of two diodes each connected in series and the connection point of which is connected to the input or the output. It can be composed of two Zener diodes.

[0009]

When a negative voltage is applied to the input terminal I with respect to the power supply terminal V _{SS of the} circuit shown in FIG. 1, the diode D1 is clamped at an ON voltage of about 0.8 V in the forward direction and a positive voltage is applied. In the forward direction of diodes D2 and D6,
It is clamped at an ON voltage of about 0.8V.

When a negative voltage is applied to the input terminal I with respect to the power supply terminal V _DD , the diodes D6 and D1 are clamped at an ON voltage of about 2 × 0.8 V in the forward direction to add a positive voltage. If it is, the diode D2 is clamped at an ON voltage of about 0.8 V in the forward direction.

Therefore, if the output impedance of the overvoltage source is made sufficiently larger than that of the current limiting resistor R, it is possible to suppress the generation of hot carriers only by adding a maximum voltage of about 1.6 V to the internal circuit C. Therefore, it is possible to suppress the variation of the turn-on voltage V _T of the field effect transistor connected to the subsequent stage and the increase of the transmission delay time.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention. Power supply terminals V _DD and V _SS , an input terminal I and an output terminal O are connected to the internal circuit C in the first embodiment of the present invention. Input terminal I and output terminal O and power supply terminal V _DD
Diodes D1 to D4 are connected in the reverse direction between V _SS and V _SS . Further, a power supply protection Zener diode ZD5 having a reverse ON voltage of about 10 V is connected, and a series connection circuit of a power supply forward diode D6 and a current limiting resistor R is provided between the power supply terminals V _DD and V _SS. .

When an overvoltage of several tens of volts is applied from the input terminal I of the MOS transistor to the power supply terminal V _SS , the direction opposite to D1 is applied between the source (V _SS ) and gate of the MOS transistor Q2 shown in FIG. The voltage is not clamped up to the ON voltage (for example, 20 V) of the above and is applied as it is.

When the MOS transistor is miniaturized, the gate oxide film also becomes thinner, so that the electric field between the gate and the source increases and carriers are accelerated and trapped in the oxide film. In the case of a MOS transistor, the conduction of carriers is governed by the electric field on the silicon surface, so that it is affected by the electric field generated by the fixed charges in the oxide film. For example, when electrons are trapped, it is necessary to add an extra positive voltage to the input terminal I in order to cancel the electric field caused by the electrons.

Further, when the change in the turn-on voltage V _T becomes large, even if the input terminal I is set to the high level, the MOS transistor Q2 will not be turned on because the ON resistance becomes extremely larger than usual. When this happens,
The delay time increases as shown in the equivalent circuit.

The operation of the input protection circuit IC when an overvoltage is applied to the circuit of the embodiment of the present invention will now be described. When a negative voltage is applied to the input terminal I with respect to the power supply terminal V _SS , the forward ON voltage of the diode D1 (0.8 V
When a positive voltage is applied to the input terminal I with respect to the power supply terminal V _SS , the diodes D2 and D6 are clamped.
The forward ON voltage (about 2 × 0.8 V) is clamped.

When a negative voltage is applied to the input terminal I with respect to the power supply terminal V _DD , the diodes D6 and D1 are clamped by the forward ON voltage (about 2 × 0.8 V) to the power supply terminal V _DD . On the other hand, when a positive voltage is applied to the input terminal I, the diode D2 is clamped by the forward ON voltage (about 0.8 V). Therefore, if the output impedance of the overvoltage source is set sufficiently higher than that of the current limiting resistor R, only a maximum voltage of about 1.6 V is applied to the internal circuit C. On the other hand, in the case of the conventional example shown in FIG. 4, the voltage of the maximum diode forward ON voltage (about 0.8 V) + the reverse ON voltage of the power source protection zener diode ZD5 (about 10 V) is applied.

FIG. 2 is a circuit diagram showing the configuration of the second embodiment of the present invention. The second embodiment of the present invention includes diodes D2 and D4.
Was removed to support hot swapping, and diode D
1 and D3 are replaced by Zener diodes ZD1 and ZD3 having a reverse ON voltage of about 10V.

When an overvoltage is applied to the input terminal I and a negative voltage is applied to the input terminal I with respect to the power supply terminal V _SS , the forward ON voltage (0.8V) of the Zener diode ZD1.
When a positive voltage is applied to the input terminal I with respect to the power supply terminal V _SS , the zener diode Z
It is clamped by the reverse ON voltage (about 10V) of D1.

When a negative voltage is applied to the input terminal I with respect to the power supply terminal V _DD , the forward ON voltage of the diode D6 and the zener diode ZD1 (about 2 × 0.8 V)
When a positive voltage is applied to the input terminal I with respect to the power supply terminal V _DD , it is clamped by the forward voltage of the diode D6 (about 0.8V) + the reverse ON voltage of the Zener diode ZD1 (about 10V). To be done. That is, only a maximum voltage of about 10.8 V is applied to the internal circuit C. On the other hand, in the case of the conventional example shown in FIG. 5, the reverse ON voltage (about 20V) of the maximum diode D1 + the forward ON voltage of ZD5 (about 0.8V) is applied.

[0021]

As described above, according to the present invention, the configuration is such that the overvoltage applied to the input terminal and the output terminal is clamped at a maximum of about 10.8 V even when hot plugging / unplugging is supported. It is possible to prevent an increase in the V _{T and} an increase in the transmission delay time due to the generation of hot carriers due to the addition of an overvoltage of about 20 V.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a diagram for explaining changes in delay time due to turn-on voltage fluctuations.

FIG. 4 is a circuit diagram showing a configuration of a conventional example.

FIG. 5 is a circuit diagram showing the configuration of another conventional example.

[Explanation of symbols]

C Internal circuit I Input terminal O Output terminal V _DD , V _SS Power supply terminal IC Input protection circuit OC Output protection circuit D1, D2, D3, D4, D6 Diode ZD5 Power supply protection Zener diode R Current limiting resistor ZD1, ZD3 Zener diode

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[Procedure amendment]

[Submission date] September 30, 1991

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

Claims (3)

[Claims] 1. A semiconductor integrated circuit comprising an input protection circuit and an output protection circuit between an input terminal and an output terminal, and a power supply protection circuit having one Zener diode between power supply terminals. A semiconductor integrated circuit comprising a series connection circuit of a forward diode and a current limiting resistor connected in parallel to the Zener diode. 2. The semiconductor integrated circuit according to claim 1, wherein each of the input protection circuit and the output protection circuit is composed of two diodes, each of which is connected in series and whose connection point is connected to an input or an output. 3. The semiconductor integrated circuit according to claim 1, wherein each of the input protection circuit and the output protection circuit is composed of one Zener diode.