JPH0590699A - Manufacture of multiple-wavelength semiconductor laser device - Google Patents

Manufacture of multiple-wavelength semiconductor laser device

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Publication number
JPH0590699A
JPH0590699A JP24934991A JP24934991A JPH0590699A JP H0590699 A JPH0590699 A JP H0590699A JP 24934991 A JP24934991 A JP 24934991A JP 24934991 A JP24934991 A JP 24934991A JP H0590699 A JPH0590699 A JP H0590699A
Authority
JP
Japan
Prior art keywords
layer
stripe
stop layer
width
etching stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP24934991A
Other languages
Japanese (ja)
Inventor
Iwao Komazaki
岩男 駒崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP24934991A priority Critical patent/JPH0590699A/en
Publication of JPH0590699A publication Critical patent/JPH0590699A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To obtain a multiple-wavelength semiconductor laser device having a low threshold, the degree of freedom of an oscillation wavelength, a high output and a clean buried interface by forming striped grooves having different width and depth. CONSTITUTION:Masks having striped opening sections having different width are formed onto a substrate 31 through a first etching stop layer 33, a growth layer 34, a second etching stop layer 35 and a non-doped growth layer 36. Each growth layer 34, 36 and the second stop layer 35 are vapor-phase etched, and striped grooves reaching the first and second stop layers 33, 35 and having different width and depth are formed. A lower clad layer 39, quantum well active layers 40,44, an upper clad layer 41 and cap layers 42, 46 are shaped successively into the striped grooves, and Ga ions are implanted up to the second stop layer 35 at positions except regions corresponding to the width of the striped grooves. Lastly, electrodes 48, 49a, 49b connected to the cap layers 42, 46 in each striped groove are formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、情報処理用の多波長半
導体レ−ザ装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multiwavelength semiconductor laser device for information processing.

【0002】[0002]

【従来の技術】周知の如く、光記録分野の波長多重化に
よる記録密度の向上等、半導体レ−ザに求められる機能
として、高性能な波長可変機能が重要である。
2. Description of the Related Art As is well known, a high-performance wavelength tunable function is important as a function required of a semiconductor laser such as an improvement in recording density by wavelength multiplexing in the field of optical recording.

【0003】ところで、波長を可変にする半導体レ−ザ
装置として、例えば図7に示すものが知られている(特
開平1−276686号)。図中の1は、n型のGaA
s基板である。この基板1上には、2つの異なる幅を有
し,断面が逆テ−パ状の第1溝2a,第2溝2bを有し
た電流ブロック層3が形成されている。前記第1溝2a
の前記基板1上には、n型のAI0.3 Ga0.7Asクラ
ッド層(下クラッド層)4,量子井戸活性層5,p型の
AI0.3 Ga0.7 Asクラッド層(上クラッド層)6及
びp+ 型のGaAsキャップ層7が順次形成されてい
る。前記第2溝2bの前記基板1上には、n型のAI
0.3 Ga0.7 Asクラッド層(下クラッド層)8,量子
井戸活性層9,p型のAI0.3 Ga0.7 Asクラッド層
(上クラッド層)10及びp+ 型のGaAsキャップ層11
が順次形成されている。前記キャップ層7及び電流ブロ
ック層3の一部上にはp側電極12aが形成され、前記キ
ャップ層11及び電流ブロック層3の一部上にはp側電極
12bが形成されている。前記基板1の裏面にはn側電極
13が形成されている。次に、図7の構成のレ−ザ装置の
動作について説明する。
By the way, as a semiconductor laser device for changing the wavelength, for example, one shown in FIG. 7 is known (Japanese Patent Laid-Open No. 1-276686). 1 in the figure is n-type GaA
s substrate. On this substrate 1, there is formed a current block layer 3 having two different widths and having a first groove 2a and a second groove 2b having a reverse tapered cross section. The first groove 2a
On the substrate 1, the n-type AI 0.3 Ga 0.7 As clad layer (lower clad layer) 4, the quantum well active layer 5, the p-type AI 0.3 Ga 0.7 As clad layer (upper clad layer) 6 and p + Type GaAs cap layer 7 is sequentially formed. An n-type AI is formed on the substrate 1 in the second groove 2b.
0.3 Ga 0.7 As clad layer (lower clad layer) 8, quantum well active layer 9, p-type AI 0.3 Ga 0.7 As clad layer (upper clad layer) 10 and p + Type GaAs cap layer 11
Are sequentially formed. A p-side electrode 12a is formed on a part of the cap layer 7 and the current blocking layer 3, and a p-side electrode is formed on a part of the cap layer 11 and the current blocking layer 3.
12b is formed. An n-side electrode is provided on the back surface of the substrate 1.
13 are formed. Next, the operation of the laser device configured as shown in FIG. 7 will be described.

【0004】まず、レ−ザ装置に電流注入を行なうと、
前記量子井戸活性層5では活性層幅が狭いために縦モ−
ドは量子準位の0次が飽和し、縦モ−ドが量子準位の1
次で発振する。そのため、高エネルギ側,つまり短波長
で発振する。
First, when current is injected into the laser device,
In the quantum well active layer 5, since the active layer width is narrow, the vertical mode is
Mode, the 0th order of the quantum level is saturated, and the vertical mode is 1 of the quantum level.
It oscillates at the next. Therefore, it oscillates on the high energy side, that is, at a short wavelength.

【0005】一方、他方の量子井戸活性層9は、普通に
縦モ−ドが量子準位の0次で発振する。例えば、量子井
戸活性層5の幅を1μmとし、量子井戸活性層9の幅を
2μmとし、量子井戸幅を10nmとすれば、発振波長
が量子井戸活性層5では810nm,量子井戸活性層9
では840nmで約30nmの波長差が得られ、しきい
値電流は1次準位発振の方が0次に比べ3割り程度上昇
する。
On the other hand, in the other quantum well active layer 9, the longitudinal mode normally oscillates in the 0th order of the quantum level. For example, if the width of the quantum well active layer 5 is 1 μm, the width of the quantum well active layer 9 is 2 μm, and the quantum well width is 10 nm, the oscillation wavelength is 810 nm in the quantum well active layer 5, and the quantum well active layer 9 is
, A wavelength difference of about 30 nm is obtained at 840 nm, and the threshold current in the first level oscillation is increased by about 30% in comparison with the zero order.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、従来の
レ−ザ装置は、量子井戸幅が同一であるため、量子準位
の0次と1次を利用するしかないため、その波長の自由
度は限定される。また、量子準位を1次,2次と高次準
位を利用すると、発振波長は短波長になるが、動作電流
が上昇してしまう。特に、高出力にする場合、高次準位
の発振では、発振波長がさらに高次へ移行するために出
力効率が低下する。
However, since the conventional laser device has the same quantum well width, it has no choice but to use the 0th order and the 1st order of the quantum levels. Limited. Further, if the quantum levels of 1st order and 2nd order and higher levels are used, the oscillation wavelength becomes short, but the operating current increases. In particular, when the output is high, in the oscillation of a high level, the oscillation wavelength shifts to a higher level, so that the output efficiency decreases.

【0007】一方、ストライプ幅を1μm,2μmと狭
窄化する場合、再成長埋込み時に、再成長界面の結晶が
劣化し、界面に沿って流れる漏れ電流量が増加する。ま
た、活性層幅が狭いため、両側の結晶の劣化が内部に広
がり、信頼性を著しく劣化させる。
On the other hand, when the stripe width is narrowed to 1 μm or 2 μm, the crystal at the regrowth interface is deteriorated during regrowth filling, and the amount of leakage current flowing along the interface increases. In addition, since the width of the active layer is narrow, the deterioration of the crystals on both sides spreads inside, which significantly deteriorates the reliability.

【0008】本発明は上記事情に鑑みてなされたもの
で、低しきい値で発振波長自由度が有り、かつ高出力で
埋込み界面がクリ−ンな多波長半導体レ−ザ装置を提供
することを目的とする。
The present invention has been made in view of the above circumstances, and provides a multi-wavelength semiconductor laser device having a low threshold value, oscillation wavelength freedom, high output, and a clean buried interface. With the goal.

【0009】[0009]

【課題を解決するための手段】本発明は、化合物半導体
基板上に第1エッチングストップ層,不純物を含有した
成長層,第2エッチングストップ層及びノンド−プ成長
層を介して異なる幅を有したストライプ状の開口部を有
するマスクを形成する工程と、前記マスクを用いて前記
各成長層及び第2エッチングストップ層を気相エッチン
グし、第1・第2エッチングストップ層に達し,ストラ
イプ幅及び深さが互いに異なるストライプ溝を形成する
工程と、前記ストライプ溝内に下クラッド層,量子井戸
活性層,上クラッド層及びキャップ層を順次形成する工
程と、前記ストライプ溝内の各層の実効的な幅に対応す
る領域を除く箇所にGaイオンを第2エッチングストッ
プ層まで注入する工程と、前記各ストライプ溝内の前記
キャップ層に接続する電極を夫々形成する工程とを具備
することを特徴とする多波長半導体レ−ザ装置の製造方
法である。
The present invention has different widths on a compound semiconductor substrate through a first etching stop layer, a growth layer containing impurities, a second etching stop layer and a non-doped growth layer. A step of forming a mask having a stripe-shaped opening, and vapor-phase etching each growth layer and the second etching stop layer using the mask to reach the first and second etching stop layers, and stripe width and depth. Forming stripe grooves having different widths, sequentially forming a lower clad layer, a quantum well active layer, an upper clad layer and a cap layer in the stripe grooves, and an effective width of each layer in the stripe grooves. A step of implanting Ga ions up to the second etching stop layer in a region other than the region corresponding to, and connecting to the cap layer in each stripe groove. Multiwavelength semiconductor laser characterized by comprising a step of electrodes respectively formed that - a method of manufacturing the laser device.

【0010】[0010]

【作用】本発明において、第1・第2エッチングストッ
プ層を含むウェハの表面にa−Si膜又はSiO2 膜の
極薄膜を形成し、Ga+ イオンビ−ム又は電子ビ−ムを
μm以下に絞って直接パタ−ニングすると、物理的なス
パッタを同じ作用で窓開けができる(図2参照)。その
後、図8のようにAs雰囲気中でHCIガスで気相エッ
チングすると、AI組成によりエッチング速度の選択性
が生じる。この効果と、マスクの窓の幅によりエッチン
グの深さが異なる。この状態でジメチルガリウムクロラ
イド(DMGaCI)を含むMOVPEで、ストライプ
溝内にダブルヘテロ接合構造を選択的に形成する。この
時、溝の深さが深いと成長速度が早く、つまり量子井戸
幅が厚くなる(図4参照)。
In the present invention, an extremely thin film of a-Si film or SiO 2 film is formed on the surface of the wafer including the first and second etching stop layers, and Ga + If the ion beam or the electron beam is narrowed down to less than μm and directly patterned, physical spattering can be performed by the same action (see FIG. 2). Then, as shown in FIG. 8, when vapor phase etching is performed with HCI gas in an As atmosphere, selectivity of the etching rate occurs due to the AI composition. The etching depth varies depending on this effect and the width of the window of the mask. In this state, MOVPE containing dimethylgallium chloride (DMGaCI) is used to selectively form a double heterojunction structure in the stripe groove. At this time, if the depth of the groove is large, the growth rate is high, that is, the quantum well width is large (see FIG. 4).

【0011】そして、ストライプ幅及び深さを変えるこ
とにより、量子井戸幅を変化させることができ、実効的
な活性層幅はGa+ イオンビ−ムをウェハ表面から注入
して、幅を制御する。これら一連のプロセスは、炉内で
の一貫プロセスのために例えば通常再成長する場合に
は、下部クラッド層を比較的に厚く成長させて、酸化,
歪を緩和させる必要があるが、本発明のプロセスでは、
直接下部クラッド層無しで光導波路層を形成することも
可能であり、素子の信頼性が優れている。
The quantum well width can be changed by changing the stripe width and the depth, and the effective active layer width is Ga +. Ion beams are implanted from the wafer surface to control the width. For a series of processes in the furnace, for example, when re-growing normally, a lower clad layer is grown to be relatively thick, and oxidation,
Although strain needs to be mitigated, the process of the present invention
It is possible to directly form the optical waveguide layer without the lower clad layer, and the device has excellent reliability.

【0012】[0012]

【実施例】以下、本発明の一実施例に係る多波長半導体
レ−ザ装置の製造方法について図1〜図6を参照して説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a multiwavelength semiconductor laser device according to an embodiment of the present invention will be described below with reference to FIGS.

【0013】(1) まず、(100)n型GaAs基板31
上に、MOVPE技術により、n型AI0.5 Ga0.5
s層32、n型AI0.3 Ga0.7 Asエッチングストップ
層(以下、第1ストップ層と呼ぶ)33、n型GaAs層
34、n型AI0.5 Ga0.5Asエッチングストップ層
(以下、第2ストップ層と呼ぶ)35、及びノンド−プG
aAs層36を順次成長させた。ここで、前記AI0.5
0.5 As層32はSiド−プ,不純物濃度1×1017cm-3
で厚み2.0μm、第1ストップ層33はSiド−プ,不
純物濃度1×1017cm-3で厚み0.1μm、n型GaAs
層34はSiド−プ,不純物濃度1×1018cm-3で厚み0.
4μm、第2ストップ層35の厚み0.05μm、ノンド
−プGaAs層36の厚みは1.6μmである。つづい
て、前記ノンド−プGaAs層36上に、プラズマCVD
により厚さ3nmのa−Si膜37を成長した(図1)。
(1) First, a (100) n-type GaAs substrate 31
N-type AI 0.5 Ga 0.5 A by MOVPE technology
s layer 32, n-type AI 0.3 Ga 0.7 As etching stop layer (hereinafter referred to as the first stop layer) 33, n-type GaAs layer
34, n-type AI 0.5 Ga 0.5 As etching stop layer (hereinafter referred to as a second stop layer) 35, and non-doped G
The aAs layer 36 was sequentially grown. Here, the AI 0.5 G
a 0.5 As layer 32 is made of Si and has an impurity concentration of 1 × 10 17 cm -3
The thickness is 2.0 μm, the first stop layer 33 is Si-doped, the impurity concentration is 1 × 10 17 cm −3 , the thickness is 0.1 μm, and the n-type GaAs is
Layer 34 is Si de - flop, the thickness at an impurity concentration of 1 × 10 18 cm -3 0.
4 μm, the thickness of the second stop layer 35 is 0.05 μm, and the thickness of the non-doped GaAs layer 36 is 1.6 μm. Subsequently, plasma CVD is performed on the non-doped GaAs layer 36.
Then, an a-Si film 37 having a thickness of 3 nm was grown (FIG. 1).

【0014】(2) 次に、前記a−Si膜37上に、集束G
aイオンビ−ム(加速電圧20KeV,ド−ズ量5×1014
cm-2)で、幅(W1 )4μm,幅(W2 )8μmの平行
するストライプを間隔80μmで直接描画する(図
2)。
(2) Next, a focusing G is formed on the a-Si film 37.
a ion beam (accelerating voltage 20 KeV, dose amount 5 × 10 14
cm −2 ), parallel stripes having a width (W 1 ) of 4 μm and a width (W 2 ) of 8 μm are directly drawn at intervals of 80 μm (FIG. 2).

【0015】(3) 次に、窓の開いたウェハをMOVPE
炉へ移動させ、850℃でAs圧下でHCIガスでエッ
チングした。エッチング深さは、狭いストライプの深さ
が第2ストップ層35で止まる深さとする。この場合、広
いストライプでは、オ−バ−エッチングにより第2スト
ップ層35はエッチング除去され、エッチング速度が早い
n型GaAs層34を除去し、第1ストップ層33で止まる
(図3)。なお、図中の38aを狭いストライプ溝、38b
を広いストライプ溝を示す。
(3) Next, the wafer with the window opened is subjected to MOVPE.
It was transferred to a furnace and etched with HCI gas at 850 ° C. under As pressure. The etching depth is the depth at which the narrow stripe depth stops at the second stop layer 35. In this case, in a wide stripe, the second stop layer 35 is removed by over-etching, the n-type GaAs layer 34 having a high etching rate is removed, and the second stop layer 35 stops at the first stop layer 33 (FIG. 3). In the figure, 38a is a narrow stripe groove, 38b
Shows a wide stripe groove.

【0016】(4) 次に、MOVPE炉内温度を700℃
の成長温度に下げ、成長圧力10Torr 以下で続いて溝
内にDEGaCIを含むMOVPE法でダブルヘテロ構
造を成長する。つまり、以下に述べるように、狭いスト
ライプ溝内で層厚を制御する。
(4) Next, the temperature inside the MOVPE furnace is set to 700 ° C.
At a growth temperature of 10 Torr or less, and then a double heterostructure is grown in the groove by the MOVPE method including DEGaCI. That is, as described below, the layer thickness is controlled within the narrow stripe groove.

【0017】最初、狭いストライプ溝38a内へ、n型A
0.45Ga0.55Asクラッド層(以下、下部クラッド層
と呼ぶ)39、活性層40、p型AI0.45Ga0.55Asクラ
ッド層(以下、上部クラッド層と呼ぶ)41、及びp+
GaAsキャップ層42を選択的に成長させた。但し、前
記下部クラッド層39はSiド−プ,不純物濃度1×1017
cm-3で厚み0.4μm、活性層40は量子井戸幅5nmの
GaAs,AIAsバリア幅5nmを2周期、上部クラ
ッド層41はMgド−プ,不純物濃度7×1017cm-3で厚み
0.4μmである。
First, the n-type A is inserted into the narrow stripe groove 38a.
I 0.45 Ga 0.55 As clad layer (hereinafter referred to as lower clad layer) 39, active layer 40, p-type AI 0.45 Ga 0.55 As clad layer (hereinafter referred to as upper clad layer) 41, and p + A type GaAs cap layer 42 was selectively grown. However, the lower clad layer 39 is made of Si and has an impurity concentration of 1 × 10 17
cm -3 with a thickness 0.4 .mu.m, the active layer 40 is GaAs quantum well width 5 nm, 2 cycle AIAs barrier width 5 nm, an upper clad layer 41 of Mg-de - flop, the thickness at an impurity concentration of 7 × 10 17 cm -3 0 It is 0.4 μm.

【0018】ここで、10Torr 以下の減圧下での選択
成長において、溝幅10μm以下で深さが1.5μm以
上では成長速度が深さが1μm以下に比べて1.5 〜2.0
倍と早い。本発明では、この性質を利用して狭いストラ
イプ溝38a内への選択埋込み成長時の成長層厚みを可変
にしている。従って、広いストライプ溝38b内での各層
厚パラメ−タは次のようになる。
In the selective growth under reduced pressure of 10 Torr or less, when the groove width is 10 μm or less and the depth is 1.5 μm or more, the growth rate is 1.5 to 2.0 as compared with the depth of 1 μm or less.
It is twice as fast. In the present invention, by utilizing this property, the thickness of the growth layer at the time of selective burying growth in the narrow stripe groove 38a is made variable. Therefore, the layer thickness parameters in the wide stripe groove 38b are as follows.

【0019】即ち、n型AI0.45Ga0.55As層43は
0.6〜0.8μm、活性層44はGaAs量子井戸幅8
nm,AIAsバリア幅8nmとなり、p型AI0.45
0.55Asクラッド層45は1μm、最後のp+ 型GaA
sキャップ層46の厚さは変わらず0.4μmとなる(図
4)。
That is, the n-type AI 0.45 Ga 0.55 As layer 43 is 0.6 to 0.8 μm, and the active layer 44 is the GaAs quantum well width 8
nm, AIAs barrier width becomes 8 nm, and p-type AI 0.45 G
a 0.55 As clad layer 45 is 1 μm, the last p + Type GaA
The thickness of the s-cap layer 46 remains 0.4 μm (FIG. 4).

【0020】(5) 次に、SiO2 からなる絶縁膜47を厚
み500nm選択パタ−ニングし、ストライプ中央部の
み幅2μm残した。つづいて、前記絶縁膜47の上方より
Ga+ イオンビ−ム(ド−ズ量4×1014cm-2)を第1ス
トップ層33まで注入した(図5)。
(5) Next, the insulating film 47 made of SiO 2 was selectively patterned to a thickness of 500 nm, leaving a width of 2 μm only in the central portion of the stripe. Then, from above the insulating film 47, Ga + Ion beams (dose amount 4 × 10 14 cm -2 ) were injected up to the first stop layer 33 (FIG. 5).

【0021】(6) 次に、前記絶縁膜47を除去した後、前
記基板31の裏面にp側電極48を形成した。つづいて、ノ
ンド−プGaAs層36及びキャップ層42,46上にp側電
極49を形成した。更に、前記p側電極49を絶縁膜50で2
分割してp側電極49a,49bとし、2素子からなる多波
長半導体レ−ザを製造した(図6)。
(6) Next, after removing the insulating film 47, a p-side electrode 48 is formed on the back surface of the substrate 31. Subsequently, a p-side electrode 49 was formed on the non-doped GaAs layer 36 and the cap layers 42 and 46. Further, the p-side electrode 49 is formed of an insulating film 50.
Divided into p-side electrodes 49a and 49b, a multiwavelength semiconductor laser composed of two elements was manufactured (FIG. 6).

【0022】こうして得られた多波長半導体レ−ザ装置
の動作は、次に述べる通りである。つまり、p側電極49
a,49bより注入されたキャリアは、Ga+ イオン注入
領域(図6の点々領域)が高抵抗領域となっているた
め、活性層40,44へ流れ込む。これらの活性層で、キャ
リアの再結合により生じた光は、活性層の両サイドが無
秩序化により屈折率が低下しているために、水平横方向
に拡がり、光吸収されることが小さく、共振器端面で光
帰還を繰り返し、光増幅,やがてレ−ザ発振が生じる。
The operation of the thus obtained multi-wavelength semiconductor laser device is as follows. That is, the p-side electrode 49
Carriers injected from a and 49b are Ga + Since the ion implantation region (dotted region in FIG. 6) is a high resistance region, it flows into the active layers 40 and 44. In these active layers, the light generated by recombination of carriers spreads horizontally and laterally because the refractive index is lowered due to disordering on both sides of the active layer, so that light absorption is small and resonance occurs. Optical feedback is repeated on the end face of the device, optical amplification is performed, and laser oscillation eventually occurs.

【0023】しかして、上記実施例によれば、量産性,
制御性に優れたMOVPE技術を利用でき、集束イオン
ビ−ム直接描画,HCIガスによる気相エッチングでス
トライプ溝38a,38bを形成した後、それに続くダブル
ヘテロ接合構造の選択成長とで一貫プロセスが可能であ
る。従って、空気中にウェハをさらすことがなく、連続
してプロセスが流れるため、再成長によって生じる結晶
界面の劣化を防止できる。
However, according to the above embodiment, mass productivity,
MOVPE technology with excellent controllability can be used. Focused ion beam direct writing, stripe grooves 38a and 38b are formed by vapor-phase etching with HCI gas, and then a selective process of double heterojunction structure is possible. Is. Therefore, since the process flows continuously without exposing the wafer to the air, deterioration of the crystal interface caused by regrowth can be prevented.

【0024】[0024]

【発明の効果】以上詳述した如く本発明によれば、低し
きい値で発振波長自由度が有り、かつ高出力で埋込み界
面がクリ−ンな多波長半導体レ−ザ装置を提供できる。
As described above in detail, according to the present invention, it is possible to provide a multi-wavelength semiconductor laser device having a low threshold value, oscillation wavelength freedom, high output, and a clean buried interface.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る多波長半導体レ−ザ装
置の製造方法に一工程を示すもので、基板上に各成長層
を形成した状態を示す断面図。
FIG. 1 is a cross-sectional view showing a state in which each growth layer is formed on a substrate, showing one step in a method for manufacturing a multiwavelength semiconductor laser device according to an embodiment of the present invention.

【図2】本発明の一実施例に係る多波長半導体レ−ザ装
置の製造方法に一工程を示すもので、集束Gaイオンビ
−ムで所定の幅を有するストライプを描画した状態を示
す断面図。
FIG. 2 is a cross-sectional view showing a step in a method of manufacturing a multi-wavelength semiconductor laser device according to an embodiment of the present invention, showing a state in which stripes having a predetermined width are drawn with a focused Ga ion beam. ..

【図3】本発明の一実施例に係る多波長半導体レ−ザ装
置の製造方法に一工程を示すもので、HCIガスを用い
てストライプ溝を形成した状態を示す断面図。
FIG. 3 is a cross-sectional view showing a step of a method for manufacturing a multi-wavelength semiconductor laser device according to an embodiment of the present invention, in which stripe grooves are formed using HCI gas.

【図4】本発明の一実施例に係る多波長半導体レ−ザ装
置の製造方法に一工程を示すもので、ストライプ溝内に
各成長層を形成した状態を示す断面図。
FIG. 4 is a cross-sectional view showing a step of a method for manufacturing a multi-wavelength semiconductor laser device according to an embodiment of the present invention, showing a state in which each growth layer is formed in a stripe groove.

【図5】本発明の一実施例に係る多波長半導体レ−ザ装
置の製造方法に一工程を示すもので、実効的な活性層幅
を制御する目的から所定の領域Gaイオンを注入した状
態を示す断面図。
FIG. 5 shows one step in a method of manufacturing a multi-wavelength semiconductor laser device according to an embodiment of the present invention, in which Ga ions are implanted in a predetermined region for the purpose of controlling the effective active layer width. FIG.

【図6】本発明の一実施例に係る多波長半導体レ−ザ装
置の製造方法に一工程を示すもので、基板の裏面,表面
側に夫々電極を形成した状態を示す断面図。
FIG. 6 is a cross-sectional view showing a step in a method for manufacturing a multi-wavelength semiconductor laser device according to an embodiment of the present invention, showing a state in which electrodes are formed on the back surface and the front surface side of a substrate respectively.

【図7】従来の多波長半導体レ−ザ装置の断面図。FIG. 7 is a sectional view of a conventional multi-wavelength semiconductor laser device.

【図8】図2でHCIガスを用いて各成長層をエッチン
グした場合のエッチング深さとエッチング時間との関係
を示す特性図。
FIG. 8 is a characteristic diagram showing the relationship between etching depth and etching time when etching each growth layer in FIG. 2 using HCI gas.

【符号の説明】[Explanation of symbols]

31…n型GaAs基板、32…n型AI0.5 Ga0.5 As
層、33…第1ストップ層、34…n型GaAs層、35…第
2ストップ層、36…ノンド−プGaAs層、37…a−
Si膜、38a,38b…ストライプ溝、39…下部クラッ
ド層、40,44…活性層、41…上部クラッド層、42,46…
+ 型GaAsキャップ、43…n型AI0.45Ga0.55
s層、45…p型AI0.45Ga0.55Asクラッド層、47…
絶縁膜、48…n側電極、49a,49b…p側電極。
31 ... n-type GaAs substrate, 32 ... n-type AI 0.5 Ga 0.5 As
Layer 33 ... first stop layer 34 ... n-type GaAs layer 35 ... second stop layer 36 ... non-doped GaAs layer 37 ... a-
Si film, 38a, 38b ... Stripe groove, 39 ... Lower clad layer, 40, 44 ... Active layer, 41 ... Upper clad layer, 42, 46 ...
p + Type GaAs cap, 43 ... n type AI 0.45 Ga 0.55 A
s layer, 45 ... p-type AI 0.45 Ga 0.55 As clad layer, 47 ...
Insulating film, 48 ... N-side electrode, 49a, 49b ... P-side electrode.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 化合物半導体基板上に第1エッチングス
トップ層,不純物を含有した成長層,第2エッチングス
トップ層及びノンド−プ成長層を介して異なる幅を有し
たストライプ状の開口部を有するマスクを形成する工程
と、前記マスクを用いて前記各成長層及び第2エッチン
グストップ層を気相エッチングし、第1・第2エッチン
グストップ層に達し,ストライプ幅及び深さが互いに異
なるストライプ溝を形成する工程と、前記ストライプ溝
内に下クラッド層,量子井戸活性層,上クラッド層及び
キャップ層を順次形成する工程と、前記ストライプ溝内
の各層の実効的な幅に対応する領域を除く箇所にGaイ
オンを第2エッチングストップ層まで注入する工程と、
前記各ストライプ溝内の前記キャップ層に接続する電極
を夫々形成する工程とを具備することを特徴とする多波
長半導体レ−ザ装置の製造方法。
1. A mask having stripe-shaped openings having different widths on a compound semiconductor substrate through a first etching stop layer, a growth layer containing impurities, a second etching stop layer and a non-doped growth layer. And forming a stripe groove in which the growth layers and the second etching stop layer are vapor-phase etched using the mask to reach the first and second etching stop layers and stripe widths and depths are different from each other. And a step of sequentially forming a lower clad layer, a quantum well active layer, an upper clad layer and a cap layer in the stripe groove, and a step except a region corresponding to the effective width of each layer in the stripe groove. Implanting Ga ions to the second etching stop layer,
And a step of forming an electrode connected to the cap layer in each of the stripe grooves, respectively.
JP24934991A 1991-09-27 1991-09-27 Manufacture of multiple-wavelength semiconductor laser device Withdrawn JPH0590699A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24934991A JPH0590699A (en) 1991-09-27 1991-09-27 Manufacture of multiple-wavelength semiconductor laser device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24934991A JPH0590699A (en) 1991-09-27 1991-09-27 Manufacture of multiple-wavelength semiconductor laser device

Publications (1)

Publication Number Publication Date
JPH0590699A true JPH0590699A (en) 1993-04-09

Family

ID=17191706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24934991A Withdrawn JPH0590699A (en) 1991-09-27 1991-09-27 Manufacture of multiple-wavelength semiconductor laser device

Country Status (1)

Country Link
JP (1) JPH0590699A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5982799A (en) * 1994-09-14 1999-11-09 Xerox Corporation Multiple-wavelength laser diode array using quantum well band filling
WO2007046317A1 (en) * 2005-10-21 2007-04-26 Rohm Co., Ltd. Semiconductor laser light emitting device and method for manufacturing same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5982799A (en) * 1994-09-14 1999-11-09 Xerox Corporation Multiple-wavelength laser diode array using quantum well band filling
WO2007046317A1 (en) * 2005-10-21 2007-04-26 Rohm Co., Ltd. Semiconductor laser light emitting device and method for manufacturing same
JP2007115974A (en) * 2005-10-21 2007-05-10 Rohm Co Ltd Two-wavelength semiconductor laser light emitting device and its manufacturing method
US7860138B2 (en) 2005-10-21 2010-12-28 Rohm Co., Ltd. Semiconductor laser light emitting device and method for manufacturing same
KR101006267B1 (en) * 2005-10-21 2011-01-06 로무 가부시키가이샤 Semiconductor laser light emitting device and method for manufacturing same
US8102892B2 (en) 2005-10-21 2012-01-24 Rohm Co., Ltd. Semiconductor laser light emitting device and method for manufacturing same

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