JPH0590566A - Schottky barrier diode - Google Patents

Schottky barrier diode

Info

Publication number
JPH0590566A
JPH0590566A JP24808591A JP24808591A JPH0590566A JP H0590566 A JPH0590566 A JP H0590566A JP 24808591 A JP24808591 A JP 24808591A JP 24808591 A JP24808591 A JP 24808591A JP H0590566 A JPH0590566 A JP H0590566A
Authority
JP
Japan
Prior art keywords
layer
ring
guard ring
conductivity type
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24808591A
Other languages
Japanese (ja)
Inventor
Atsuhiko Kanbara
敦彦 蒲原
Hideaki Yamagishi
秀章 山岸
Junichi Suzuki
順一 鈴木
Hisako Suga
久子 菅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP24808591A priority Critical patent/JPH0590566A/en
Publication of JPH0590566A publication Critical patent/JPH0590566A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the breakdown strength of a breakdown voltage or the amount of a current by a method wherein a single crystal layer of the same conductivity type as that of a semiconductor substrate is formed on the one conductivity type semiconductor substrate containing a high-concentration impurity and a Schottky electrode of the same depth as that of a guard ring is formed in the guard ring formed in such a way as to encircle a prescribed region shallower than the thickness of the single crystal layer with a layer of a conductivity type inverse to that of the single crystal layer. CONSTITUTION:An epitaxial layer 2 is formed on a substrate 1 and thereafter, a P<+> layer is formed at a part including a region to be formed with a guard ring 3 and a Schottky electrode 5 in a depth shallower than the thickness of the layer 2. Then, the P<+> layer located at the center part of the P layer is etched leaving the outer periphery only, which is used as the ring 3, of the P<+> layer to make the n-type layer expose and the electrode 5 is formed in an etching pit including the upper part of the ring 3 in the same depth as that of the ring 3. Accordingly, the breakdown strength of a breakdown voltage can be improved without reducing the amount of current or the amount of the current can be improved keeping the breakdown voltage intact.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,高耐圧化をはかったシ
ョットキ―バリアダイオ―ドに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky barrier diode having a high breakdown voltage.

【0002】[0002]

【従来の技術】図2はショットキ―バリアダイオ―ドの
従来例を示す構成図である。図において1は高濃度の不
純物を含む一導電形(ここではn+ )基板,2は基板1
の表面にエビタキシャル成長により形成された基板と同
じ導電形からなる単結晶(n)層である。3は単結晶層
2の厚さよりも浅い深さで所定の領域をリング状に囲っ
て形成されたp+ 層からなるガ―ドリングであり,この
ガ−ドリングは耐圧向上に寄与するものである。4はS
iO2 やSi3 4 等からなる絶縁膜,5はガ―ドリン
グ内のエピタキシャル層(n)上に形成された金属材料
(Al,Pt,W,Au等)からなるショットキ―電
極,6は基板1の裏面に形成されたオ―ミック電極であ
る。
2. Description of the Related Art FIG. 2 is a block diagram showing a conventional example of a Schottky barrier diode. In the figure, 1 is a substrate of one conductivity type (here, n + ) containing a high concentration of impurities, 2 is a substrate 1
Is a single crystal (n) layer having the same conductivity type as the substrate formed on the surface of the substrate by the epitaxial growth. Reference numeral 3 is a guard ring composed of a p + layer formed so as to surround a predetermined region in a ring shape with a depth shallower than the thickness of the single crystal layer 2, and this guard ring contributes to the improvement of breakdown voltage. .. 4 is S
An insulating film made of iO 2 , Si 3 N 4, etc., 5 is a Schottky electrode made of a metal material (Al, Pt, W, Au, etc.) formed on the epitaxial layer (n) in the guard ring, 6 is It is an ohmic electrode formed on the back surface of the substrate 1.

【0003】上記構成のショットキ―バリアダイオ―ド
は導電成分が多数キャリアであり,小数キャリアの注入
がほとんどないので,小数キャリアの蓄積がない。従っ
てスイッチング時間が短く,高速動作に適している。ま
た,pn接合のダイオ―ドと異なり,片側が金属である
ため,同一半導体基板濃度に対して立上がり電圧が低く
直列抵抗も低いという特徴がある。
In the Schottky barrier diode having the above structure, the conductive component is the majority carrier, and since the minority carrier is hardly injected, the minority carrier is not accumulated. Therefore, the switching time is short and it is suitable for high-speed operation. Further, unlike the diode of the pn junction, since one side is made of metal, the rising voltage is low and the series resistance is low for the same semiconductor substrate concentration.

【0004】[0004]

【発明が解決しようとする課題】しかしながら,上記従
来のショットキ―バリアダイオ―ドにおいては,ガ―ド
リング(p+ 層)3の下方が基板(n+ 層)1側にショ
ットキ―電極よりも深い位置に突出している為,逆電圧
を印加するとガ―ドリングの先端に電界が集中し,その
電界による空乏層がn+ 層に達してブレ―クダウンが起
きやすいという問題があった。なお,ブレ―クダウンを
防止する為にはn層2を厚くしてガ―ドリングの底部と
基板(n+ )1の距離を長くすれば良いが,その場合は
順方向電流の流れが悪くなり,結果として損失の増加を
招くことになる。
However, in the above conventional Schottky barrier diode, the position below the guard ring (p + layer) 3 is deeper than the Schottky electrode on the substrate (n + layer) 1 side. Since the electric field is concentrated at the tip of the guard ring when a reverse voltage is applied, there is a problem that the depletion layer reaches the n + layer due to the electric field and breakdown easily occurs. In order to prevent the breakdown, the n layer 2 should be thickened and the distance between the bottom of the guard ring and the substrate (n +) 1 should be lengthened, but in that case the forward current flow becomes worse. , As a result, the loss will increase.

【0005】図3はショットキ―バリアダイオ―ドに逆
電圧を印加した場合の空乏層8の拡がり具合を示すもの
で,例えばn層2から基板1(n+ )までの深さds を
4μm,p+ 層の深さを2.2μmとした場合,n層の
厚さdg は1.8μmとなる。そのためショットキ―電
極5側の空乏層よりガ―ドリング(p+ 層)側の空乏層
が深くなって電界強度が更に増大しブレ―クダウンとな
る。
FIG. 3 shows how the depletion layer 8 spreads when a reverse voltage is applied to the Schottky barrier diode. For example, the depth ds from the n layer 2 to the substrate 1 (n + ) is 4 μm, p When the depth of the + layer is 2.2 μm, the thickness dg of the n layer is 1.8 μm. Therefore, the depletion layer on the guard ring (p + layer) side becomes deeper than the depletion layer on the Schottky electrode 5 side, and the electric field strength further increases, resulting in breakdown.

【0006】即ち,各層の厚さを上記の通りとし,n層
の不純物濃度を2×1015,p+ 層の不純物濃度を10
19として公知の簡略式を用いて計算した結果ではおよそ
67Vでブレ―クダウンを起こす。このブレ―クダウン
電圧と順方向抵抗は,一方を良くすれば他方が悪くなる
という相補的な関係となる。本発明は流れる電流量を低
下させることなくブレ―クダウン電圧の耐圧の向上をは
かるか,または,ブレ―クダウン電圧はそのままにして
電流量を向上させたショットキ―バリアダイオ―ドを提
供することを目的とする。
That is, the thickness of each layer is as described above, the impurity concentration of the n layer is 2 × 10 15 , and the impurity concentration of the p + layer is 10 ×.
The result calculated by using a simplified formula known as 19 causes a breakdown at about 67V. The breakdown voltage and the forward resistance have a complementary relationship that if one is improved, the other is deteriorated. It is an object of the present invention to improve the breakdown voltage of a breakdown voltage without reducing the amount of current flowing, or to provide a shot key barrier diode in which the amount of current is increased while keeping the breakdown voltage unchanged. And

【0007】[0007]

【課題を解決するための手段】上記課題を解決する為に
本発明は,高濃度の不純物を含む一導電形の半導体基板
上に同導電型の単結晶層が形成され,その単結晶層の厚
さよりも浅い深さの所定領域を逆導電形の層で囲ってカ
―ドリングが形成され,前記カ―ドリング内にショット
キ―電極を形成してなるショットキ―バリアダイオ―ド
において,前記ガ―ドリングおよびショットキ―電極の
深さを同一に形成したことを特徴とするものである。
In order to solve the above-mentioned problems, the present invention is to form a single crystal layer of the same conductivity type on a semiconductor substrate of one conductivity type containing a high concentration of impurities. In a Schottky barrier diode, a card ring is formed by surrounding a predetermined region having a depth shallower than a thickness with a layer of an opposite conductivity type, and a Schottky barrier diode is formed in the card ring. And the Schottky electrodes are formed to have the same depth.

【0008】[0008]

【作用】ガ―ドリングの深さがショットキ―電極の深さ
と同一に形成されているので,ガ―ドリングとショット
キ―電極下の空乏層が平均化され突出部がなくなる。
Since the depth of the guard ring is formed to be the same as the depth of the Schottky electrode, the guard ring and the depletion layer under the Schottky electrode are averaged and the protrusion is eliminated.

【0009】[0009]

【実施例】図1は本発明の一実施例を示す断面図(ただ
し向かって右側の半分は中心線を境に省略している)で
ある。なお,従来例と同一要素には同一符号を付してい
る。 即ち,本発明では基板1にエピタキシャル層2を
形成した後,ガ―ドリング3及びショットキ―電極5を
形成すべき領域を含む部分にp+ 層をイオン注入や拡散
等により形成する(このp+ 層の深さは例えばエピタキ
シャル層2の厚さを4μmとすれば2.2μm程度の厚
さとする)。
FIG. 1 is a sectional view showing an embodiment of the present invention (however, the right half of the drawing is omitted with the center line as a boundary). The same elements as those in the conventional example are designated by the same reference numerals. That is, in the present invention, after the epitaxial layer 2 is formed on the substrate 1, a p + layer is formed by ion implantation or diffusion in the portion including the region where the guard ring 3 and the Schottky electrode 5 are to be formed (this p + The layer depth is, for example, about 2.2 μm if the thickness of the epitaxial layer 2 is 4 μm).

【0010】次に,ガ―ドリング3とすべき外周のみを
残して中央部のp+ 層をエッチングしてn層を露出させ
る(この状態ではエッチング穴の底部がn層で周囲の壁
がp + となっている)。次に,ガ―ドリング3上を含む
前記エッチング穴にショットキ―電極5を形成する。上
記の構成において,従来例で示したものと同様の条件,
即ち,n層の不純物濃度を2×1015,p+ 層の不純物
濃度を1019とし,n層2から基板1(n+ )までの深
さds を4μm,p+ 層の深さを2.2μmとする。そ
の場合p+ 層の深さは従来と同様なのでブレ―クダウン
電圧は従来と同様約67Vであるが,ショットキ―電極
と基板1との距離がdg が4μmから1.8μmに縮ま
るので,その分抵抗が少なくなり電流量が多くなる。
Next, only the outer periphery to be the guard ring 3 is
The central p + layer is etched leaving the n layer exposed.
(In this state, the bottom of the etching hole is the n layer and the surrounding wall
Is p +Has become). Next, including on the guard ring 3
A Schottky electrode 5 is formed in the etching hole. Up
In the above configuration, the same conditions as those shown in the conventional example,
That is, the impurity concentration of the n layer is 2 × 1015, P + layer impurities
Concentration 1019From the n layer 2 to the substrate 1 (n+) Up to
The depth ds is 4 μm, and the depth of the p + layer is 2.2 μm. So
In the case of, the depth of the p + layer is the same as before, so it is broken down.
The voltage is about 67V as before, but the Schottky electrode
And the distance between the substrate 1 and dg is reduced from 4 μm to 1.8 μm.
Therefore, the resistance decreases and the amount of current increases.

【0011】また,エピタキシャル層2の厚さを6μm
程度に形成し,ガ―ドリング3となるp+ 層を表面から
2μmの深さに形成すればショットキ―電極5から基板
1(n+ )までの距離は従来と同様4μmとなる。従っ
て電流量はそのままにしてブレ―クダウン電圧を約97
Vに向上させることができる。なお,上記各工程におい
てはマスクとしての絶縁膜を形成したりパタ―ニングを
行う工程を要するがこれらについては公知の半導体技術
を用いて製作する。また,本実施例においてはガ―ドリ
ングとショットキ―電極を形成するに際し,p+ 層を所
定の領域全面に形成した後,ガ―ドリングとすべき外周
部分を残して中心部をエッチングし,そのエッチングし
た部分にショットキ―電極を形成したが,この方法に限
定するものではない。例えばp+ 層をリング状に形成し
た後リング内のエピタキシャル層を気相HClによりエ
ッチングしてもよい。その場合エッチングの深さをp+
層の深さに合せる必要があるがエッチングの深さは時間
により正確に制御することが可能である。
Further, the thickness of the epitaxial layer 2 is 6 μm.
If the p + layer to be the guard ring 3 is formed to a depth of 2 μm from the surface, the distance from the Schottky electrode 5 to the substrate 1 (n + ) is 4 μm as in the conventional case. Therefore, leave the current amount unchanged and set the breakdown voltage to about 97.
It can be improved to V. In addition, in each of the above steps, a step of forming an insulating film as a mask and patterning are required, but these are manufactured by using a known semiconductor technique. Further, in this embodiment, when forming the guard ring and the Schottky electrode, the p + layer is formed on the entire surface of a predetermined region, and then the central portion is etched except for the outer peripheral portion to be the guard ring. A Schottky electrode is formed on the etched portion, but the method is not limited to this. For example, after forming the p + layer in a ring shape, the epitaxial layer in the ring may be etched by vapor phase HCl. In that case, the etching depth should be p +
It is necessary to match the depth of the layer, but the etching depth can be accurately controlled with time.

【0012】[0012]

【発明の効果】以上実施例とともに具体的に説明した様
に,本発明のショットキ−バリアダイオ―ドによればガ
―ドリングおよびショットキ―電極の深さを同一に形成
しているので,流れる電流量を低下させることなくブレ
―クダウン電圧の耐圧の向上をはかるか,または,ブレ
―クダウン電圧はそのままにして電流量を向上をはかっ
たショットキ−バリアダイオ―ドを実現することができ
る。
As described above in detail with reference to the embodiments, according to the Schottky barrier diode of the present invention, the guard ring and the Schottky electrode are formed to have the same depth. The breakdown voltage of the breakdown voltage can be improved without lowering the breakdown voltage, or the Schottky barrier diode in which the amount of current is improved can be realized while keeping the breakdown voltage unchanged.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のショットキ―バリアダイオ―ドの一実
施例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a Schottky barrier diode of the present invention.

【図2】従来のショットキ―バリアダイオ―ドの一実施
例を示す断面図である。
FIG. 2 is a sectional view showing an embodiment of a conventional Schottky barrier diode.

【図3】従来例における空乏層の状態を示す図である。FIG. 3 is a diagram showing a state of a depletion layer in a conventional example.

【符号の説明】[Explanation of symbols]

1 基板 2 エピタキシャル層 3 ガ―ドリング 4 絶縁膜 5 ショットキ―電極 6 オ―ミック電極 1 substrate 2 epitaxial layer 3 guard ring 4 insulating film 5 Schottky electrode 6 ohmic electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 菅 久子 東京都武蔵野市中町2丁目9番32号 横河 電機株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hisako Suga Inventor Yokogawa Denki Co., Ltd. 2-932 Nakamachi 2-chome, Musashino-shi, Tokyo

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 高濃度の不純物を含む一導電形の半導体
基板上に同導電型の単結晶層が形成され,その単結晶層
の厚さよりも浅い深さの所定領域を逆導電形の層で囲っ
てカ―ドリングが形成され,前記カ―ドリング内にショ
ットキ―電極を形成してなるショットキ―バリアダイオ
―ドにおいて,前記ガ―ドリングおよびショットキ―電
極の深さを同一に形成したことを特徴とするショットキ
―バリアダイオ―ド。
1. A single crystal layer of the same conductivity type is formed on a semiconductor substrate of one conductivity type containing a high concentration of impurities, and a predetermined region having a depth shallower than the thickness of the single crystal layer is formed as a layer of the opposite conductivity type. In a Schottky barrier diode in which a card ring is formed surrounded by and a Schottky electrode is formed in the card ring, the guard ring and the Schottky electrode are formed to have the same depth. Shot key barrier diode.
JP24808591A 1991-09-26 1991-09-26 Schottky barrier diode Pending JPH0590566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24808591A JPH0590566A (en) 1991-09-26 1991-09-26 Schottky barrier diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24808591A JPH0590566A (en) 1991-09-26 1991-09-26 Schottky barrier diode

Publications (1)

Publication Number Publication Date
JPH0590566A true JPH0590566A (en) 1993-04-09

Family

ID=17172989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24808591A Pending JPH0590566A (en) 1991-09-26 1991-09-26 Schottky barrier diode

Country Status (1)

Country Link
JP (1) JPH0590566A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002334998A (en) * 2001-05-08 2002-11-22 Mitsubishi Electric Corp Silicon carbide semiconductor device and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002334998A (en) * 2001-05-08 2002-11-22 Mitsubishi Electric Corp Silicon carbide semiconductor device and manufacturing method therefor

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