JPH0590372A - Method and apparatus for detecting defect of semiconductor integrated circuit - Google Patents

Method and apparatus for detecting defect of semiconductor integrated circuit

Info

Publication number
JPH0590372A
JPH0590372A JP3246179A JP24617991A JPH0590372A JP H0590372 A JPH0590372 A JP H0590372A JP 3246179 A JP3246179 A JP 3246179A JP 24617991 A JP24617991 A JP 24617991A JP H0590372 A JPH0590372 A JP H0590372A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
signal
semiconductor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3246179A
Other languages
Japanese (ja)
Inventor
Yukiharu Uraoka
行治 浦岡
Noriko Tsutsu
野里子 筒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3246179A priority Critical patent/JPH0590372A/en
Publication of JPH0590372A publication Critical patent/JPH0590372A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To drive some of or all of transistors on a semiconductor highly integrated circuit freely to detect defects on the circuit by photoluminescence. CONSTITUTION:A performance test signal pattern for driving a semiconductor highly integrated circuit 300 is generated by a circuit tester 100. The performance test signal pattern is transmitted to a pattern generator 200 through an Ethernet or a GPIB cable and the semiconductor highly integrated circuit 300 is driven by the pattern generator 200. Photoluminescence from defects is amplified by a photoluminescence amplifier 400 to detect the detects on the semiconductor highly integrated circuit 300.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、集積度の高い半導体
集積回路における不良箇所を、半導体集積回路の表面か
らの微弱な発光により検出する半導体集積回路の不良検
出方法および不良検出装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit defect detecting method and a semiconductor integrated circuit defect detecting device for detecting a defective portion in a highly integrated semiconductor integrated circuit by weak light emission from the surface of the semiconductor integrated circuit. is there.

【0002】[0002]

【従来の技術】従来、この種の半導体集積回路中の不良
箇所からの微弱な発光を増幅して、不良箇所の検出を行
う不良検出方法が広く採用されている。この不良検出方
法は、半導体集積回路に直流電圧を印加して、この直流
電圧印加により酸化膜の絶縁破壊箇所や、高電界が印加
されているトランジスタを微弱な発光の有無およびその
位置で検出する方法であった。
2. Description of the Related Art Heretofore, a defect detection method has been widely used in which a weak light emission from a defective portion in a semiconductor integrated circuit of this type is amplified to detect the defective portion. In this defect detection method, a DC voltage is applied to a semiconductor integrated circuit, and by this DC voltage application, a dielectric breakdown point of an oxide film or a transistor to which a high electric field is applied is detected at the presence or absence of weak light emission and its position. Was the way.

【0003】[0003]

【発明が解決しようとする課題】ところが、従来の半導
体集積回路の不良検出方法は、直流電圧を半導体集積回
路に印加して行う方法であるため、半導体集積回路上の
デバイスのごく一部しか駆動されない。したがって、半
導体集積回路上のすべてのデバイスの不良を検出するこ
とができなかった。また、半導体集積回路上の駆動した
い部分を選択することができず、不良を検出した部分を
選択することもできなかった。
However, since the conventional method of detecting a defect in a semiconductor integrated circuit is a method of applying a DC voltage to the semiconductor integrated circuit, only a small part of the devices on the semiconductor integrated circuit are driven. Not done. Therefore, it is not possible to detect defects in all devices on the semiconductor integrated circuit. Further, it has been impossible to select a portion on the semiconductor integrated circuit to be driven, and it has not been possible to select a portion in which a defect is detected.

【0004】したがって、この発明の目的は、半導体集
積回路上のすべてのデバイスの不良を検出することがで
きるとともに、半導体集積回路上の不良を検出したい部
分を任意に選択することができる半導体集積回路の不良
検出方法および不良検出装置を提供することである。
Therefore, an object of the present invention is to detect a defect in all devices on a semiconductor integrated circuit and to arbitrarily select a portion on the semiconductor integrated circuit where a defect is to be detected. To provide a defect detection method and a defect detection device.

【0005】[0005]

【課題を解決するための手段】請求項1記載の半導体集
積回路の不良検出方法は、回路テスターから所定の動作
テスト用信号パターンの交流信号を作成し、この交流信
号の半導体集積回路への印加に伴って半導体集積回路の
表面から発生する微弱な発光を検出することにより、半
導体集積回路の不良箇所を検出することを特徴とする。
According to another aspect of the present invention, there is provided a method of detecting a defect in a semiconductor integrated circuit, wherein an alternating current signal of a predetermined operation test signal pattern is created from a circuit tester and the alternating current signal is applied to the semiconductor integrated circuit. It is characterized in that the defective portion of the semiconductor integrated circuit is detected by detecting the weak light emission generated from the surface of the semiconductor integrated circuit.

【0006】請求項2記載の半導体集積回路の不良検出
方法は、請求項1記載の構成において、交流信号をパタ
ーン発生器に送り、このパターン発生器により半導体集
積回路を駆動する。請求項3記載の半導体集積回路の不
良検出装置は、半導体集積回路に対する所定のテスト用
信号パターンの交流信号を作成する回路テスターを設
け、交流信号の半導体集積回路への印加に伴って半導体
集積回路の表面から発生する微弱な発光を増幅すること
により半導体集積回路の不良箇所を検出する発光増幅器
を設けたことを特徴とする。
According to a second aspect of the present invention, there is provided a method of detecting a defect in a semiconductor integrated circuit, wherein in the configuration of the first aspect, an AC signal is sent to a pattern generator and the pattern generator drives the semiconductor integrated circuit. The defect detecting apparatus for a semiconductor integrated circuit according to claim 3, further comprising a circuit tester for creating an AC signal of a predetermined test signal pattern for the semiconductor integrated circuit, and the semiconductor integrated circuit being applied with the application of the AC signal to the semiconductor integrated circuit. A light emitting amplifier is provided for detecting a defective portion of the semiconductor integrated circuit by amplifying the weak light emission generated from the surface of the semiconductor integrated circuit.

【0007】請求項4記載の半導体集積回路の不良検出
装置は、請求項3記載の構成において、交流信号を入力
し、この交流信号に基づいて半導体集積回路を駆動する
パターン発生器を設けている。
According to a fourth aspect of the present invention, there is provided a defect detecting device for a semiconductor integrated circuit according to the third aspect, further comprising a pattern generator for inputting an AC signal and driving the semiconductor integrated circuit based on the AC signal. ..

【0008】[0008]

【作用】この発明の構成によれば、半導体集積回路に対
する所定のテスト用信号パターンの交流信号が回路テス
ターで作成され、この交流信号が不良箇所を調べるべき
半導体集積回路に印加され、その半導体集積回路が駆動
される。上記交流信号は、不良箇所が存在すると予想さ
れる回路の一部または回路の全部を駆動するものであ
る。
According to the structure of the present invention, an AC signal having a predetermined test signal pattern for a semiconductor integrated circuit is created by a circuit tester, and this AC signal is applied to a semiconductor integrated circuit to be examined for a defective portion. The circuit is driven. The AC signal drives part of the circuit or all of the circuit expected to have a defective portion.

【0009】上記交流信号によって、不良箇所を含むデ
バイスに信号が印加されると、半導体集積回路が不良箇
所を含むデバイスの部分で発光し、その光が表面から外
部へ放射される。発光増幅器は、半導体集積回路の表面
からの微弱な発光を増幅することで、半導体集積回路の
不良箇所を検出する。
When a signal is applied to the device including the defective portion by the AC signal, the semiconductor integrated circuit emits light in the portion of the device including the defective portion, and the light is emitted from the surface to the outside. The light emission amplifier detects a defective portion of the semiconductor integrated circuit by amplifying weak light emission from the surface of the semiconductor integrated circuit.

【0010】[0010]

【実施例】この発明の第1の実施例を図1および図2に
基づいて説明する。はじめに、この発明の基本原理であ
る発光解析方法について図2を用いて説明する。図2
(a)〜(c)はいずれも半導体高集積回路における一
つのMOS型トランジスタの断面図を示し、10はゲー
ト、20はゲート酸化膜、30はソース、40はドレイ
ン、50は基板である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. First, the emission analysis method, which is the basic principle of the present invention, will be described with reference to FIG. Figure 2
Each of (a) to (c) is a cross-sectional view of one MOS type transistor in a semiconductor highly integrated circuit, where 10 is a gate, 20 is a gate oxide film, 30 is a source, 40 is a drain, and 50 is a substrate.

【0011】まず、図2(a)に示すように、トランジ
スタの内部を走るキャリア1が電界からエネルギーを得
ると、ドレイン近傍でホットキャリア2となる。このホ
ットキャリア2がエネルギーを放出する際、発光する
(矢印A)。つまり、設計不良などによって、ホットキ
ャリア2が電界から非常に高いエネルギーを得ると非常
に強い発光が観測される。従って、設計不良のトランジ
スタをこの発光から、LSI上で検出できる。
First, as shown in FIG. 2A, when carriers 1 running inside the transistor obtain energy from the electric field, they become hot carriers 2 near the drain. When this hot carrier 2 releases energy, it emits light (arrow A). That is, when the hot carrier 2 obtains very high energy from the electric field due to a defective design, very strong light emission is observed. Therefore, a poorly designed transistor can be detected on the LSI from this light emission.

【0012】また、図2(b)に示すように、ゲート酸
化膜20が部分3で絶縁破壊している場合においても、
発光が見られる(矢印B)。絶縁破壊を起こしている
際、電流は破壊場所に集中して流れるため、エネルギー
の高い電子がエネルギーを放出する際、発光が観測でき
るのである。さらに、図2(c)に示すように、拡散層
である例えばドレイン40が部分4で破壊している場合
にも、発光が見られる(矢印B)。
Further, as shown in FIG. 2B, even when the gate oxide film 20 has a dielectric breakdown in the portion 3,
Luminescence is seen (arrow B). When a dielectric breakdown occurs, the electric current concentrates on the breakdown site, so that light emission can be observed when high-energy electrons release energy. Further, as shown in FIG. 2C, light emission can be seen even when the diffusion layer, for example, the drain 40 is broken at the portion 4 (arrow B).

【0013】その他、ラッチアップが発生しているよう
な場合も発光がみられる。つぎに、この発明にかかる実
施例を図1を参照しながら説明する。この半導体集積回
路の不良検出装置は、回路テスター100によって、不
良の検出を行うべき半導体高集積回路300の一部もし
くは全部(不良箇所の存在すると予想される回路の一部
または回路の全部)を駆動するための信号群(以後、動
作テスト用信号パターンと称する)を作成し、インター
フェースバス(IEEE Std.488−1975規
格、通称GPIBケーブル、以後GPIBケーブルと称
する)、またはイーサネットによって、パターン発生器
200に転送する。この時、この動作テスト用信号パタ
ーンはパターン発生器200の形式に変換して送られ
る。
In addition, light emission is observed even when latch-up occurs. Next, an embodiment according to the present invention will be described with reference to FIG. In this semiconductor integrated circuit failure detection device, the circuit tester 100 detects a part or all of the semiconductor highly integrated circuit 300 for which a failure should be detected (a part of the circuit expected to have a failure part or the entire circuit). A signal group for driving (hereinafter, referred to as an operation test signal pattern) is created, and a pattern generator is provided by an interface bus (IEEE Std. 488-1975 standard, commonly known as GPIB cable, hereinafter referred to as GPIB cable), or Ethernet. Transfer to 200. At this time, the operation test signal pattern is converted into the format of the pattern generator 200 and sent.

【0014】回路テスター100は、半導体高集積回路
300を動作解析するための任意の動作テスト用信号パ
ターンを作成し、それをパターン発生器200の形式に
適合した形に変換してパターン発生器200に送るが、
半導体高集積回路300を直接駆動可能な形で動作テス
ト用信号パターンを出力することも可能である。パター
ン発生器200は、それ自体では動作テスト用信号パタ
ーンを作成できるものではなく、回路テスター100よ
り転送された動作テスト用信号パターンをメモリに記憶
するとともに、記憶した動作テスト用信号パターンを読
み出して半導体高集積回路300を駆動可能な信号形式
に変換した上で、半導体高集積回路300に供給するこ
とにより、半導体高集積回路300を駆動するものであ
る。図4はパターン発生器200より半導体高集積回路
300に加えられる動作テスト用信号パターンの波形の
一例を示すものであり、その波形は動作解析すべき半導
体高集積回路300の種類によって全く異なるものであ
るが、信号線の数例えばn個だけ並んでおり、各々ハイ
(例えば5V)とロー(例えば0V)の電圧の組み合わ
せとなり、全ての信号は同期している。
The circuit tester 100 creates an arbitrary operation test signal pattern for analyzing the operation of the semiconductor highly integrated circuit 300, converts it to a form suitable for the format of the pattern generator 200, and converts it. Sent to
It is also possible to output the operation test signal pattern in a form capable of directly driving the semiconductor highly integrated circuit 300. The pattern generator 200 cannot create an operation test signal pattern by itself, but stores the operation test signal pattern transferred from the circuit tester 100 in a memory and reads the stored operation test signal pattern. The semiconductor highly integrated circuit 300 is converted into a drivable signal format and then supplied to the semiconductor highly integrated circuit 300 to drive the semiconductor highly integrated circuit 300. FIG. 4 shows an example of the waveform of the operation test signal pattern applied to the semiconductor highly integrated circuit 300 from the pattern generator 200. The waveform is completely different depending on the type of the semiconductor highly integrated circuit 300 to be subjected to the operation analysis. However, the number of signal lines, for example, n, is lined up, each of which is a combination of high (for example, 5 V) and low (for example, 0 V) voltages, and all signals are synchronized.

【0015】半導体高集積回路300上で不良が存在す
れば、先に述べた原理によって、不良箇所において発光
が生じ、半導体高集積回路300の表面から外部へ放射
される。この発光を発光増幅器400によって増幅する
ことにより、半導体高集積回路300上のどの位置に不
良が発生しているのかがわかる。半導体高集積回路30
0を駆動するための動作テスト用信号パターンは、一度
パターン発生器200のメモリーに蓄積しておけば、回
路テスター100とは無関係にいつでも、メモリー上の
パターンを読み出して不良解析することが可能である。
If there is a defect on the semiconductor highly integrated circuit 300, light emission is generated at the defective portion according to the principle described above, and the light is emitted from the surface of the semiconductor highly integrated circuit 300 to the outside. By amplifying this light emission by the light emission amplifier 400, it is possible to know at which position on the semiconductor highly integrated circuit 300 the defect has occurred. Semiconductor highly integrated circuit 30
Once the operation test signal pattern for driving 0 is stored in the memory of the pattern generator 200, the pattern on the memory can be read out for failure analysis at any time regardless of the circuit tester 100. is there.

【0016】なお、500は電源である。この実施例に
よれば、半導体高集積回路300に回路テスター100
からパターン発生器200を介して所定の動作テスト用
信号パターンの交流信号を供給して不良の検出を行うの
で、半導体高集積回路300上のデバイスを自由に駆動
することができ、半導体高集積回路300上のすべての
デバイスの不良を簡便に検出することができ、しかも半
導体高集積回路300上の不良を検出したい部分を任意
に選択することができる。
Reference numeral 500 is a power source. According to this embodiment, the semiconductor highly integrated circuit 300 is used in the circuit tester 100.
Since the defective signal is detected by supplying an AC signal having a predetermined operation test signal pattern from the pattern generator 200, the device on the semiconductor highly integrated circuit 300 can be freely driven, and the semiconductor highly integrated circuit can be freely driven. It is possible to easily detect defects in all the devices on the semiconductor device 300, and it is possible to arbitrarily select a portion on the semiconductor highly integrated circuit 300 where a defect is to be detected.

【0017】また、パターン発生器200は、回路テス
ター100とは異なり、動作テスト用信号パターンを発
生する機能のみで動作テスト用信号パターンを作成する
機能はないが、回路テスター100に比べて大きさ,価
格は十分の一程度であり、発光増幅器400の近くに設
置する等持ち運びが容易で、回路テスター100が近く
になくても動作テストを行うことが可能で、さらに複数
台を準備して動作試験を能率的に行うことも可能であ
る。
Further, unlike the circuit tester 100, the pattern generator 200 has only a function of generating an operation test signal pattern and not a function of creating an operation test signal pattern, but is larger than the circuit tester 100. , The price is about one tenth, it is easy to carry such as installing it near the light emitting amplifier 400, and it is possible to perform the operation test even if the circuit tester 100 is not nearby. It is also possible to carry out the test efficiently.

【0018】この発明の第2の実施例を図3を参照しな
がら説明する。この実施例は、図3に示すように、回路
テスター100を直接、半導体高集積回路300に接続
したものである。この実施例では、回路テスター100
より半導体高集積回路300を駆動可能な動作テスト用
信号パターンを直接発生して、回路テスタ100により
半導体高集積回路300を直接駆動するので、パターン
を変換することがなく、容易に半導体高集積回路300
を駆動することができる。つまり、パターン発生器20
0を介在させることによる信号変換用ソフトウェアの作
成の手間を省くことができ、回路テスター100の近く
に半導体高集積回路300がある場合において、半導体
高集積回路300の動作試験が容易である。
A second embodiment of the present invention will be described with reference to FIG. In this embodiment, as shown in FIG. 3, the circuit tester 100 is directly connected to the semiconductor highly integrated circuit 300. In this embodiment, the circuit tester 100
Since the operation test signal pattern capable of driving the higher semiconductor integrated circuit 300 is directly generated and the higher semiconductor integrated circuit 300 is directly driven by the circuit tester 100, the semiconductor high integrated circuit can be easily converted without converting the pattern. 300
Can be driven. That is, the pattern generator 20
It is possible to save the trouble of creating the signal conversion software by interposing 0, and the operation test of the semiconductor highly integrated circuit 300 is easy when the semiconductor highly integrated circuit 300 is near the circuit tester 100.

【0019】[0019]

【発明の効果】この発明によれば、半導体集積回路に交
流信号を供給して不良の検出を行うので、半導体集積回
路上のデバイスを自由に駆動することができ、半導体集
積回路上のすべてのデバイスの不良を簡便に検出するこ
とができ、しかも半導体集積回路上の不良を検出したい
部分を任意に選択することができる。
According to the present invention, since an AC signal is supplied to a semiconductor integrated circuit to detect a defect, devices on the semiconductor integrated circuit can be freely driven and all the devices on the semiconductor integrated circuit can be driven. It is possible to easily detect a defect of the device, and it is possible to arbitrarily select a portion on the semiconductor integrated circuit where the defect is to be detected.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1の実施例を示すブロック図であ
る。
FIG. 1 is a block diagram showing a first embodiment of the present invention.

【図2】この発明における故障検出の原理を説明するた
めのMOS型トランジスタの断面図を示し、(a)はホ
ットキャリアによる発光の様子を示す断面図、(b)は
ゲート酸化膜の絶縁破壊の発光の様子を示す断面図、
(c)は拡散層の破壊による発光の様子を示す断面図で
ある。
2A and 2B are cross-sectional views of a MOS transistor for explaining the principle of failure detection in the present invention, FIG. 2A is a cross-sectional view showing a state of light emission by hot carriers, and FIG. 2B is a dielectric breakdown of a gate oxide film. Cross-sectional view showing the state of light emission of
(C) is a cross-sectional view showing a state of light emission due to destruction of the diffusion layer.

【図3】この発明の第2の実施例を示すブロック図であ
る。
FIG. 3 is a block diagram showing a second embodiment of the present invention.

【図4】動作テスト用信号パターンの一例を示す波形図
である。
FIG. 4 is a waveform diagram showing an example of an operation test signal pattern.

【符号の説明】[Explanation of symbols]

10 ゲート 20 ゲート酸化膜 30 ソース 40 ドレイン 50 基板 100 回路テスター 200 パターン発生器 300 半導体高集積回路 400 発光増幅器 500 電源 10 gate 20 gate oxide film 30 source 40 drain 50 substrate 100 circuit tester 200 pattern generator 300 semiconductor highly integrated circuit 400 light emission amplifier 500 power supply

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 回路テスターから所定の動作テスト用信
号パターンの交流信号を作成し、この交流信号の半導体
集積回路への印加に伴って前記半導体集積回路の表面か
ら発生する微弱な発光を検出することにより、前記半導
体集積回路の不良箇所を検出することを特徴とする半導
体集積回路の不良検出方法。
1. A circuit tester creates an AC signal of a predetermined operation test signal pattern, and detects weak light emission generated from the surface of the semiconductor integrated circuit when the AC signal is applied to the semiconductor integrated circuit. Accordingly, a defect detection method for a semiconductor integrated circuit, comprising detecting a defect location of the semiconductor integrated circuit.
【請求項2】 交流信号をパターン発生器に送り、この
パターン発生器により半導体集積回路を駆動する請求項
1記載の半導体集積回路の不良検出方法。
2. The defect detection method for a semiconductor integrated circuit according to claim 1, wherein an AC signal is sent to the pattern generator, and the semiconductor integrated circuit is driven by the pattern generator.
【請求項3】 半導体集積回路に対する所定のテスト用
信号パターンの交流信号を作成する回路テスターを設
け、前記交流信号の前記半導体集積回路への印加に伴っ
て前記半導体集積回路の表面から発生する微弱な発光を
増幅することにより前記半導体集積回路の不良箇所を検
出する発光増幅器を設けたことを特徴とする半導体集積
回路の不良検出装置。
3. A circuit tester for generating an alternating current signal of a predetermined test signal pattern for a semiconductor integrated circuit is provided, and a feeble generated from the surface of the semiconductor integrated circuit when the alternating current signal is applied to the semiconductor integrated circuit. A semiconductor integrated circuit defect detecting device, wherein a light emitting amplifier for detecting a defective portion of the semiconductor integrated circuit is provided by amplifying the emitted light.
【請求項4】 交流信号を入力し、この交流信号に基づ
いて半導体集積回路を駆動するパターン発生器を設けた
請求項3記載の半導体集積回路の不良検出装置。
4. The defect detecting device for a semiconductor integrated circuit according to claim 3, further comprising a pattern generator for inputting an AC signal and driving the semiconductor integrated circuit based on the AC signal.
JP3246179A 1991-09-25 1991-09-25 Method and apparatus for detecting defect of semiconductor integrated circuit Pending JPH0590372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3246179A JPH0590372A (en) 1991-09-25 1991-09-25 Method and apparatus for detecting defect of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3246179A JPH0590372A (en) 1991-09-25 1991-09-25 Method and apparatus for detecting defect of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0590372A true JPH0590372A (en) 1993-04-09

Family

ID=17144695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3246179A Pending JPH0590372A (en) 1991-09-25 1991-09-25 Method and apparatus for detecting defect of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0590372A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650768B1 (en) 1998-02-19 2003-11-18 International Business Machines Corporation Using time resolved light emission from VLSI circuit devices for navigation on complex systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650768B1 (en) 1998-02-19 2003-11-18 International Business Machines Corporation Using time resolved light emission from VLSI circuit devices for navigation on complex systems

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