JPH0590348A - Film carrier and semiconductor device using same - Google Patents

Film carrier and semiconductor device using same

Info

Publication number
JPH0590348A
JPH0590348A JP27671591A JP27671591A JPH0590348A JP H0590348 A JPH0590348 A JP H0590348A JP 27671591 A JP27671591 A JP 27671591A JP 27671591 A JP27671591 A JP 27671591A JP H0590348 A JPH0590348 A JP H0590348A
Authority
JP
Japan
Prior art keywords
film carrier
solder
metal
lead
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27671591A
Other languages
Japanese (ja)
Inventor
Masakazu Sugimoto
正和 杉本
Kazuo Ouchi
一男 大内
Ichiro Amino
一郎 網野
Atsushi Hino
敦司 日野
Mikio Aizawa
幹雄 相沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP27671591A priority Critical patent/JPH0590348A/en
Publication of JPH0590348A publication Critical patent/JPH0590348A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide a film carrier and a semiconductor device which can prevent solder used to connect the film carrier mounting a semiconductor chip to an external board from flowing into the joint of the semiconductor chip. CONSTITUTION:A lead 1 on a film carrier is spread one after the other with a metal lower layer 3 poor in wettability to solder 8 and a metal upper layer 4 rich in wettability to it; further, the metal upper layer 4 is partially removed to form a region A which prevents inflow of solder 8.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はフィルムキャリアおよび
これを用いた半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film carrier and a semiconductor device using the film carrier.

【0002】[0002]

【従来の技術】従来、半導体素子の実装する方法の一つ
としてフィルムキャリアを用いた方法が採用されてお
り、このフィルムキャリアを外部基板に接続する、所謂
アウターリードボンディングには、導電媒体金属として
半田が採用されている。一方、近年における電子機器の
薄型化や小型軽量化に伴い、半導体装置を多数個用いる
デバイスや機器は、半導体素子を一定面積の基板上に高
密度実装する必要があるために、インナーリードおよび
アウターリード共にリード間ピッチを狭くし、しかもイ
ンナーリードボンディング部とアウターリードボンディ
ング部との距離をできるだけ短くする傾向にある。
2. Description of the Related Art Conventionally, a method using a film carrier has been adopted as one of the methods for mounting a semiconductor element. In the so-called outer lead bonding for connecting this film carrier to an external substrate, a conductive medium metal is used. Solder is used. On the other hand, as electronic devices have become thinner and smaller and lighter in recent years, devices and equipment that use a large number of semiconductor devices require inner leads and outer layers to be mounted because the semiconductor elements must be mounted at high density on a substrate having a fixed area. For both leads, the pitch between leads tends to be narrowed, and the distance between the inner lead bonding portion and the outer lead bonding portion tends to be as short as possible.

【0003】しかしながら、ボンディング部間の距離を
短くすると、フィルムキャリアを外部基板に実装する際
に用いる半田が、その濡れ性からリードを伝わって半導
体素子の載置、接続部にまで流入して半導体素子間の短
絡を生じ、接続信頼性に悪影響を及ぼす恐れがある。ま
た、IC側に半田バンプを有する場合は他の部分への流
出によって、ICとリードとの接続部への必要量の半田
が不足して充分に接続できない場合がある。そこで、各
接続部への半田の流入を防止する目的で、絶縁性樹脂に
て半導体素子の接続部を被覆保護したり、リード表面に
半田に対して濡れ性の悪い金属層をメッキなどの手段で
選択的に形成したりする方法が提案されているが、上記
のようなインナーリードボンディング部とアウターリー
ドボンディング部とが近接するフィルムキャリアでは設
計および製造が困難になると共に、接続部での信頼性が
低下する恐れがある。
However, when the distance between the bonding portions is shortened, the solder used for mounting the film carrier on the external substrate flows from the wettability to the mounting and connection portions of the semiconductor element through the leads and the semiconductor. This may cause a short circuit between the elements and adversely affect the connection reliability. Further, when the IC has a solder bump, it may not be able to be sufficiently connected due to a shortage of the required amount of solder to the connecting portion between the IC and the lead due to the outflow to another portion. Therefore, in order to prevent the inflow of solder into each connection portion, a means such as covering and protecting the connection portion of the semiconductor element with an insulating resin or plating a metal layer having poor wettability with respect to the solder on the lead surface is used. However, it is difficult to design and manufacture a film carrier in which the inner lead bonding part and the outer lead bonding part are close to each other as described above, and the reliability of the connection part is improved. There is a risk of deterioration in sex.

【0004】[0004]

【発明が解決しようとする課題】本発明は上記従来の方
法における課題を解決すべくなされたものであって、半
導体素子載置部と外部基板接続部とが近接した場合で
も、外部基板接続時に用いる半田が半導体素子載置部へ
流入するのを確実に防止できる構造を有するフィルムキ
ャリアの提供、およびこのフィルムキャリアを用いて半
導体素子を実装、およびこれを外部基板上に実装した半
導体装置を提供することを目的とするものである。
SUMMARY OF THE INVENTION The present invention has been made to solve the problems in the above-mentioned conventional method, and when the semiconductor element mounting portion and the external substrate connecting portion are close to each other, the external substrate is connected at the time of connecting the external substrate. Provide a film carrier having a structure capable of surely preventing the used solder from flowing into a semiconductor element mounting portion, and mounting a semiconductor element using the film carrier, and a semiconductor device mounting the same on an external substrate The purpose is to do.

【0005】[0005]

【課題を解決するための手段】そこで、本発明者らは上
記目的を達成するために鋭意検討を重ねた結果、フィル
ムキャリアのリード表面に半田に対して濡れ性の悪い金
属層と濡れ性の良好な金属層を積層し、半田の流入を防
止するために部分的に濡れ性の悪い金属層を露出させる
ことにより、上記目的を達成できることを見い出し、本
発明を完成するに至った。
The inventors of the present invention have conducted extensive studies to achieve the above object, and as a result, have found that the lead surface of the film carrier has a metal layer having poor wettability with respect to solder and a wettability. It has been found that the above object can be achieved by laminating a good metal layer and partially exposing a metal layer having poor wettability in order to prevent the inflow of solder, and completed the present invention.

【0006】即ち、本発明は半導体素子載置用のリード
を絶縁体フィルムの片面に有するフィルムキャリアにお
いて、上記リードの表面には半田に対して濡れ性が悪い
金属下層と濡れ性が良好な金属上層が順次形成され、か
つ半導体素子載置部より外側領域のリード表面の金属上
層が一部除去されて、金属下層が露出していることを特
徴とするフィルムキャリア、およびこのフィルムキャリ
アに半導体素子を載置、接続してなる半導体装置、なら
びに上記フィルムキャリアに半導体素子を載置、接続
し、これを外部基板上の回路配線に接続してなる半導体
装置を提供するものである。
That is, according to the present invention, in a film carrier having a semiconductor element mounting lead on one surface of an insulating film, the surface of the lead is a metal lower wettability to solder and a metal good wettability to solder. A film carrier, in which an upper layer is sequentially formed, a metal upper layer on a lead surface in an area outside the semiconductor element mounting portion is partially removed, and a metal lower layer is exposed, and a semiconductor element on the film carrier. And a semiconductor device in which a semiconductor element is placed and connected to the film carrier and is connected to a circuit wiring on an external substrate.

【0007】[0007]

【実施例】以下に本発明の実施例を図面を用いて具体的
に説明する。
Embodiments of the present invention will be specifically described below with reference to the drawings.

【0008】図1は本発明のフィルムキャリアを用いて
半導体素子を載置、接続してなる状態を示す部分断面図
である。図1から明らかなように本発明のフィルムキャ
リアは絶縁性フィルム2の片面に半導体素子5を載置す
るためのリード1を有し、リード1の表面には半田に対
して濡れ性の悪い金属下層3と濡れ性が良好な金属上層
4とが形成されている。そして本発明のフィルムキャリ
アには外部基板上の回路配線に接続する際に用いる半田
の流入を防止する目的で、半導体素子5載置部よりも外
側のリード上の金属上層4が一部除去されて、金属下層
3を露出させた領域Aが設けられている。
FIG. 1 is a partial sectional view showing a state in which a semiconductor element is placed and connected using the film carrier of the present invention. As is clear from FIG. 1, the film carrier of the present invention has a lead 1 for mounting the semiconductor element 5 on one surface of the insulating film 2, and the surface of the lead 1 is made of a metal having poor wettability to solder. The lower layer 3 and the metal upper layer 4 having good wettability are formed. The metal upper layer 4 on the leads outside the semiconductor element 5 mounting portion is partially removed in order to prevent the solder used for connecting to the circuit wiring on the external substrate from flowing into the film carrier of the present invention. Thus, a region A exposing the metal lower layer 3 is provided.

【0009】図1において本発明のフィルムキャリアに
用いる絶縁性フィルム2は、電気絶縁特性を有するもの
であり、適度な可撓性があればその材質に制限はなく、
例えばポリエステル系樹脂、エポキシ系樹脂、ウレタン
系樹脂、ポリスチレン系樹脂、ポリエチレン系樹脂、ポ
リアミド系樹脂、ポリイミド系樹脂、ABS樹脂、ポリ
カーボネート樹脂、シリコーン系樹脂、フッ素樹脂など
熱硬化性樹脂や熱可塑性樹脂を問わず用いることができ
る。これらのうち耐熱性や機械的強度の点からはポリイ
ミド系樹脂からなるフィルムを用いることが好ましい。
絶縁性フィルム2の厚みは通常、5〜150μm程度の
ものを採用することが好ましい。
In FIG. 1, the insulating film 2 used in the film carrier of the present invention has electrical insulating properties, and its material is not limited as long as it has appropriate flexibility.
For example, polyester resin, epoxy resin, urethane resin, polystyrene resin, polyethylene resin, polyamide resin, polyimide resin, ABS resin, polycarbonate resin, silicone resin, fluororesin, etc. thermosetting resin or thermoplastic resin. It can be used regardless of. Of these, it is preferable to use a film made of a polyimide resin from the viewpoint of heat resistance and mechanical strength.
The thickness of the insulating film 2 is usually preferably about 5 to 150 μm.

【0010】また、上記絶縁性フィルム2の片面に形成
されるリード1は、例えば金、銀、ニッケル、コバルト
などの各種金属や、これらを主成分とする各種合金など
からなる導電性材料によって所望の線状パターンに形成
された配線回路からなるものであり、リード1上に半導
体素子1が載置、電気的接続される。
The lead 1 formed on one surface of the insulating film 2 is preferably made of a conductive material such as various metals such as gold, silver, nickel and cobalt, and various alloys containing these as main components. The semiconductor device 1 is placed on the leads 1 and electrically connected thereto.

【0011】リード1の表面にはまず、半田に対して濡
れ性が悪いニッケルやクロムなどからなる金属下層3が
メッキなどの方法によって形成される。次いで、その上
に半田に対して濡れ性が良い金、銀、スズ、鉛、半田な
どからなる金属上層4がメッキなどの方法によって形成
される。金属下層3および金属上層4の厚みは通常、1
〜50μmおよび0.1〜10μm程度とすることが、
後述する領域Aの形成し易さの点から好ましい。
First, a metal lower layer 3 made of nickel, chromium or the like having poor wettability with respect to solder is formed on the surface of the lead 1 by a method such as plating. Then, a metal upper layer 4 made of gold, silver, tin, lead, solder or the like having good wettability with respect to solder is formed thereon by a method such as plating. The thickness of the metal lower layer 3 and the metal upper layer 4 is usually 1
To about 50 μm and 0.1 to 10 μm,
It is preferable from the viewpoint of easy formation of the area A described later.

【0012】本発明においては半田の流入を防止するた
めに、上記半田に対する濡れ性の悪い金属および濡れ性
の良い金属を利用しているが、濡れ性の指標として各金
属の表面張力を用いることができる。つまり、金属下層
3の表面張力は金属上層4の表面張力よりも大きく、具
体的にはActa Met., 4,576(1956)や、Chem. Rev., 52,4
17(1953)、Z.anorg. und Allge. Chem., 276, 227(195
4) に記載の方法によって測定される表面張力(γS
が3000ダイン/センチメートル以上の金属を金属下
層3に用いることが好ましい。
In the present invention, in order to prevent the inflow of solder, a metal having poor wettability with respect to the solder and a metal having good wettability are used, but the surface tension of each metal is used as an index of wettability. You can That is, the surface tension of the lower metal layer 3 is larger than that of the upper metal layer 4, and specifically, Acta Met., 4 , 576 (1956) and Chem. Rev., 52 , 4
17 (1953), Z.anorg. Und Allge. Chem., 276 , 227 (195
Surface tension (γ S ) measured by the method described in 4)
Is preferably 3000 dynes / centimeter or more for the metal lower layer 3.

【0013】本発明においては、上記のようにして各金
属層を表面に積層したリード1に図1に示すように、半
田の流入を防止するために金属下層3を露出させた領域
Aを形成する。形成方法としては切削や研磨などの機械
的加工法や、金属上層を選択的に溶解させる化学エッチ
ング法、レーザー照射や光照射によるドライエッチング
法などが挙げられる。これらの方法のうち、インナーリ
ードボンディング部とアウターリードボンディング部と
を近接させて半導体素子を高密度実装し、しかも高精度
で領域Aを形成したフィルムキャリアを作製するには、
紫外光レーザーの照射によるドライエッチング法を採用
することが好ましい。紫外光レーザーを用いて領域Aを
形成する場合、例えば金属下層3にニッケルを、金属上
層4に金を形成して、紫外光レーザーの照射エネルギー
を金のみを選択的に除去できるエネルギー値に設定して
レーザー照射することによって、金属上層4のみを除去
し金属下層3が露出した領域Aが形成できる。
In the present invention, as shown in FIG. 1, the lead 1 having the metal layers laminated on the surface as described above is provided with an area A in which the metal lower layer 3 is exposed in order to prevent the inflow of solder. To do. Examples of the forming method include a mechanical processing method such as cutting and polishing, a chemical etching method for selectively dissolving an upper metal layer, and a dry etching method by laser irradiation or light irradiation. Among these methods, in order to fabricate a film carrier in which the inner lead bonding portion and the outer lead bonding portion are brought close to each other, the semiconductor elements are mounted at high density, and the region A is formed with high accuracy,
It is preferable to adopt a dry etching method by irradiation with an ultraviolet light laser. When the region A is formed by using an ultraviolet laser, for example, nickel is formed on the metal lower layer 3 and gold is formed on the metal upper layer 4, and the irradiation energy of the ultraviolet laser is set to an energy value capable of selectively removing only gold. Then, by irradiating the laser, only the upper metal layer 4 can be removed to form the region A where the lower metal layer 3 is exposed.

【0014】本発明のフィルムキャリアに形成される上
記領域Aの大きさは、外部基板との接続時に用いる半田
が流入しない程度であればよく、好ましくは10〜50
0μm程度の幅でリード1の表面に形成する。
The size of the area A formed on the film carrier of the present invention may be such that the solder used for connection with the external substrate does not flow in, and is preferably 10 to 50.
It is formed on the surface of the lead 1 with a width of about 0 μm.

【0015】図2は本発明のフィルムキャリアのリード
1部のみの拡大斜視図である。リード1には半田流入を
防止するために、一部分のリード周囲の金属上層4を選
択的に除去して金属下層3を露出させた領域Aが形成さ
れている。
FIG. 2 is an enlarged perspective view of only one lead of the film carrier of the present invention. In order to prevent the solder from flowing into the lead 1, a region A is formed in which the metal upper layer 4 around a part of the lead is selectively removed to expose the metal lower layer 3.

【0016】図3は本発明のフィルムキャリアに半導体
素子5を載置、接続し、これを外部基板6上の回路配線
7に半田8によって接続した本発明の半導体装置の部分
断面図である。上記本発明のフィルムキャリアを用いる
ことによって、外部基板6と接続する際に用いる半田8
の流入が、図示するように領域Aの形成によって阻止さ
れるのである。
FIG. 3 is a partial cross-sectional view of the semiconductor device of the present invention in which the semiconductor element 5 is placed and connected to the film carrier of the present invention and is connected to the circuit wiring 7 on the external substrate 6 by the solder 8. By using the film carrier of the present invention, the solder 8 used when connecting to the external substrate 6
Is blocked by the formation of region A as shown.

【0017】[0017]

【発明の効果】以上のように本発明のフィルムキャリア
を用いることによって、半導体素子を実装、および外部
基板上に接続して半導体装置をする場合、外部基板との
接続時に用いる半田が半導体素子接続部に流入すること
がなく、電気的接続信頼性が極めて向上するという効果
を発揮する。
As described above, by using the film carrier of the present invention, when a semiconductor element is mounted and connected to an external substrate to form a semiconductor device, the solder used when connecting to the external substrate is semiconductor element connection. The effect that the electric connection reliability is extremely improved without flowing into the part.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明のフィルムキャリアを用いて半導体素
子を載置、接続してなる状態を示す部分断面図である。
FIG. 1 is a partial cross-sectional view showing a state in which a semiconductor element is placed and connected using the film carrier of the present invention.

【図2】 本発明のフィルムキャリアのリード部のみの
拡大斜視図である。
FIG. 2 is an enlarged perspective view of only the lead portion of the film carrier of the present invention.

【図3】 本発明の半導体装置の部分断面図である。FIG. 3 is a partial cross-sectional view of a semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1 リード 2 絶縁性フィルム 3 金属下層 4 金属上層 5 半導体素子 6 外部基板 7 回路配線 8 半田 1 Lead 2 Insulating Film 3 Metal Lower Layer 4 Metal Upper Layer 5 Semiconductor Element 6 External Board 7 Circuit Wiring 8 Solder

───────────────────────────────────────────────────── フロントページの続き (72)発明者 日野 敦司 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 (72)発明者 相沢 幹雄 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Hino 1-2-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation (72) Inventor Mikio Aizawa 1-21-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子載置用のリードを絶縁体フィ
ルムの片面に有するフィルムキャリアにおいて、上記リ
ードの表面には半田に対して濡れ性が悪い金属下層と濡
れ性が良好な金属上層が順次形成され、かつ半導体素子
載置部より外側領域のリード表面の金属上層が一部除去
されて、金属下層が露出していることを特徴とするフィ
ルムキャリア。
1. A film carrier having a semiconductor element mounting lead on one surface of an insulating film, wherein a metal lower layer having poor wettability to solder and a metal upper layer having good wettability are successively formed on the surface of the lead. A film carrier, wherein a metal upper layer is formed and a metal upper layer on a lead surface in a region outside a semiconductor element mounting portion is partially removed to expose a metal lower layer.
【請求項2】 請求項1記載のフィルムキャリアに半導
体素子を載置、接続してなる半導体装置。
2. A semiconductor device in which a semiconductor element is placed on and connected to the film carrier according to claim 1.
【請求項3】 請求項1記載のフィルムキャリアに半導
体素子を載置、接続し、これを外部基板上の回路配線に
接続してなる半導体装置。
3. A semiconductor device in which a semiconductor element is placed and connected to the film carrier according to claim 1 and is connected to a circuit wiring on an external substrate.
JP27671591A 1991-09-26 1991-09-26 Film carrier and semiconductor device using same Pending JPH0590348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27671591A JPH0590348A (en) 1991-09-26 1991-09-26 Film carrier and semiconductor device using same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27671591A JPH0590348A (en) 1991-09-26 1991-09-26 Film carrier and semiconductor device using same

Publications (1)

Publication Number Publication Date
JPH0590348A true JPH0590348A (en) 1993-04-09

Family

ID=17573323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27671591A Pending JPH0590348A (en) 1991-09-26 1991-09-26 Film carrier and semiconductor device using same

Country Status (1)

Country Link
JP (1) JPH0590348A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158177A (en) * 2005-12-07 2007-06-21 Yamaha Corp Thermoelectric conversion module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158177A (en) * 2005-12-07 2007-06-21 Yamaha Corp Thermoelectric conversion module

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