JPH0590338A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve hermeticalness in a cavity and to prevent breaks of bump electrodes in a semiconductor device which seals a semiconductor pellet mounted face down on the mount face of a base board with a sealing cap. CONSTITUTION:The clearance t of a junction between a base board 5 and a sealing cap 6 is made as large as or smaller than the diameter of a crystal grain of a sealant 10, and a topmost layer wiring (electrode 13) 36 of the base board 5 is kept floated from the surface of an insulating film (etching stopper) 33 of the base board 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a semiconductor pellet is mounted on a mounting surface of a base substrate with a bump electrode interposed.

[0002]

2. Description of the Related Art A semiconductor device utilizing a face-down method is known as a semiconductor device capable of obtaining a high packaging density. In this type of semiconductor device, semiconductor pellets are mounted on a pellet mounting surface of a base substrate by a face-down method, and the semiconductor pellets are sealed with a sealing cap.
The semiconductor pellet is sealed in the cavity formed by the base substrate and the sealing cap. The face-down method is a method of electrically and mechanically connecting the external terminals (bonding pads) of the semiconductor pellet and the electrodes of the base substrate with bump electrodes (CCB electrodes, protruding electrodes) using solder. Since the face-down method can be mounted on the base substrate within the area occupied by the semiconductor pellet, the mounting area and the signal propagation path can be reduced as compared with the bonding wire method.

A plurality of semiconductor devices utilizing the face-down method, which the present inventor is developing, are mounted on a mounting surface of a mounting substrate such as a module substrate or a PCB substrate, and are incorporated in a cooling system forcibly cooled by a cooling device. Be done. The back surface of the semiconductor pellet of the semiconductor device is connected to a sealing cap through a heat-conducting filler, and heat generated by the operation of the circuit system mounted on the semiconductor pellet is conducted to the sealing cap. The heat conducted to the sealing cap is further conducted to the cooling device. As the heat conduction filler, solder having high heat conductivity is used. The base substrate and the sealing cap of the semiconductor device are bonded to each other in a region (bonding region) around the semiconductor pellet with a sealing material using solder.
The inside of the cavity formed by the base substrate and the sealing cap is filled with an immortalizing gas (for example, mainly nitrogen gas) for sealing the semiconductor pellet, and the airtightness to the outside of the cavity is maintained. Further, the base substrate of the semiconductor device is mounted on the mounting surface of the mounting substrate by a face-down method. That is, the base substrate of the semiconductor device is mounted on the mounting surface of the mounting substrate via the bump electrodes using solder.

The semiconductor device has bump electrodes for mounting the semiconductor pellets on a base substrate, a heat conductive filler for connecting the semiconductor pellets and the sealing cap, and sealing for joining the base substrate and the sealing cap. A total of 3 types of solder are used. Further, since the bump electrodes are used when the semiconductor device is mounted on the mounting substrate and incorporated in the cooling system, a total of four kinds of solder are used in the cooling system. These four types of solder are formed in the cooling system assembling process under the condition that the solder formed in the former step does not melt by the heat treatment in the latter step. That is, the above-mentioned four types of solder have a temperature hierarchy in which the melting temperature sequentially decreases in each forming order in the assembly process.

A semiconductor device using a general face-down method is disclosed in JP-A-62-2449429.
It is described in Japanese Patent Publication No.

[0006]

In the above semiconductor device, the bonding region of the sealing cap is bonded to the bonding region of the base substrate with the sealing material interposed. Since the melting temperature of the sealing material is regulated by the above-mentioned temperature hierarchy, a Pb-Sn alloy having a relatively high melting point (for example, Pb-10 of 90% by weight) is used.
[Wt%] Sn) solder is used. This Pb-Sn
Alloys have a non-eutectic composition, that is, a dendrite structure,
Shrinkage holes are easily generated between dendrite branches and at grain boundaries. Also,
Pb-Sn alloys have a S content in the heat treatment step during the assembly process and in the temperature cycle that is an environmental test after product completion
Segregation of n occurs, and a large number of minute contraction holes are connected to each other. Therefore, there is a problem that a leak path that connects the inside of the cavity to the outside of the cavity is generated at the joining portion (sealing portion) between the base substrate and the sealing cap, and the airtightness inside the cavity of the semiconductor device is deteriorated. It was This decrease in airtightness inside the cavity causes intrusion of contaminants and water through the leak path from the outside of the cavity to the inside of the cavity, which lowers the reliability of the semiconductor device.

Therefore, as a technique for solving the technical problem in such a semiconductor device, although it is not a publicly known technique, the Japanese Patent Application No. 2-77 previously filed by the applicant of the present application.
As described in No. 331, the present inventor has configured the distance between the bonding region of the base substrate and the bonding region of the sealing cap to be equal to or smaller than the crystal grain diameter of the sealing material. However, the present invention has been made to prevent the occurrence of a leak path that connects the inside of the cavity and the outside of the cavity.

However, the present inventor has found a new problem with the semiconductor device.

In the above semiconductor device, since the single crystal grain of the sealing material existing in the gap between the bonding region of the base substrate and the bonding region of the sealing cap exists in the gap direction, the heat treatment during the assembly process is performed. The joint cannot absorb the thermal stress generated in the temperature cycle which is an environmental test after the process or the product is completed. Therefore, due to the structure of the semiconductor device, stress concentrates on the bump electrode used for mounting the semiconductor pellet on the base substrate having the lowest mechanical strength, and the bump electrode is damaged.

An object of the present invention is to provide a technique capable of preventing damage to bump electrodes in a semiconductor device in which semiconductor pellets are mounted on a mounting surface of a base substrate by a face-down method.

Another object of the present invention is to improve the airtightness of the inside of a cavity in a semiconductor device in which a semiconductor cap mounted on a mounting surface of a base substrate in a face-down manner is sealed with a sealing cap, and a bump is formed. An object of the present invention is to provide a technique capable of preventing damage to electrodes.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) The second wiring arranged on the uppermost layer of the multilayer wiring layers of the semiconductor pellet with bump electrodes interposed on the first wiring arranged on the uppermost layer of the multilayer wiring layers of the base substrate.
In the semiconductor device to which the wiring is connected, a part of the region of the first wiring arranged on the uppermost layer of the base substrate or the second wiring arranged on the uppermost layer of the semiconductor pellet that is not connected to the bump electrode is more than the uppermost layer. A region of another portion connected to the lower layer wiring and connected to the bump electrode is drawn out from the joint portion to the periphery thereof, and the insulating film between the uppermost first wiring or second wiring and the lower layer wiring is formed. Composed of floating from the surface.

(2) The semiconductor pellet of the semiconductor device according to the above-mentioned means (1) is sealed in a cavity formed by a base substrate and a sealing cap joined to the base substrate with a solder sealing material interposed therebetween. While being stopped, a part of the semiconductor pellet is connected to the sealing cap with a heat conductive material interposed, and the gap between the joint portion between the base substrate and the sealing cap is the same as that of the solder-based sealing material. The size is the same as or smaller than the crystal grain size.

[0016]

According to the above-mentioned means (1), the thermal stress generated in the heat treatment step in the assembly process or the temperature cycle which is the environmental test after the product is completed is absorbed by the first wiring or the second wiring, and the mechanical strength is increased. Since the stress concentrated on the low bump electrode can be relieved, the bump electrode can be prevented from being damaged and the reliability of the semiconductor device can be improved.

According to the above-mentioned means (1) and (2), the crystal grains of the encapsulant are present singly in the gap direction of the joining portion between the base substrate and the encapsulation and are generated at the crystal grain boundaries. Since the contraction holes that connect to each other are not connected to each other, it is possible to prevent the generation of a leak path that connects the inside of the cavity and the outside of the cavity, improve the airtightness of the inside of the cavity, and prevent thermal stress that is not absorbed in the joint portion from the first wiring or Since the stress absorbed by the two wirings and concentrated on the bump electrode can be relieved, the damage of the bump electrode can be prevented. As a result, the reliability of the semiconductor device can be improved.

The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor device incorporated in a cooling system.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A schematic structure of a semiconductor device incorporated in a cooling system according to an embodiment of the present invention is shown in FIG. 1 (cross-sectional view), FIG. 2 (enlarged cross-sectional view of main part) and FIG. Show.

As shown in FIG. 1, in a semiconductor device incorporated in a cooling system, semiconductor pellets 1 are mounted on a pellet mounting surface of a base substrate 5, and the semiconductor pellets 1 are sealed with a sealing cap 6. To do.

The base substrate 5 is composed of a ceramic substrate 4 having a multi-layer wiring structure formed of, for example, mullite and a resin substrate 3 having a multi-layer wiring structure formed of, for example, a polyimide resin. The wiring of the multilayer wiring structure of the resin substrate 3 is electrically connected to the wiring of the multilayer wiring structure of the ceramic substrate 4. A plurality of electrodes 13 are arranged on the pellet tower mounting surface (the surface of the resin substrate 3) of the base substrate 5, and a plurality of electrodes 14 are arranged on the back surface facing the pellet tower mounting surface. Each of the electrodes 13 and 14 is electrically connected via the wiring of the ceramic substrate 4 and the wiring of the resin substrate 3.

The semiconductor pellet 1 is mainly composed of, for example, a single crystal silicon substrate, and its element forming surface (lower surface in FIG. 1).
A logic circuit system, a memory circuit system, or a mixed circuit system thereof is installed in the. A plurality of external terminals (bonding pads) 12 are arranged on the element forming surface side of the semiconductor pellet 1.

A bump electrode (CCB electrode or bump electrode) 2 is interposed between the electrode 13 of the base substrate 5 and the electrode 14 of the semiconductor pellet 1. That is, the base substrate 5 and the semiconductor pellet 1 are electrically and mechanically connected via the bump electrodes 2 and are connected in a face-down manner. The bump electrode 2 is formed of a solder material whose melting point is located at the highest temperature in the temperature hierarchy among the solder materials used in the cooling system. For example, the bump electrode 2 is made of Pb-Sn alloy (98.2 [wt%] Pb-
Formed by 1.8 [wt%] Sn), and 320 to 327
It has a melting point of [° C.].

The sealing cap 6 has a U-shaped cross section, and the semiconductor pellet 1 together with the base substrate 5 is formed.
A cavity for housing and hermetically sealing. The sealing cap 6 is formed of, for example, aluminum nitride having good thermal conductivity.

Pellet connecting surface of the sealing cap 6
(Inside the cavity) is connected to the back surface of the semiconductor pellet 1 facing the element formation surface with the heat conducting filler 7 interposed. The heat-conducting filler 7 substantially eliminates minute spaces generated by minute irregularities that exceed the processing accuracy of the pellet coupling surface of the sealing cap 6 and the back surface of the semiconductor pellet 1, respectively.
The two can be almost completely adhered. That is, the heat conduction filler 7 can transfer the heat generated by the operation of the circuit system mounted on the semiconductor pellet 1 to the sealing cap 6 with high efficiency. The heat conduction filler 7 is formed of a solder material having a lower melting point than that of the bump electrode 2. For example, the heat conduction filler 7 is a Pb-Sn alloy (90 [wt%] Pb-1.
0 [wt%] Sn) and 275-300 [° C]
Having a melting point of.

The sealing cap 6 is a base substrate 10
The bonding area facing the bonding area (the area around the semiconductor pellet) is bonded to the bonding area of the base substrate 5 by the sealing material 10. When the back surface of the semiconductor pellet 1 and the pellet connecting surface of the sealing cap 6 are connected by the heat conduction filling material 7, the sealing material 10 bonds a part of the heat conduction filling material 7 to the base substrate 5. It is formed of the heat-conducting filler 7 that is poured between the region and the joining region of the sealing cap 6. That is, the sealing material 10 is the same Pb-S as the heat conduction filler 7.
n-based alloy (90 [wt%] Pb-10 [wt%] Sn)
And has a melting point of 275 to 300 [° C.].

In the bonding region of the base substrate 5, a metallized layer 9 is formed by sequentially depositing, for example, a W film, a Ni film, and an Au film. That is, the metallized layer 9 is formed between the bonding region of the base substrate 5 and the sealing material 10. In the bonding region of the sealing cap 6, for example, a Ti film, N
A metallized layer 8 is formed by sequentially depositing the i film and the Au film. That is, the metallized layer 8 is formed between the bonding region of the sealing cap and the sealing material 10. Each of the metallized layer 8 and the metallized layer 9 ensures the wettability of the sealing material 10. The metallized layer 8 is also formed on the inner wall of the sealing cap 6 on the inner side of the cavity and the outer wall of the outer side of the cavity.

As shown in FIGS. 1 and 3, the gap t between the bonding region of the base substrate 5 and the bonding region of the sealing cap 6 is larger than the diameter of the crystal particles 10A of the sealing material 10. Composed of small dimensions. This gap t is not limited to this, but in the manufacturing process for sealing the sealing cap 6 of the semiconductor device, for example, when sealing is performed at a cooling rate of 30 ° C./min, the sealing material (Pb-Sn The diameter of the crystal particles 10A of the (type alloy) 10 is about 25 μm. Since the diameter of the crystal particles 10A of the encapsulating material 10 naturally varies depending on the speed of the cooling rate, for example, if the cooling rate is slowed down by one digit, the diameter of the crystal particles 10A doubles. When the sealing is performed under such conditions, the gap t can be expanded to a dimension of about 50 μm or less. By configuring the gap t between the bonding region of the base substrate 5 and the bonding region of the sealing cap 6 thus configured to be equal to or less than the diameter of the crystal particles 10A of the sealing material 10. , Gap t
Since the single crystal particle 10A of the sealing material 10 existing in 1) exists in the gap direction, and the contraction holes 10B generated in the crystal grain boundaries are not connected to each other, the generation of the leak path connecting the inside of the cavity and the outside of the cavity is prevented. This can be prevented and the airtightness inside the cavity of the semiconductor device can be improved. In addition, the sealing material 1
Since the crystal particles 10A of 0 grow three-dimensionally, the length L of the bonding region of the sealing cap 6 (the length from the inside of the cavity toward the outside of the cavity) L
The length is several times longer than the diameter of 0A. In this embodiment, the length L of the joining region of the sealing cap 6 is about 500 μm.
It consists of. The joining of the base substrate 5 and the sealing cap 6 of the semiconductor device configured as described above is described in Japanese Patent Application No. 2-77331.

As shown in FIGS. 1 and 2, the external terminals 12 of the semiconductor pellet 1 are connected to the bump electrodes 2 through the bonding openings 25a formed in the insulating film 25. Underlying metal layer is provided between the external terminal 12 and the bump electrodes 2 of the semiconductor pellet 1 (BLM: B all L imiting M etaliz
ation) 26. The base metal layer 26 is formed of, for example, a composite film in which a Cr film, a Cu film, an Au film or a Cr film, a Ni film, and an Au film are sequentially deposited.

The external terminals 12 are formed integrally with the uppermost wiring 24. The wiring 24 is electrically connected to the wiring 22 in a lower layer than the wiring 24 through a connection hole 23 a formed in the insulating film 23. The wiring 22 is connected to the element forming the circuit system mounted on the element forming surface of the single crystal silicon substrate 20 with the insulating film 21 interposed therebetween. That is, the semiconductor pellet 1 has a two-layer wiring structure, although not limited to this structure. Each of the insulating films 21, 23 and 25 is formed of, for example, a silicon oxide film. The wiring 24, 22
Are formed of, for example, an aluminum film or an aluminum alloy film.

A base metal layer 38 is formed between the electrode 13 of the base substrate 5 and the bump electrode 2. The base metal layer 38 is formed of the same composite film as the base metal layer 26. Each of the underlying metal layers 26 and 38 ensures the wettability of the bump electrode 2. The electrode 13 is formed integrally with the uppermost wiring 36 of the base substrate 5. Part of the wiring 36 is electrically connected to the wiring 31 in a layer lower than the wiring 36 through a connection hole 35 formed in each of the insulating films 33 and 32. The wiring 31 is the connection hole 3 formed in the insulating film 30.
It is electrically connected to the wiring 4A formed on the mullite substrate 4 through 0a. This wiring 4A is the electrode 14 shown in FIG.
Connected to. Each of the insulating films 32 and 30 is formed of, for example, a polyimito resin, and the insulating film 33 is formed of, for example, a silicon oxide film. Each of the wirings 36 and 31 is formed of, for example, an aluminum film or an aluminum alloy film.

A part of the wiring 36, to which the bump electrode 2 is not connected, is joined to the underlying wiring 31, and the other area, to which the bump electrode 2 is connected, is drawn out from the joining portion onto the insulating film 33. At the same time, it is configured so as to float from the surface of the insulating film 33. That is, in the base substrate 5, a gap is provided between the insulating film 33 and a region (electrode 13) in the other portion where the bump electrode 2 is connected to the uppermost wiring 36, and the region in the other portion of the wiring 36 is separated by the gap. It is configured to be movable.
The base substrate 5 configured as described above absorbs thermal stress generated in a heat treatment step in an assembly process or a temperature cycle which is an environmental test after product completion by the movement of the wiring 36 to form a bump electrode having low mechanical strength. Since the concentrated stress can be relaxed, the bump electrode 2 can be prevented from being damaged.

The semiconductor device having such a structure is shown in FIG.
As shown in FIG. 1, one or a plurality of components are mounted on the mounting surface of the mounting substrate (module substrate or PCB substrate) 40 of the cooling system in a face-down manner. That is, the semiconductor device is mounted on the mounting substrate 40 by electrically and mechanically connecting the electrodes 14 of the base substrate 5 to the electrodes 41 of the mounting substrate 40 via the bump electrodes 11. This semiconductor device includes a mounting substrate 40 and a sealing cap (not shown).
It is sealed in the cavity formed by.

Next, a method of manufacturing the base substrate 5 of the semiconductor device will be briefly described with reference to FIGS. 4 to 6 (cross-sectional views of the essential part shown in each manufacturing step).

First, a ceramic substrate 4 made of mullite and having a multilayer wiring structure is formed. The wiring 4A of the ceramic substrate 4 is formed of, for example, a W film.

Next, for example, a polyimide resin is dropped and coated on the entire surface of the ceramic substrate 4 by a spin coating method, and a baking process is performed to form an insulating film 30 (organic film). After that, the insulating film 30 is patterned in a predetermined pattern to form a connection hole 30a exposing the surface of the wiring 4B.

Next, the insulating film 3 including on the connection hole 30a.
After an aluminum film is deposited on the entire surface of the substrate 0 by, for example, a sputtering method, the aluminum film is patterned with a predetermined pattern to form the wiring 31. The wiring 31 is electrically connected to the wiring 4A through the connection hole 30a.

Next, an insulating film 32 is formed on the entire surface of the insulating film 30 including the wiring 31. The insulating film 32 is formed of a polyimide resin, like the insulating film 30. Then, an insulating film 33 is formed on the entire surface of the insulating film 32.
The insulating film 33 is formed of, for example, a silicon oxide film or a silicon nitride film (inorganic film) deposited by the CVD method. The insulating film 33 is used as an etching stopper in the subsequent manufacturing process.

Next, as shown in FIG. 4, the insulating film 33 is formed.
An insulating film 34 is formed on the entire upper surface. The insulating film 34 is formed of a polyimide resin, like the insulating film 30.

Next, each of the insulating films 34, 33 and 32 is sequentially patterned with a predetermined pattern to form a connection hole 35 in which the surface of the wiring 31 is exposed. This patterning is performed by dry etching or the like with no selection ratio. Then, an aluminum film is deposited on the entire surface of the insulating film 34 including the connection hole 35 by, for example, a sputtering method, and the aluminum film is patterned with a predetermined pattern to form a wiring 36, and the wiring 36 is formed. The electrode 13 formed integrally with the electrode is formed. The wiring 36 is the connection hole 35.
It is electrically connected to the wiring 31 through.

Next, an insulating film 37 is formed on the entire surface of the insulating film 34 including the wiring 36, and the insulating film 37 is patterned with a predetermined pattern so that the surface of the electrode 13 is exposed. 37a is formed. Thereafter, as shown in FIG. 5, a base metal layer 38 is formed on the electrode 13 through the connection hole 37a.

Next, using the insulating film 33 as an etching stopper, the insulating film 37 and the insulating film 34 are removed by wet etching or isotropic dry etching. As a result, part of the uppermost wiring 36 is joined to the lower wiring 31, the other portion of the wiring 36 is pulled out from the joining portion to the periphery thereof, and the base substrate 5 is floated from the surface of the insulating film 33. Is completed.

As described above, the wiring 36 arranged in the uppermost layer of the multilayer wiring layers of the base substrate 5 and the wiring 36 arranged in the uppermost layer of the semiconductor pellet 1 with the bump electrode 2 interposed therebetween. In the semiconductor device to which 24 is connected,
A part of the wiring 36 arranged in the uppermost layer of the base substrate 5 that is not connected to the bump electrode 2 is joined to the wiring 31 in the lower layer than the uppermost layer, and the other area (electrode 13) is drawn out from the joint portion to the periphery thereof and is floated from the surface of the insulating film 33 between the uppermost wiring 36 and the lower wiring 31. With this configuration, the wiring 36 can absorb the thermal stress generated in the heat treatment step in the assembly process or the temperature cycle which is the environmental test after the product is completed, and the stress concentrated on the bump electrode 2 having low mechanical strength can be relaxed. The bump electrode 2 can be prevented from being damaged and the reliability of the semiconductor device can be improved.

Further, the semiconductor pellet 1 of the semiconductor device
Is sealed in the cavity formed by the base substrate 5 and the sealing cap 6 bonded to the base substrate 5 with the sealing material 10 interposed therebetween, and the back surface of the semiconductor pellet 1 has the heat conduction filler material interposed therebetween. Then, the gap t at the joining portion between the base substrate 5 and the sealing cap 6 connected to the pellet connecting surface of the sealing cap 6 is equal to or less than the diameter of the crystal particles 10A of the sealing material 10. It consists of dimensions. With this configuration, the crystal particles 10A of the encapsulating material 10 exist singly in the gap direction of the joint portion between the base substrate 5 and the sealing cap 6,
Since the contraction holes 10B generated at the crystal grain boundaries are not connected to each other, it is possible to prevent the generation of a leak path connecting the inside of the cavity and the outside of the cavity, improve the airtightness of the inside of the cavity, and not absorb the thermal stress at the joint portion. Can be absorbed by the wiring 36 and the stress concentrated on the bump electrode 2 can be relaxed, so that the bump electrode 2 can be prevented from being damaged. As a result, the reliability of the semiconductor device can be improved.

In the structure in which the uppermost wiring 36 of the base substrate 5 is floated from the surface of the insulating film 33, the uppermost wiring 24 of the semiconductor pellet 1 is floated from the surface of the insulating film 23. You may comprise.

Alternatively, the base metal layer 38 of the base substrate 5 may be omitted and the base metal layer 38 may be used to form the wiring 36. Similarly, the base metal layer 26 of the semiconductor pellet 1 is also provided.
The wiring 24 may be formed of the underlying metal layer 26.

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

[0049]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

In a semiconductor device in which semiconductor pellets are mounted face down on the mounting surface of the base substrate, damage to bump electrodes can be prevented.

In a semiconductor device in which a semiconductor cap mounted on the mounting surface of a base substrate by a face-down method is sealed with a sealing cap, the airtightness in the cavity can be improved and the bump electrode can be prevented from being damaged. As a result, the reliability of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device using a face-down method according to an embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view of a main part of the semiconductor device.

FIG. 3 is an enlarged cross-sectional view of a main part of the semiconductor device.

FIG. 4 is a cross-sectional view of a main part showing each step of manufacturing the base substrate of the semiconductor device.

FIG. 5 is a cross-sectional view of an essential part showing each manufacturing step of the base substrate of the semiconductor device.

FIG. 6 is a cross-sectional view of a main part showing each manufacturing step of the base substrate of the semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor pellet, 2 ... Bump electrode, 5 ... Base substrate, 6 ... Sealing cap, 7 ... Thermal conductive filler, 10 ...
Sealing material, 11 ... Bump electrode, 12 ... External terminal of semiconductor pellet, 13, 14 ... Base substrate electrode, 22, 24 ...
Wiring, 31, 36 ... Wiring, 33 ... Insulating film (etching stopper).

Claims (2)

[Claims] 1. A first wiring arranged on the uppermost layer of the multilayer wiring layer of the base substrate is connected to a second wiring arranged on the uppermost layer of the multilayer wiring of the semiconductor pellet through a bump electrode. In the semiconductor device according to the above, a part of the first wiring arranged on the uppermost layer of the base substrate or the second wiring arranged on the uppermost layer of the semiconductor pellet, which is not connected to the bump electrode, is partially formed on the wiring lower than the uppermost layer. Areas of other portions that are joined and connected to the bump electrodes are pulled out from the joined portions to the periphery thereof and float from the surface of the insulating film between the uppermost first wiring or second wiring and the lower wiring. A semiconductor device characterized by being configured in a state. 2. The semiconductor pellet of the semiconductor device according to claim 1 is sealed in a cavity formed by a base substrate and a sealing cap joined to the base substrate with a solder sealing material interposed therebetween. At the same time, a part of the semiconductor pellet is connected to the sealing cap through the heat conduction filler, and the gap between the base substrate and the sealing cap is a crystal of the solder-based sealing material. A semiconductor device characterized by being set to be equal to or smaller than a particle diameter.