JPH0589304A - Memory card - Google Patents

Abstract

PURPOSE:To enable plural users to have the same data, and to enable plural users to have associated data by sharing the same by providing plural memory chips of the storage parts in a memory card, and making these detachable. CONSTITUTION:The memory chips 25a, 25b are fitted detachably to a memory card frame. A chip select circuit 35 stores the same data inputted to a data output terminal 16d to the memory chips 25a, 25b. Besides, it stores the inputted data serially to the memory chips 25a, 25b, or stores the associated input data to the memory chips 25a, 25b by sharing the same. In this way, the plural same data or the associated data are stored in the individual memory, and simultaneously, the individual memory can be divided. Thus, a memory card of which plural persons can have a piece of data while the memory card slot of a memory card camera is one in number is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card used as a recording medium for electronic still cameras and the like.

[0002]

2. Description of the Related Art An electronic photographic system for converting an optical image into an electric signal and displaying an image on a television receiver is disclosed in, for example, JP-A-49-52192.

This electronic photographic system is a cassette or a cover of a tape, disk, drum or the like made of a magnetic material.
This is a system in which a recording medium in the form of a trig is used, mounted on a camera, and a reproduced image is obtained by a television receiver connected to the reproducing device.

Since the recording medium in this system is made of a magnetic material, it has a size that is normally used, and when the memory capacity is taken into consideration, when storing digital data that requires a large capacity. Can store very small amounts of information. Therefore, the analog data is stored, which causes deterioration of image quality.

As a solution to this problem, a memory card camera using a semiconductor memory element is now becoming the mainstream as a recording medium for digital data of photographed images.

A memory card camera in which current digital data is stored in a memory card has only one memory card slot. For this reason, only one person can have the captured image data, and it is impossible for a plurality of people to have the same data. In order to avoid this problem, naturally, it is sufficient to increase the memory card slot of the memory card camera, but as a result, the main body of the memory card camera becomes large.

[0007]

In the above-mentioned conventional memory card, normally, there is only one captured image data, and it is impossible for a plurality of people to have common data, which is solved. It would be better to increase the number of memory cards, but this led to a larger camera body and higher costs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory card in which a plurality of persons can carry one piece of data while the memory card camera has one memory card slot.

[0009]

SUMMARY OF THE INVENTION A memory card according to the present invention makes a semiconductor memory capable of electrically rewriting recorded data and a control circuit of the memory independent, and
A plurality of memories are made detachable and the same image data is recorded in each memory.

[0010]

With the above-described means, a plurality of persons can have the same data or related data by recording a plurality of the same data in the memory by one recording operation.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic perspective view of an electronic still camera according to an embodiment of the present invention. The electronic still camera mainly comprises a camera body 1 and a memory card 2 which can be attached to and detached from the camera body 1. Camera body 1
Is equipped with a lens barrel 3, a viewfinder 4, a shutter 5 and the like as in a normal camera, and has an opening 6 having removable memory chips 25a and 25b into which the memory card 2 is inserted. There is. The memory card 2 functions as a film used in a normal camera.

FIG. 2 is a block diagram shown for explaining the circuit configuration of the camera body 1 of FIG.

Reference numeral 7 denotes a lens. This lens 7 is arranged in the lens barrel 3, and the object image is arranged on the back surface of the lens C.
Project to CD8. The CCD 8 outputs an analog electric signal according to the brightness of the projected image. This electric signal is converted into a digital signal by the A / D converter 9, and then the band is compressed by the band compression circuit 10 and input to the memory card control circuit 11.

Reference numeral 45 is a microphone arranged outside the main body 1, and a voice signal input from the microphone 45 is passed through an A / D converter 46 and a digital voice circuit 47 to a memory card control circuit. Enter in 11.

Reference numeral 12 denotes a CPU, which controls the overall electronic still camera including the memory card 2 and, for example, a CCD via a drive system 13.
8 and the compression ratio of the band compression circuit 10, and also controls the memory card control circuit 11 and the memory card 2.

FIG. 3 shows a memory card control circuit 11
FIG. 3 is a block diagram for explaining the configuration of the and surroundings.

In the figure, 14 is an I / O control circuit for controlling output between the band compression circuit 10 or the CPU 12 and the memory card 2 in order to exchange data signals between them. .. The data input terminal 15 inputs the data signal relating to the image from the band compression circuit 10, and the data input terminal 48 outputs the digital audio circuit 4 of FIG.
The data signal concerning the voice from 7 is input. These data signals and the data signals generated by the CPU 12 are sent to the memory card 2 from the data input / output terminal 16a via the I / O control circuit 14. On the other hand, the data signal supplied from the memory card 2 to the data input / output terminal 16a is sent to the CPU 12 via the I / O control circuit 14.

Here, the CPU 12 and the I / O control circuit 14
A memory 17 is inserted on the data line between the two and the data transfer speed interface between them.
That is, the data signal input / output by the CPU 12 is a low speed because it is a serial signal. Since the data signal input / output by the I / O control circuit 14 is a parallel signal, it has a high speed. The memory 17 converts these serial signals or parallel signals into parallel signals or serial signals, respectively.

Reference numeral 18 denotes an address generating circuit, which sequentially generates an address signal corresponding to an initial address value designated by the CPU 12, and an address value obtained by sequentially adding "1" to this value. It is sent from the address output terminal 19a to the memory card 2.

Reference numeral 20 denotes a timing signal generation circuit. This timing signal generation circuit 20 is based on the designation from the CPU 12, the I / O control circuit 14, the memory 17, the address generation circuit 18, the recording determination circuit 22, and the timing output terminal. A predetermined timing is generated from 21a to the memory card 2.

The recording decision circuit 22 is a circuit for deciding the recording method of the memory card 2. The recording decision circuit 22 sequentially records a plurality of memory chips connected to the memory card 2 or a plurality of memory chips. This is a determination signal for determining whether to write the same data, which is sent from the recording selection output terminal 23a to the memory card 2.

FIG. 4 is a perspective view of the memory card 2. The memory card 2 has a memory card frame 24 and a memory chip which is detachable from the frame 24 and does not have a control circuit for controlling a data signal or an address signal. 25a and 25b.

FIG. 5 is a diagram for explaining the structure of the memory card frame 24 in detail. The memory card frame 24 has a connector 26 connected to the camera body 1 at one end, and openings 27a and 27 into which the removable memory chips 25a and 25b are inserted into the frame 24.
b and the memory chips 25a and 25b are equipped with terminals 28a and 28b for transferring data signals and the like. Further, when the memory chips 25a and 25b are mounted, the projections 29a and 2 are provided on the opposite side surfaces of the opening 27a for stability.
9b, and the projections 30a, 30 on the opposite side surfaces of the opening 27b.
equipped with b.

FIG. 6 is a perspective view of the memory chips 25a and (25b) detachably attached to the openings 27a (27b). This memory chip 25a is mounted on the internal substrate with RA
Although one or more electrically rewritable memories 38 for data such as M or EEPROM are mounted, description will be made assuming that two memories are mounted. The memory chip 25a has a terminal 39 connected to the memory card frame 24 at one end and the memory chip 2 provided with the memory card frame 24.
5a for stabilizing the protrusions 29a, 29b (30a, 30
It has grooves 40a, 40b for receiving b).

The memory chip 25a (25b) is attached by engaging the grooves 40a and 40b with the protrusions 29a and 29b and sliding them to couple the terminals 39 and 28a. The memory chip 25a can be removed from the memory card frame 24 by performing the reverse operation.

FIG. 7 shows such a memory card frame 2.
4 is a block diagram for explaining the circuit configuration of FIG.

Reference numeral 16b is a data output / input terminal connected to the data input / output terminal 16a on the camera body 1 side. The data output / input terminal 16b is connected to the I / O control circuit 32 through the I / O control circuit 32. It is sent to the O output terminal 33.

Further, 19b is an address input terminal connected to the address output terminal 19a on the camera body 1 side,
The address input terminal 19b is directly connected to the memory chip connectors 34a and 34b and is also connected to the chip select circuit 35 in the frame. Reference numeral 23b is a recording selection input terminal connected to the recording selection output terminal 23a on the camera body 1 side, and the recording selection input terminal 23b is connected to the chip select circuit 35. Furthermore, the camera body 1
The timing input terminal 21b connected to the side timing output terminal 21a is the same as the timing input terminal 21b.
From the memory chip connectors 34a and 34b. The memory chip connectors 34a and 34b are connected to the memory chips 25a and 25b.

The operation of the chip select circuit 35 will be described. Here, it is assumed that the memory in the memory chips 25a and 25b is 1 MB and the address input signal is 18 bits. The chip select circuit 35 inputs the 18th bit of the address input signal supplied to the address input terminal 19b and the recording selection signal supplied to the recording determination input terminal 23b. First, the address 18th bit is decoded to determine whether it is 0 or 1. If the result is 0 and the recording selection signal is in the sequential mode, only the output 35a is active. When the recording selection signals are in the same mode, the outputs 35a and 35c are activated. When the decoded result is 1, when the recording selection signal is the sequential mode, only 35b is active, and when the recording selection signal is the same mode, the outputs 35b and 35d are active.

As described above, in the sequential mode, one of the chip select signals becomes active, and in the same mode, the chip select for all the memory chips mounted on the memory card frame. The signal becomes active. Even when the memory capacity and the address signal are different from this assumption, the chip select signal is sent to the memory chips 25a and 25b as in this example.

FIG. 8 shows such a memory chip 25a (2
It is a block diagram for demonstrating the circuit structure of 5b).

41a is an I of the memory card frame 24.
The data input / output terminal 41a is connected to the / O output 33, and the data input / output terminal 41a is connected to each data input / output terminal of the memory 38. 41b is a memory card frame 24
The address input terminal 41b is connected to the output 35a of the memory. The address input terminal 41b is connected to each address input terminal of the memory 38.

41c and 41d are chip select circuits 3
5 is a select terminal for supplying the chip select signals 35a and 35b, and is connected to the chip select terminal of the memory 38. Further, 41e is a memory card frame 24.
Is a timing signal to be connected to the output 35 c of the memory 38 and is connected to the timing input terminal of the memory 38.

As described above, the memory chips 25a, 2
By having 5b held by a plurality of users, a plurality of users can have the same data. For example, if there are memory chips A, B, and C, a plurality of users can use these memories as dedicated memories, so that even if an expensive memory card is used, there will be no problem in management.

The present invention is not limited to the above-described embodiment, but a plurality of memories are recorded by distinguishing them by patterns, and a landscape is recorded in the memory A and a person is recorded in the memory B to manage the editing. It will be easier.

[0037]

As described above, according to the memory card of the present invention, the same data can be stored by providing a plurality of memory chips, which are storage units in the memory card, and by making them removable. It is possible for a plurality of users to have the data, or for a plurality of users to have associated data separately.

[Brief description of drawings]

FIG. 1 is a perspective view schematically showing an embodiment of the present invention.

FIG. 2 is a block diagram showing the circuit configuration of FIG.

FIG. 3 is a block diagram showing a configuration of a main part and its peripheral part shown in FIG.

FIG. 4 is a perspective view of the memory card of the present invention.

5 is a perspective view showing a state in which a part of FIG. 4 is removed.

FIG. 6 is a perspective view showing a part of FIG. 4 removed.

FIG. 7 is a block diagram showing the internal circuit configuration of FIG.

FIG. 8 is a circuit block diagram of a main part shown in FIG.

[Explanation of symbols]

2 ... Memory card, 9 ... A / D converter, 11 ... Memory card control circuit, 12 ... CPU, 14,
29 ... I / O control circuit, 17, 38 ... Memory, 18 ...
Address generation circuit, 20 ... Timing signal generation circuit,
22 ... Recording method selection circuit, 24 ... Memory card frame, 25a, 25b ... Memory chip, 33 ... Chip select circuit.

Claims (4)

[Claims] 1. A semiconductor memory comprising a plurality of memory chips, signal connecting means for transmitting and receiving data signals, address signals and control signals, means for controlling input / output of the data signals, and the address signals. And the control signal
A memory card main body having a means for generating a control signal for the semiconductor memory, and a means for detachably attaching at least one memory chip among a plurality of memory chips constituting the semiconductor memory to the memory card main body. A memory card comprising: 2. The memory card according to claim 1, wherein the control signal for the semiconductor memory simultaneously writes data signals input to at least two or more memory chips. 3. A control signal external to the main body of the memory card is used to select whether or not to generate a control signal so as to write input data into any one of the plurality of memory chips. 2. A memory card according to claim 1, further comprising means. 4. The memory card according to claim 1, wherein the removable memory chip is sealed in the memory card main body when mounted.