JPH0589262A - Processor address setting system - Google Patents

Abstract

PURPOSE:To impart and set individual addresses to plural processors by software with the conventional constitution of hardware. CONSTITUTION:A shift register 5 is provided for data exchange among plural processors P1 to P4. Prescribed value '0b is imparted one terminal of the shift register 5. An input means 102 imparts initial address to a prescribed register in a processor. A shift means 103 transfers contents of the prescribed register to the shift register 5 and shifts them by one stage, and an arithmetic means 105 compares contents of the prescribed register and those in the corresponding stage of the shift register with each other and holds contents of the prescribed register as they are in the case of disaccord between them but writes the result, which is obtained by subjecting contents of the shift register 5 to prescribed operation, in the prescribed register in the case of coincidence between them. A discriminating means 106 repeats the operation of the arithmetic means 105 and the shift means 103 and discriminates the frequency in repeat of this loop and terminates the processing at the time of arrival at a presribed frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to SIMD (single i
nstrution multiple data) multiple DSPs
The present invention relates to a processor address setting method suitable for a signal processing system that performs parallel signal processing using (digital signal processor) (hereinafter simply referred to as a processor).

[0002]

2. Description of the Related Art A system has been developed which processes a video signal in parallel using a plurality of processors. The reason for using a plurality of processors is that one processor cannot secure a sufficient calculation processing time for one piece of data due to the high sampling rate of the video signal. When a plurality of processors, for example, a number of processors corresponding to the number of pixels for one scanning line are used in parallel, pixels for one scanning line can be processed in parallel, and one processor can process one pixel for one scanning period. Can afford For video signals, 1
Since the same contents are often processed for each pixel in the horizontal period, in such a case, each processor is driven by using the same program.

FIG. 3 shows an example of the configuration of a conventional digital signal processing device. Input terminal 200 has a sampling rate of 4
A digital video signal of fsc (fsc: color carrier frequency) is supplied and transferred by the shift register 201. The shift register 201 has, for example, 910 stages (corresponding to one scanning line), and a processor 202 is connected to each stage. That is, the shift register 201 converts parallel serial data. Multiple processors 20
2 performs arithmetic processing on each input pixel and outputs it.
The output of each processor 202 is input to each stage of the shift register 206. The shift register 206 converts the parallel data into serial data and outputs the serial data to the output terminal 207.

When data needs to be exchanged among a plurality of processors 202, a shift register 210 for communication is used as shown in FIG. In other words, the output of the processor is shifted to the right or the left as much as necessary so that the output of the processor is taken into the desired processor.

In the processing of the video signal, the arithmetic processing for each pixel often has exactly the same contents, so that the programs having the same contents are set in each processor 202. As described above, a method of causing a plurality of processors to perform the same processing to process a plurality of data in parallel is SIMD.
It is called a method. In this system, since the programs of the respective processors are exactly the same, it is not necessary for each processor to have an independent program, and it is sufficient for the entire system to have one program memory. Therefore, there is an advantage that the system scale can be reduced by sharing the program memory.

On the other hand, however, there are disadvantages of the SIDM system. For example, consider the case where only the pixel at a certain coordinate on the scan line is desired to be processed. In this case, in the SIDM system, since it is desired to process a specific pixel, it is not possible to change only the program of the processor that inputs the pixel. In such a case, each processor is given information about what position the processor corresponds to in the entire system, that is, an address, and the address is stored in a register or the like. Then, a method in which a conditional branch instruction for referencing this address is provided in the processing program and the processing is switched by the conditional branch is adopted.

FIGS. 4A and 4B are diagrams for explaining an example of using the above method. In this example, four processors are used. Now, in this system, the processors 402 and 403 output the input values as they are, and the processors 404 and 405 output 0 regardless of the input values.

First, address data is stored in the internal register of each processor. For example, when one of the internal registers of the processor is the register R1, the address data 1 to 4 are stored respectively. This is processor 4
Addresses 02, 403, 404, and 405 are shown.

A program as shown in FIG. 4B is set in each processor. That is, in branch 501, first, it is determined whether or not the own address is 2 or more. If it is 2 or more, the process proceeds to step 502, the output is set to 0, and if it is 2 or less, the process proceeds to step 503. Perform the process of shifting and outputting the input as it is. As a result, the processors 402 and 403 output the input values as they are, and the processors 404 and 405 output 0 regardless of the input values, so that the above wish can be realized.

Next, when the above step 501 is provided, it is necessary to set a different address for each processor. Conventionally, a method of preliminarily storing each processor in hardware is adopted. However, this takes a lot of time due to the large number of processors. So let's think about how to set it automatically.

The example shown in FIG. 5A is a shift register 2
This is an example in which the selector 601 is provided in the input unit of 01. The selector 601 can selectively supply the address signal 602 and the video signal 603 to the shift register 201. In the address setting mode, the selector 601
Selectively introduces the address signal 602. The address signal is synchronized with the horizontal synchronizing signal, and is 0 for each pixel.
From the counter output, for example. It is reset when the number of pixels for one scanning line is reached. Therefore, if the number of pixels of one scanning line is 910, the address signal becomes a sawtooth wave that repeats from 0 to 909 (see FIG. 7B). Since this repetition is synchronized with the horizontal synchronizing signal, this address signal becomes the address of the processor 202 (910th to 1st) as it is. This address is fetched and set in the register of each processor 202. After this address setting, the selector 601 selects the video signal and stores it in the shift register 201.

FIG. 6 shows another example. In this example, the output from the selector 802 is directly supplied to each processor 202. The output from the counter 801 is supplied to the input of the selector 802.
Also in this case, the counter 801 is synchronized with the horizontal synchronization signal to increase from 0 to 1 pixel at a time, and the output of the selector 802 is switched in synchronization with this increase so that each processor 2
You can enter a different address in 02. After that, the address stored in the register of each processor 202 is used as described in the above flowchart.

[0013]

According to the above-mentioned address setting method, it is necessary to add some hardware to configure the system in each method. This hardware has a large effect on the hardware configuration, although it has only a small function for giving an address to the processor.

In view of this, the present invention provides a processor address setting system in which individual addresses can be given to and set by a plurality of processors by software even if the hardware has a conventional configuration. To aim.

[0015]

According to the present invention, a first shift register for taking in serial data and performing parallel conversion and a same program for taking in parallel conversion outputs of the first shift register and performing arithmetic processing are the same. A parallel operation type signal processing device having a plurality of processors having a configuration and a second shift register for taking outputs of the plurality of processors in parallel and converting the outputs into a serial output,

A third shift register provided between the processors for exchanging data of the plurality of processors to shift data, and a third shift register for giving a predetermined value to one end of the third shift register. One input means, a plurality of processors for providing an initial processor address to a predetermined register, and a second input means for providing each processor with the contents of the predetermined register corresponding to the stage of the third shift register. And a shift means for shifting to one side by one step, and the contents of the predetermined register and the third register provided in each processor next to the operation of the shift means.
And the contents of the corresponding stages of the shift register are compared, and if different, the predetermined register is held in the predetermined register as it is, and if the same, the result of performing a predetermined operation on the contents of the third shift register is obtained. An arithmetic means for writing in the predetermined register and an operation of the shift means are executed from the processing of the arithmetic means to determine the number of repetitions of the loop,
And a determining unit that ends the process when the number of times reaches a predetermined number.

[0017]

According to the above means, the communication means between the processors of the SIMD type processor can be used to set its own processor address by software, and the processor is provided with the address arithmetic means of the same format. Just add it.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 (B) is a basic configuration of an embodiment of the present invention, and FIG. 1 (A) is a flow chart shown for explaining the operation thereof. In this example, four processors P1, P2, P3, P4 and a register 5 for inter-processor communication are extracted and shown. Further, FIG. 3A shows the address setting routine incorporated in each processor. At the left end of the shift register 5, 0 is always input when the shift is made.

In step 101, 1 is stored in the register R1 of each processor. In the next step 102,
The contents of register R1 are transferred to the corresponding stages of the shift register. Next, the data in the shift register 5 is shifted to the right by one stage. Next, at step 104, the contents of the corresponding stage of the shift register 5 and the contents of its own register R1 are compared. Here, if they are different, the contents of the shift register are stored in their own register R1 (step 10).
7) If they are different, the operation of +1 is performed on R1 and the result is stored in the register R1 as its own processor address. Then, the process proceeds to step 106, where (n-
2) It is determined whether or not the process has been performed once (n is the number of processors). FIG. 2 specifically shows how the data changes when the above processing is performed. The processor is shown as executing one instruction per clock.

At clock 1, each processor executes step 101 and stores a 1 in register R1. At clock 2, each processor executes step 102 and inputs the value of register R1 into the corresponding stage of shift register 5. At clock 3, each processor executes step 103 to shift the shift register 5 to the right by one step. At this time, 0 is input to the leftmost side of the shift register 5.

At clock 4, each processor performs step 104 to compare the value stored in register R1 within each processor with the value stored in the shift register in direct communication with each processor. .. When the two values are equal, each processor executes step 105 at clock 5, increments the content of the register R1 by 1 and stores it in the register R1 again. When the two values are different, each processor executes step 107, and the value of the register R1 is stored as it is. At clock 5, the processors P2, P3, and P4 execute step 105 to increase the value stored in the register R1 by 1 to 2. The value stored in the register of the processor P1 remains unchanged. Then, the clock 6 is used to confirm how many times these processes have been performed, and it is determined whether the processes have been completed or repeated. In this example, addresses are given to all processors.
When the number of processors is n, (n-2) times of processing is required. Further, in this example, the number of processors is 4, so the required number of loops is 2. At clock 6, the number of loops is zero. Therefore, the process returns to step 102.

The processing of clock 7 to clock 11 is the same as the processing of clock 2 to clock 6, but the processing of clock 9
Then, the processors P3 and P4 execute the step 105,
The value stored in the register R1 is incremented by 1 to 3. Since the processors P1 and P2 execute step 107, the value stored in the register R1 remains unchanged. Further, at the clock 11, since the number of loops is 1, the process returns to step 102.

The processing of clocks 12 to 16 is the same as the processing of clocks 2 to 6, but clock 1
In 4, the processor P4 executes step 105 to increase the value stored in the register R1 by 1 to 4. Processor P1
.. through P3 execute step 107, so the value of the register R1 remains unchanged. Further, at the clock 16, the number of loops becomes 2, so the processing ends.

By setting the addresses as described above, addresses 1 to 1 are assigned to the processors P1 to P4, respectively.
4 will be set. Each processor stores different addresses even though it processes the same program at the same timing and at the same timing.

[0026]

As described above, according to the present invention,
Even if the hardware has the conventional configuration, it is possible to give individual addresses to a plurality of processors and set them by software.

[Brief description of drawings]

FIG. 1 is a flowchart and a basic configuration diagram showing an embodiment of the present invention.

FIG. 2 is an operation explanatory view shown for explaining the operation of the device of the present invention.

FIG. 3 is an explanatory diagram of a configuration of a parallel type arithmetic signal processing device.

FIG. 4 is an explanatory diagram showing an example of signal processing using processor addresses of a parallel type arithmetic signal processing device.

FIG. 5 is a diagram showing an example of setting a processor address, which is a premise of the present invention.

FIG. 6 is a diagram showing a setting example of another processor address which is also a premise of the present invention.

[Explanation of symbols]

 P1 to P4 ... Processor, 5 ... Register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoshi Hoshino 8 Shinshinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture

Claims (3)

[Claims] 1. A first shift register for taking in serial data and performing parallel conversion, a plurality of processors having the same configuration and operating with the same program for taking in parallel conversion outputs of the first shift register and performing arithmetic processing, In a parallel operation type signal processing device having a second shift register which takes in outputs of a plurality of processors in parallel and converts them into a serial output, provided between the processors for exchanging data of the plurality of processors. A third shift register for shifting the received data, a first input means for giving a predetermined value to one end of the third shift register, and a plurality of processors provided with an initial processor address in the predetermined register. Second input means for giving and contents of the predetermined register provided in each processor Shift means for moving to a corresponding stage of the shift register and shifting one stage to one side, and provided to each processor, next to the operation of the shift means, the contents of the predetermined register and the correspondence of the third shift register If the difference is different, the predetermined register is held in the predetermined register as it is, and if the same, the result obtained by performing a predetermined operation on the content of the third shift register is written in the predetermined register. A processor address setting method comprising: a computing unit; and a determining unit that executes the operation of the shift unit from the processing of the computing unit, determines the number of times the loop is repeated, and terminates when the number of times reaches a predetermined number. 2. The arithmetic means determines the value of the content of a predetermined register of its own processor when the content of the predetermined register of the adjacent processor is greater than or equal to the content of the predetermined register of its own processor in the comparison result. 2. The processor address setting system according to claim 1, further comprising means for creating its own address data by an operation of incrementing by one. 3. The arithmetic means determines the value of the content of the predetermined register of the own processor when the content of the predetermined register of the adjacent processor is greater than or equal to the content of the predetermined register of the own processor in the comparison result. 2. The processor address setting system according to claim 1, further comprising means for generating its own address data by a calculation for reducing by one.