JPH0589212A - Simulating method for semiconductor element - Google Patents

Abstract

PURPOSE:To shorten the computing time of simulation of a semiconductor element by numeric value calculation. CONSTITUTION:Repetitive calculation in the simulation of the semiconductor element is performed by selecting S8 a lattice point area with an error over a constant value from error distribution obtained in convergence decision step S6, updating S9-S12 the value by computing only the area by supplying a boundary condition for a selected area when the selected area is smaller than the whole, repeating procedure to select the next analysis area for the area with the error over the constant value again, and solving the whole by an ordinary repetitive solution S14 at a stage where all the lattice points are housed in a certain range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation method for evaluating the characteristics of semiconductor devices by numerical calculation.

[0002]

2. Description of the Related Art As a method of simulating a semiconductor element, a method of cutting a mesh in a semiconductor element region and solving a basic equation by numerical calculation is known.

FIG. 4 shows such a conventional semiconductor device simulation algorithm. Briefly explaining this algorithm, the simulation is started in step S25, and the calculation conditions are input in step S26. In step S27, the correction amount is calculated at all grid points to be analyzed, and in step S28, the value of each grid point is updated from the result. Then, in step S29, it is determined whether or not it has converged. If it has not converged, the process returns to step S27, and this procedure is repeated until it converges. If it converges, it is determined in step S30 whether the whole calculation is completed.
Return to 26 and repeat the above steps.

In this conventional algorithm, if there is at least one grid point having a large correction amount, the correction amount must be calculated for all grid points each time, and therefore the calculation time becomes long.

[0005]

As described above, when performing the numerical calculation in the conventional semiconductor device simulation, the correction amount has to be calculated for all the lattice points every time, and there is a problem that the calculation time becomes long. It was An object of the present invention is to provide a semiconductor element simulation method capable of obtaining a solution in a shorter calculation time than ever before.

[0006]

According to the present invention, in the simulation of a semiconductor device by numerical calculation, the distribution of the correction amount (change amount) after updating the values for all the lattice points is investigated, and the correction is performed at a certain value or more. Repeated the procedure of selecting the region with a certain amount and giving the boundary condition only to that region and performing the next calculation, so that the whole amount of correction of all grid points was within a certain range and the whole was solved. It is characterized by

[0007]

When the mesh is cut in the semiconductor element region and the correction amount is calculated by numerically calculating all the lattice points, the correction amount of each lattice point is different for each lattice point and has a distribution within the element region. If a grid point having a certain correction value or more is selected, the area is naturally smaller than the entire area. The distribution and shape of the area changes depending on the set constant value, but if you update the value only for that area and perform the next calculation, the calculation time will be longer than when iterative calculation is performed for all grid points. Is shortened. In this case, if the constant value for selecting the region is sufficiently small, a large calculation error does not occur even if the grid point having a correction amount less than that is excluded from the analysis region.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an algorithm for semiconductor device simulation using an implicit method according to an embodiment of the present invention. In step S1, the element structure and other input data are input and the calculation starts. Input data to be calculated is read in step S2, a coefficient matrix is generated for the entire region discretized using the mesh in step S3, and the coefficient matrix is solved using the matrix solving method in step S4.

The correction amount obtained in step S4 is added to the trial value in step S5 to update the value of each grid point, and it is determined in step S6 whether or not the values have converged. If it has converged, it is judged in step S7 whether or not the calculation is completed. If it is completed, the whole calculation is completed (step S7).
15). If all calculations have not been completed, the process returns to step S2 to update the input data and perform the next calculation. The above basic procedure is the same as the conventional one.

If convergence does not occur in step S6, a region having an error equal to or greater than a certain value is selected from the error distribution in step S8. This constant value is a value that can be arbitrarily set depending on the usage conditions. Then, in step S9, the area selected in step S8 is changed to step S1.
Is smaller than the entire area defined by
If they are the same, the process returns to step S2. This is the case far from convergence.

If the area selected in step S8 is smaller than the entire area defined in step S1, a boundary condition is given to the selected area in step S10.
A coefficient matrix is generated only for the selected region, the determinant is solved in step S11, and the value is updated in step S12. Then, in step S13, step S11
It is judged whether or not there is a value greater than or equal to a certain fixed value (this value can also be arbitrarily set depending on the usage conditions) out of the amount of change obtained in. , Return to step S8 and repeat the same procedure.

If it is determined in step S13 that there is no fixed value or more, in step S14,
Using the values obtained by the series of procedures up to this point as trial values,
The entire area defined in step S1 is solved by the usual Newton iterative solution until it converges. After convergence, the procedure of determining whether or not the calculation is completed is repeated in step S7.

According to this embodiment, the size of the matrix solved in step S11 is smaller than the matrix solved in steps S4 and S14. For example, as shown in FIG. 2, the number of grid points in the selected area can be reduced to 25, as indicated by the diagonal lines, by selecting the area where the error is equal to or greater than a certain value, which should be calculated at all grid points 81. As described above, the size and shape of the selected area differ depending on the set constant value. The smaller the matrix, the shorter the calculation time. Further, when the values obtained by the series of procedures from step S3 to step S13 are used as trial values, these values are close to the convergent solution to be obtained, and thus the usual Newton iteration of step S4 can be reduced accordingly. As a result, the total calculation time is shorter than that of the conventional method.

FIG. 3 shows an algorithm for semiconductor device simulation of an embodiment using the explicit method. Step S
Input the device structure and other input data at 16 and start the calculation. The input data calculated in step S17 is read in, the correction amount is calculated for all grid points in the analysis area, and the values are updated for all grid points in step S18.

In step S19, it is checked whether or not there is a grid point whose correction amount calculated in step S18 is a certain value or more, and if there is, in step S20, only the grid point selected in step S19 is checked. The next correction amount is calculated, and the process returns to step S19 again.

If there is no grid point having a correction amount equal to or greater than a certain value in step S19, the process proceeds to step S21, the correction amount is calculated for the entire area, and the value is updated. Then, in step S22, it is determined whether or not it has converged. If it has not converged, the process returns to step S21 again to calculate the correction amount, and this procedure is repeated until it converges. After convergence, step S
At 23, it is judged whether or not all the calculations have been completed, and if not completed, the procedure returns to step S1 to update the input data,
Repeat the same procedure.

Also in this embodiment, steps S19 and S
It is possible to reduce the total number of calculations by selectively calculating only the grid points having a modification amount of 20 or more, which is a fixed value or more. When the value calculated in this way is used as a trial value and the iterative calculation is performed in steps S21 and S22, the value close to the solution to be obtained is given as the trial value, and the calculation is completed with a small number of iterations.

[0019]

As described above, according to the present invention, when a semiconductor device is simulated by numerical calculation, a region having a correction amount equal to or larger than a certain value is selected and only the region is iteratively calculated. , The number of grid points to be calculated can be reduced, and the calculation time can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart of a semiconductor device simulation using an explicit method according to an embodiment of the present invention.

FIG. 2 is a diagram showing how a rectangular mesh and some grid points thereof are selected.

FIG. 3 is a flowchart of a semiconductor device simulation using an implicit method according to another embodiment of the present invention.

FIG. 4 is a flowchart of a conventional semiconductor device simulation.

[Explanation of symbols]

 S1 to S14 ... Processing steps.

Claims (1)

[Claims] 1. In a method for simulating a semiconductor device by numerical calculation, the distribution of correction amounts after updating the values for all grid points is examined, and a region having a correction amount of a certain value or more is selected, A method for simulating a semiconductor device characterized in that the procedure of giving the boundary condition only for the region and performing the next calculation is repeated to solve the whole after the correction amounts of all the lattice points are within a certain range. ..