JPH058883B2 - - Google Patents
Info
- Publication number
- JPH058883B2 JPH058883B2 JP61033904A JP3390486A JPH058883B2 JP H058883 B2 JPH058883 B2 JP H058883B2 JP 61033904 A JP61033904 A JP 61033904A JP 3390486 A JP3390486 A JP 3390486A JP H058883 B2 JPH058883 B2 JP H058883B2
- Authority
- JP
- Japan
- Prior art keywords
- electrical component
- circuit board
- line
- package
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Waveguide Connection Structure (AREA)
- Waveguides (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は集積化回路等を含む回路基板の実装方
式に係り、特に超高周波帯にて複雑な回路配線を
可能とする回路基板の実装構造および方法に関す
る。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a mounting method for a circuit board including an integrated circuit, etc., and particularly to a mounting structure and structure of a circuit board that enables complicated circuit wiring in an ultra-high frequency band. Regarding the method.
従来、例えばTTL（Transistor Transistor
Logic）などの集積化回路（以下ICという）は
DIP（Dual in Package）形のパツケージに実装
され、エポキシ系のプリント基板に半田付けされ
ることが多かつた。しかし、1GHzを超すような
超高周波帯においては、電極の自己インダクタン
スや浮遊容量による帯域特性の劣化を防ぐため
に、特開昭59−218762号公報及び第４図に示す如
く、セラミツク製のLCC（Leadless chip
carrier）パツケージにICを実装することが多い。
第４図において５２は電極である。
Conventionally, for example, TTL (Transistor
Integrated circuits (hereinafter referred to as ICs) such as
It was often mounted in a DIP (Dual in Package) type package and soldered to an epoxy printed circuit board. However, in ultra-high frequency bands exceeding 1 GHz, in order to prevent deterioration of band characteristics due to self-inductance and stray capacitance of electrodes, ceramic LCC ( Leadless chip
carrier) ICs are often mounted in the package.
In FIG. 4, 52 is an electrode.
また。反射波による波形劣化を防ぐために、
ICの入出力端子において配線の線路インピーダ
ンスと整合をとる必要がある。線路インピーダン
スの値は、通常、ICの入力容量による帯域劣化
を考慮して数10Ωが選ばれている。1GHzを超す
ような高周波帯まで数10Ωの線路として動作する
線路形式として、第３図に示すようなマイクロス
トリツプ線路等の誘電体線路が知られている。第
３図において４１は誘電体基板、４２は接地導
体、４３〜４５はストリツプ導体である。基板４
１の誘電率ε，厚さｈ，ストリツプ導体４３〜４
５の幅Ｗが決まると、線路の特性インピーダンス
は一義的に定まる。 Also. To prevent waveform deterioration due to reflected waves,
It is necessary to match the line impedance of the wiring at the input and output terminals of the IC. The value of the line impedance is usually selected to be several tens of ohms, taking into consideration band deterioration due to the input capacitance of the IC. A dielectric line such as a microstrip line as shown in Fig. 3 is known as a line type that operates as a line of several tens of ohms up to high frequency bands exceeding 1 GHz. In FIG. 3, 41 is a dielectric substrate, 42 is a ground conductor, and 43 to 45 are strip conductors. Board 4
dielectric constant ε of 1, thickness h, strip conductor 43-4
Once the width W of 5 is determined, the characteristic impedance of the line is uniquely determined.
従つて、LCCパツケージに実装されたICをマ
イクロストリツプ線路を用いて配線することによ
り、超高周波まで動作する回路を実現することが
出来る。しかしながら、マイクロストリツプ線路
は２本の線路を交叉させることが出来ない。第３
図に示す如く、ボンデイングワイヤ４６にて２本
の線路を交叉させ得るが、ワイヤ４６の自己イン
ダクタンスによる高周波特性劣化が生じる。この
ため、互いに交叉するような複雑な配線ができな
かつた。 Therefore, by wiring an IC mounted in an LCC package using microstrip lines, it is possible to realize a circuit that operates up to ultra-high frequencies. However, microstrip lines cannot cross two lines. Third
As shown in the figure, although the two lines can be crossed using the bonding wire 46, the high frequency characteristics deteriorate due to the self-inductance of the wire 46. For this reason, complicated wiring such as crossing each other was not possible.
本発明の目的は、例えば1GHzを超えるような
超高周波帯においても良好な線路特性を有する誘
電体線路を用いて、複雑な回路配線を可能とする
基板実装構造および方法を提供することにある。
An object of the present invention is to provide a board mounting structure and method that enables complex circuit wiring using a dielectric line that has good line characteristics even in an ultra-high frequency band exceeding 1 GHz, for example.
本発明は、LCCパツケージの上下にマイクロ
ストリツプ線路による配線基板を設け、配線が交
叉するような複数な回路配線を可能となしたこと
を特徴とする。
The present invention is characterized in that a wiring board with microstrip lines is provided above and below an LCC package, thereby making it possible to have a plurality of circuit wirings in which the wiring lines intersect.
以下、本発明の一実施例を第１図及び第２図に
より説明する。第１図は上からみた透視図、第２
図は第１図の−線断面図である。LCCパツ
ケージ１の上下をセラミツク基板２，３にて挾ん
でいる。２０及び３０は接地導体、２１〜２７及
び３１〜３３はストリツプ導体であり、各々マイ
クロストリツプ線路を構成している。第１図で
は、LCCパツケージ１の上に実装したセラミツ
ク基板３及びストリツプ導体３１〜３３を破線に
て示している。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. Figure 1 is a perspective view from above, Figure 2
The figure is a sectional view taken along the line -- in FIG. The top and bottom of the LCC package 1 are sandwiched between ceramic substrates 2 and 3. 20 and 30 are ground conductors, and 21 to 27 and 31 to 33 are strip conductors, each of which constitutes a microstrip line. In FIG. 1, the ceramic substrate 3 and strip conductors 31 to 33 mounted on the LCC package 1 are indicated by broken lines.
実装方法は、従来のハイブリツドICにおける
半田付と同様に、まず、セラミツク基板３に
LCCパツケージ１の電極を半田付し、次にLCC
パツケージ１の他方の電極を基板２に半田付けす
ればよい。LCCパツケージ１を基板２に半田付
けする際に、LCCパツケージ１の温度勾配によ
りLCCパツケージ１と基板３との間の半田が解
けることは無く、半田付けによる信頼性の高い実
装が可能となる。なお、電源のバイパスコンデン
サやインピーダンス整合用の抵抗等も、チツプコ
ンデンサやチツプ抵抗等を、従来のハイブリツド
ICと同様に実装できることは言うまでもない。
また、接地導体３０は、図では省略しているが、
セラミツク基板２，３にスルーホールを設け、
LCCパツケージ１の接地電極端子を介して接地
導体２０と接続することにより、接地電位を保つ
ことができる。 The mounting method is the same as soldering in conventional hybrid ICs.
Solder the electrodes of LCC package 1, then
The other electrode of the package 1 may be soldered to the substrate 2. When the LCC package 1 is soldered to the board 2, the solder between the LCC package 1 and the board 3 will not melt due to the temperature gradient of the LCC package 1, and highly reliable mounting by soldering is possible. Note that chip capacitors, chip resistors, etc. for power supply bypass capacitors and impedance matching resistors can be replaced with conventional hybrid
Needless to say, it can be implemented in the same way as an IC.
In addition, although the ground conductor 30 is omitted in the figure,
Through holes are provided in the ceramic substrates 2 and 3,
By connecting to the ground conductor 20 via the ground electrode terminal of the LCC package 1, the ground potential can be maintained.
なお、本実施例ではICのLCCパツケージ１を
介して、上下のセラミツク基板（誘導体線路）間
を接続したが、チツプコンデンサやチツプ抵抗な
どの受動素子や単に金属片を介して上下の基板間
を接続しても同様な効果があることはいうまでも
ない。 In this example, the upper and lower ceramic substrates (dielectric lines) are connected via the LCC package 1 of the IC, but it is also possible to connect the upper and lower substrates via a passive element such as a chip capacitor or a chip resistor, or simply a piece of metal. Needless to say, the same effect can be obtained even if the two are connected.
また、基板３の寸法がLCCパツケージ等の寸
法と比較して極端に大きくなければ、基板３を支
える特別な工夫は必要としないであろう。しか
し、基板３の寸法が大なる場合には、基板２と３
の間にダミーの支柱を数個所にわたり半田付けす
れば強度的にも強い回路基板が実現できる。 Furthermore, unless the dimensions of the substrate 3 are extremely large compared to the dimensions of the LCC package, etc., no special measures to support the substrate 3 will be necessary. However, if the size of the board 3 is large, the board 2 and 3
If you solder several dummy supports in between, you can create a strong circuit board.
本発明によれば、簡単な構成により、配線が互
いに交叉するような複雑な回路をマイクロストリ
ツプ線路により配線することが可能となり、超高
周波帯まで良好に動作する複雑な回路を実現する
ことができる。
According to the present invention, with a simple configuration, it is possible to wire a complex circuit in which the wires intersect with each other using microstrip lines, and to realize a complex circuit that operates well up to ultra-high frequency bands. I can do it.
第１図は本発明の一実施例を示す透視図、第２
図は第１図の−線断面を示す側面図、第３図
は従来のマイクロストリツプ線路とボンデイング
ワイヤによる配線の交叉を示す斜視図、第４図は
従来のLCCパツケージの外観図である。
１……LCCパツケージ、２，３……セラミツ
ク基板、２０，３０……接地導体、２１〜２７，
３１〜３３……ストリツプ導体。
FIG. 1 is a perspective view showing one embodiment of the present invention, and FIG.
The figure is a side view showing the cross section taken along the line - in Fig. 1, Fig. 3 is a perspective view showing the intersection of a conventional microstrip line and bonding wire wiring, and Fig. 4 is an external view of a conventional LCC package. . 1... LCC package, 2, 3... Ceramic substrate, 20, 30... Ground conductor, 21 to 27,
31-33...Strip conductor.
Claims (1)
において、上記電気部品を、誘電体線路を構成す
る少くとも２枚の基板で挟み、上記電気部品の電
極を上記２枚の基板の各誘体線路に接続したこと
を特徴とする回路基板実装構造。 ２ 集積化回路等の電気部品を実装する回路基板
において、誘電体線路を構成する第１，２の基板
の間に上記集積化回路等の電気部品を設け、上記
第１の基板に上記電気部品の一方の電極を半田付
し、該電気部品の他方の電極を上記第２の基板に
半田付し、上記電気部品の両電極を上記第１，第
２の基板の各誘電体線路に接続することを特徴と
する回路基板実装方法。[Scope of Claims] 1. In a circuit board on which an electrical component such as an integrated circuit is mounted, the electrical component is sandwiched between at least two substrates forming a dielectric line, and the electrode of the electrical component is sandwiched between the two substrates. A circuit board mounting structure characterized in that the circuit board is connected to each dielectric line of the board. 2. In a circuit board on which an electrical component such as an integrated circuit is mounted, the electrical component such as the integrated circuit is provided between the first and second substrates constituting the dielectric line, and the electrical component is mounted on the first substrate. one electrode of the electrical component is soldered, the other electrode of the electrical component is soldered to the second substrate, and both electrodes of the electrical component are connected to each dielectric line of the first and second substrates. A circuit board mounting method characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61033904A JPS62193401A (en) | 1986-02-20 | 1986-02-20 | Mounting system for circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61033904A JPS62193401A (en) | 1986-02-20 | 1986-02-20 | Mounting system for circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62193401A JPS62193401A (en) | 1987-08-25 |
| JPH058883B2 true JPH058883B2 (en) | 1993-02-03 |
Family
ID=12399504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61033904A Granted JPS62193401A (en) | 1986-02-20 | 1986-02-20 | Mounting system for circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62193401A (en) |
-
1986
- 1986-02-20 JP JP61033904A patent/JPS62193401A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62193401A (en) | 1987-08-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |