JPH0588802A - V.24/v.28-v.35 shared interface circuit - Google Patents

V.24/v.28-v.35 shared interface circuit

Info

Publication number
JPH0588802A
JPH0588802A JP3276451A JP27645191A JPH0588802A JP H0588802 A JPH0588802 A JP H0588802A JP 3276451 A JP3276451 A JP 3276451A JP 27645191 A JP27645191 A JP 27645191A JP H0588802 A JPH0588802 A JP H0588802A
Authority
JP
Japan
Prior art keywords
control
driver
receiver
data
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3276451A
Other languages
Japanese (ja)
Other versions
JP2833890B2 (en
Inventor
Kenji Munakata
健二 宗像
Tadaaki Rachi
忠明 良知
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Platforms Ltd
NEC Corp
Original Assignee
NEC Corp
NEC AccessTechnica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC AccessTechnica Ltd filed Critical NEC Corp
Priority to JP3276451A priority Critical patent/JP2833890B2/en
Publication of JPH0588802A publication Critical patent/JPH0588802A/en
Application granted granted Critical
Publication of JP2833890B2 publication Critical patent/JP2833890B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To obtain an interface circuit which can arbitrarily constitute a.24/V.28 driver receiver circuit and a V.35 driver receiver circuit at one printed wiring board. CONSTITUTION:To a clock output terminal 1, a data output terminal 2 and a data input terminal 5, respective clock output drivers 16 and 17 for V.35 and V.24/V.28, data output drivers 18 and 19, data input receivers 22 and 23 are respectively connected in parallel. Respective drivers and receivers are connected to clock output terminals 6 and 11, data output terminals 7 and 12 and data input terminals 10 and 15 provided at a V.35 port, and a V.24/V.28 port respectively. On the other hand, to a control output terminal 3 and a control input terminal 4, a driver 20 for control and a receiver 21 for control shared for the V.35 and for the V.24/V.28 are connected and these are respectively connected to control output terminals 8 and 13 and control input terminals 9 and 14 of respective ports.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はV.24/V.28 ドライバ・
レシーバ回路と、V.35 ドライバ・レシーバ回路とを同
一プリント基板に構成可能なインタフェース回路に関す
る。
BACKGROUND OF THE INVENTION The present invention relates to a V.24 / V.28 driver.
The present invention relates to an interface circuit capable of forming a receiver circuit and a V.35 driver / receiver circuit on the same printed circuit board.

【0002】[0002]

【従来の技術】従来、V.24/V.28 ドライバ・レシーバ
回路は、図3のように、クロック出力端子1、データ出
力端子2、制御出力端子3、制御入力端子4、データ入
力端子5の夫々に専用のクロック出力ドライバ17、デ
ータ出力ドライバ19、制御用ドライバ20、制御用レ
シーバ21、データ入力レシーバ23を接続し、夫々を
V.24/V.28 ポートの各端子11〜15に接続してい
る。又、同様にV.35 ドライバ・レシーバ回路は、図4
のように各端子1〜5に夫々出力ドライバ16、データ
出力ドライバ18、制御用ドライバ20、制御用レシー
バ21、データ入力レシーバ22を接続し、V.35 ポー
トの各端子6〜10に接続を行っている。そして、これ
らV.24/V.28 ドライバ・レシーバ回路とV.35 ドライ
バ・レシーバ回路の各コネクタは、図5及び図6に示す
ように規格が異なっている。
2. Description of the Related Art Conventionally, a V.24 / V.28 driver / receiver circuit has a clock output terminal 1, a data output terminal 2, a control output terminal 3, a control input terminal 4, and a data input terminal 5 as shown in FIG. A dedicated clock output driver 17, data output driver 19, control driver 20, control receiver 21, and data input receiver 23 are connected to each of the above, and each is connected to each terminal 11 to 15 of the V.24 / V.28 port. Connected. Similarly, the V.35 driver / receiver circuit is shown in Fig.4.
Connect the output driver 16, the data output driver 18, the control driver 20, the control receiver 21, and the data input receiver 22 to the terminals 1 to 5, respectively, and connect them to the terminals 6 to 10 of the V.35 port. Is going. The connectors of the V.24 / V.28 driver / receiver circuit and the V.35 driver / receiver circuit have different standards as shown in FIGS.

【0003】[0003]

【発明が解決しようとする課題】このように従来のV.2
4/V.28 ドライバ・レシーバ回路と、V.35 ドライバ・
レシーバ回路は、コネクタの規格が相違するために夫々
を同一のプリント基板に構成することは困難である。そ
のため、これらの回路を構成するためには2枚のプリン
ト基板を夫々設計、製造する必要がある。又、両回路が
別のプリント基板に構成されるため、両回路に共通する
制御用ドライバ20や制御用レシーバ21が存在するの
にも係わらず、これらを兼用することができず、回路構
成を簡略化する上で不利になる。本発明の目的は、1枚
のプリント基板にV.24/V.28 ドライバ・レシーバ回路
とV.35 ドライバ・レシーバ回路を任意に構成すること
を可能にしたインタフェース回路を提供することにあ
る。
As described above, the conventional V.2 is used.
4 / V.28 driver / receiver circuit and V.35 driver /
It is difficult to configure the receiver circuits on the same printed circuit board because the connector standards are different. Therefore, in order to configure these circuits, it is necessary to design and manufacture two printed circuit boards respectively. Further, since both circuits are formed on different printed circuit boards, it is not possible to use them in common even though the control driver 20 and the control receiver 21 that are common to both circuits are present. It becomes a disadvantage in simplification. An object of the present invention is to provide an interface circuit capable of arbitrarily configuring a V.24 / V.28 driver / receiver circuit and a V.35 driver / receiver circuit on one printed circuit board.

【0004】[0004]

【課題を解決するための手段】本発明のインタフェース
回路は、クロック出力端子、データ出力端子、及びデー
タ入力端子に夫々V.35 用及びV.24/V.28 用の各クロ
ック出力ドライバ、データ出力ドライバ、データ入力レ
シーバを並列に接続し、かつ各ドライバとレシーバを夫
々V.35 ポート及びV.24/V.28 ポートに設けたクロッ
ク出力端子、データ出力端子、及びデータ入力端子に接
続し、一方制御出力端子及び制御入力端子にはV.35 用
及びV.24/V.28 用で兼用する制御用ドライバと制御用
レシーバを接続し、かつこれらを各ポートの制御出力端
子及び制御入力端子に夫々接続する。又、1枚のプリン
ト基板に前記兼用インタフェース回路を搭載し、かつこ
のプリント基板にはV.35 用及びV.24/V.28 用の各コ
ネクタを選択的に搭載可能な実装穴を開設する。
The interface circuit of the present invention has a clock output terminal, a data output terminal, and a data input terminal for V.35 and V.24 / V.28 clock output drivers and data, respectively. Connect the output driver and data input receiver in parallel, and connect each driver and receiver to the clock output terminal, data output terminal, and data input terminal provided on the V.35 port and V.24 / V.28 port, respectively. On the other hand, the control output terminal and the control input terminal are connected to the control driver and the control receiver which are also used for V.35 and V.24 / V.28, and these are connected to the control output terminal and control input of each port. Connect to each terminal. In addition, the dual-purpose interface circuit is mounted on one printed circuit board, and a mounting hole for selectively mounting the V.35 connector and the V.24 / V.28 connector is formed on this printed circuit board. ..

【0005】[0005]

【作用】本発明によれば、1枚のプリント基板にV.35
用回路とV.24/V.28 用回路を構成し、かつ両者に共通
な回路を兼用させ、しかもいずれかのコネクタを選択し
て搭載することで、設計、製造の容易化が可能となる。
According to the present invention, V.35 can be provided on one printed circuit board.
Circuit and V.24 / V.28 circuit are configured, and the circuit common to both is shared, and by selecting and mounting either connector, design and manufacturing can be facilitated. ..

【0006】[0006]

【実施例】次に、本発明を図面を参照して説明する。図
1は本発明の一実施例の回路構成を示すブロック図であ
る。クロック出力端子1にはV.35 用クロック出力ドラ
イバ16とV.24/V.28 用クロック出力ドライバ17を
並列に接続し、夫々をV.35 ポートのクロック出力端子
6、V.24/V.28 ポートのクロック出力端子11に接続
している。又、データ出力端子2には、V.35 用データ
出力ドライバ18とV.24/V.28 用データ出力ドライバ
19を並列に接続し、夫々を各ポートのデータ出力端子
7,12に接続している。更に、データ入力端子5に
も、V.35 用データ入力レシーバ22とV.24/V.28 用
データ入力レシーバ23を並列接続し、夫々を各ポート
のデータ入力端子10,15に接続している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention. A clock output driver 16 for V.35 and a clock output driver 17 for V.24 / V.28 are connected in parallel to the clock output terminal 1, and they are respectively connected to the clock output terminal 6 of the V.35 port and V.24 / V. It is connected to the clock output terminal 11 of the .28 port. Further, to the data output terminal 2, a V.35 data output driver 18 and a V.24 / V.28 data output driver 19 are connected in parallel, and each is connected to the data output terminals 7 and 12 of each port. ing. Further, a V.35 data input receiver 22 and a V.24 / V.28 data input receiver 23 are connected in parallel to the data input terminal 5, and each is connected to the data input terminals 10 and 15 of each port. There is.

【0007】一方、制御出力端子3には1つの制御用ド
ライバ20をV.35用及びV.24/V.28 用に兼用して設
けており、その上で各ポートの制御出力端子8,13に
夫々接続している。同様に制御入力端子4には1つの制
御用レシーバ21を両者に兼用して設けており、その上
で各ポートの制御入力端子9,14に夫々接続してい
る。又、この回路を搭載するプリント基板は、図2に示
す規格で構成し、V.35 用及びV.24/V.28 用のいずれ
のコネクタも取着可能に構成している。
On the other hand, the control output terminal 3 is provided with one control driver 20 for both V.35 and V.24 / V.28. 13 are connected to each. Similarly, the control input terminal 4 is provided with one control receiver 21 for both, and is connected to the control input terminals 9 and 14 of the respective ports. The printed circuit board on which this circuit is mounted complies with the standard shown in FIG. 2, and both V.35 and V.24 / V.28 connectors can be attached.

【0008】この構成によれば、データ通信速度に制約
を受けない制御用ドライバ20と制御用レシーバ21を
V.35 とV.24/V.28 の両方に兼用し、データ通信速度
に制約を受けるクロックやデータのドライバ16〜19
とレシーバ22,23をV.35 とV.24/V.28 で区別す
ることで、両回路を1枚のプリント基板に構成した場合
には、制御用ドライバ20と制御用レシーバ21を夫々
1つずつ省略することが可能となる。そして、V.35 用
又はV.24/V.28 用のいずれかのコネクタを搭載した上
で、各端子に対する接続を行えば、1枚のプリント基板
をV.35 用或いはV.24/V.28 用として任意に設定する
ことが可能となる。
According to this configuration, the control driver 20 and the control receiver 21 which are not restricted by the data communication speed are used for both V.35 and V.24 / V.28, and the data communication speed is restricted. Receive clock and data drivers 16-19
By distinguishing V.35 and V.24 / V.28 from V.35 and V.24 / V.28 for receivers, if both circuits are configured on a single printed circuit board, the control driver 20 and the control receiver 21 are respectively It is possible to omit each one. And if either V.35 or V.24 / V.28 connector is mounted and each terminal is connected, one printed circuit board can be used for V.35 or V.24 / V. It can be arbitrarily set for .28.

【0009】[0009]

【発明の効果】以上説明したように本発明は、データ通
信速度に制約を受けない制御用ドライバとレシーバを
V.35 とV.24/V.28 の両方に兼用し、データ通信速度
に制約を受けるクロックやデータのドライバとレシーバ
を両者で区別することで、1枚のプリント基板にV.35
用ドライバ・レシーバ回路と、V.24/V.28 用ドライバ
・レシーバ回路を構成することができ、プリント基板の
設計、製造は1種類で済み、かつ制御用ドライバとレシ
ーバを省略することができる効果がある。
As described above, according to the present invention, both the V.35 and V.24 / V.28 V.35 and V.24 / V.28 control drivers and receivers which are not restricted by the data communication speed are used, and the data communication speed is restricted. By distinguishing the clock and data receiving driver and receiver from each other, V.35 can be printed on one printed circuit board.
Driver / receiver circuit for V.24 / V.28 and driver / receiver circuit for V.24 / V.28 can be configured. Only one type of printed circuit board design and manufacturing is required, and the control driver and receiver can be omitted. effective.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の回路構成を示すブロック図
である。
FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

【図2】本発明の一実施例におけるプリント基板の実装
穴寸法図である。
FIG. 2 is a mounting hole dimension diagram of a printed circuit board according to an embodiment of the present invention.

【図3】従来のV.24/V.28 用回路のブロック図であ
る。
FIG. 3 is a block diagram of a conventional V.24 / V.28 circuit.

【図4】従来のV.35 用回路のブロック図である。FIG. 4 is a block diagram of a conventional V.35 circuit.

【図5】従来のV.24/V.28 用プリント基板の実装穴寸
法図である。
FIG. 5 is a mounting hole dimension diagram of a conventional V.24 / V.28 printed circuit board.

【図6】従来のV.35 用プリント基板の実装穴寸法図で
ある。
FIG. 6 is a mounting hole dimension diagram of a conventional V.35 printed circuit board.

【符号の説明】[Explanation of symbols]

1 クロック出力端子 2 データ出力端子 3 制御出力端子 4 制御入力端子 5 データ入力端子 1 Clock output terminal 2 Data output terminal 3 Control output terminal 4 Control input terminal 5 Data input terminal

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 クロック出力端子、データ出力端子、及
びデータ入力端子に夫々V.35 用及びV.24/V.28 用の
各クロック出力ドライバ、データ出力ドライバ、データ
入力レシーバを並列に接続し、かつ各ドライバとレシー
バを夫々V.35 ポート及びV.24/V.28 ポートに設けた
クロック出力端子、データ出力端子、及びデータ入力端
子に接続し、一方制御出力端子及び制御入力端子には
V.35 用及びV.24/V.28 用で兼用する制御用ドライバ
と制御用レシーバを接続し、かつこれらを各ポートの制
御出力端子及び制御入力端子に夫々接続したことを特徴
とするV.24/V.28 ・V.35 兼用インタフェース回路。
1. A clock output terminal, a data output terminal, and a data input terminal are connected in parallel with a clock output driver, a data output driver, and a data input receiver for V.35 and V.24 / V.28, respectively. Also, connect each driver and receiver to the clock output terminal, data output terminal, and data input terminal provided on the V.35 port and V.24 / V.28 port, respectively, while connecting the control output terminal and control input terminal to A V.35 and V.24 / V.28 dual-purpose control driver and control receiver are connected, and these are connected to the control output terminal and control input terminal of each port, respectively. .24 / V.28 ・ V.35 dual-purpose interface circuit.
【請求項2】 1枚のプリント基板に前記兼用インタフ
ェース回路を搭載し、かつこのプリント基板にはV.35
用及びV.24/V.28 用の各コネクタを選択的に搭載可能
な実装穴を開設してなる請求項1のV.24/V.28 ・V.3
5 兼用インタフェース回路。
2. The dual-purpose interface circuit is mounted on one printed circuit board, and this printed circuit board is V.35.
And V.24 / V.28 / V.3 according to claim 1, wherein mounting holes for selectively mounting connectors for V.24 / V.28 and V.24 / V.28 are provided.
5 Dual-purpose interface circuit.
JP3276451A 1991-09-30 1991-09-30 V. 24 / V. 28 · V. 35 Dual-purpose interface circuit Expired - Fee Related JP2833890B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3276451A JP2833890B2 (en) 1991-09-30 1991-09-30 V. 24 / V. 28 · V. 35 Dual-purpose interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3276451A JP2833890B2 (en) 1991-09-30 1991-09-30 V. 24 / V. 28 · V. 35 Dual-purpose interface circuit

Publications (2)

Publication Number Publication Date
JPH0588802A true JPH0588802A (en) 1993-04-09
JP2833890B2 JP2833890B2 (en) 1998-12-09

Family

ID=17569620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3276451A Expired - Fee Related JP2833890B2 (en) 1991-09-30 1991-09-30 V. 24 / V. 28 · V. 35 Dual-purpose interface circuit

Country Status (1)

Country Link
JP (1) JP2833890B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08255038A (en) * 1995-03-17 1996-10-01 Nec Corp V24/v28 and v35 shared interface system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03204714A (en) * 1990-01-08 1991-09-06 Hitachi Ltd Connector for connecting peripheral equipment of information processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03204714A (en) * 1990-01-08 1991-09-06 Hitachi Ltd Connector for connecting peripheral equipment of information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08255038A (en) * 1995-03-17 1996-10-01 Nec Corp V24/v28 and v35 shared interface system

Also Published As

Publication number Publication date
JP2833890B2 (en) 1998-12-09

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