JPH0585999B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory suitable for high integration.

[Background of the invention]

As is well known, semiconductor memory has flip
Flop-type memory cells are often used.

FIG. 1 is a diagram for explaining the principle of reading and writing information to and from a flip-flop type memory cell C, which has been widely used in the past.
The memory cell C stores information "0" or "1" depending on which of the transistors Q1 and Q2 is on, that is, which base potential of Q1 or Q2 is higher.

First, a method for reading out information stored in a memory cell C selected by selection signals X and Y will be described. Assume that the transistor Q1 of the memory cell C is on and the transistor Q2 is off. At this time, the base potential V _B1 of transistor Q1 is the base potential V _B2 of transistor Q2.
The potential is higher than that of the Now, in order to read the information of this memory cell, the base potential V _r1 of the read and write transistors Q3 and Q4,
Both V _r2 may be set to an intermediate level (read reference potential) between potentials V _B1 and V _B2 . At this time, the current from the current source I _R1 flows from transistor Q1 to bit line B because V _B1 is at a higher potential than V _r1 , while the current from the current source I _R2 flows because V _r2 is higher than V _B2 . Since it is at a high potential, it flows from transistor Q4 rather than from the bit line. Therefore, resistors R3 and R4
The read current flows only through R4, and the potential V _S1
becomes a higher potential than V _S2 . After that, this potential V _S1 ,
If the potential difference of V _S2 is amplified by the sense amplifier SA, an output signal V _p can be obtained corresponding to the information of the memory cell.

Next, a method for writing information into memory cell C will be explained. To write, the potential of V _r1 or V _r2 is changed to V _B1 and V _B2 depending on the information to be written.
It is sufficient to set the potential to be lower than the lower potential (write reference potential). For example, to turn on transistor Q2 and turn off transistor Q1, the potential is
It is sufficient to set V _r2 as the write reference potential. At this time, the potential V _B2 is higher than V _r2 , so the current source
The current from I _R2 flows into transistor Q2 and Q2
turns on. At this time, this current flows through the shotgun barrier diode SBD2 and the resistor R2, and the base potential of the transistor Q1 becomes a low potential, causing the Q
1 is off.

FIG. 2 shows a conventional example of a method of supplying a read reference potential and a write reference potential. here,
The read or write reference potentials (V _r1 and V _r2 ) generated by the reference potential generation circuit CK are applied to each bit line (B1 to B1) by the reference potential supply lines r1 and r2.
It is applied to the bases of read and write transistors Q3 and Q4 connected to BN, 1~). In addition, in this circuit,
This is shown in Publication No. 27552, and due to the concentrated current ΔI _ST and the wiring resistance of the word line (W ₁ to W _M ),
To compensate for the word line potential drop, the current I _r1
and I _r2 are passed through the reference potential supply line to cause the same potential drop as that of the word line, thereby making the relative relationship between the word line potential and the reference potential constant. In this technology, a reference potential generation circuit is provided on one side of the word driver circuit 10, and current sources I _r1 and I _r2 are provided on the other side, and by running the word line and the reference potential supply line in parallel, Corrects potential drop.

By the way, in recent years, users or systems have been trying to increase the number of memory outputs by 2 or more (2, 4, 8, or
16) There is a strong demand for it to be done. In order to meet this demand, the memory cell array must be divided into multiple parts.
It is necessary to have a multiple mat configuration. In this case, one more memory array shown in FIG. 2 is provided, and the X selection signal and the Y selection signal are applied to each array in parallel, so that two cells can be accessed at the same time. For example, when a memory cell array is divided into two in order to configure the cell array with two mats, it is necessary to set write reference potentials independently in order to write independent information to the cells in the two mats.

In other words, information “0” is stored in the cell of one of the mats.
In order to write information "1" into the cell of the other mat, the two reference potentials V _r1 of one mat,
Of V _r2 , V _r1 must be set to a low potential, and of the two reference potentials V _r1 and V _r2 of the other mat, V _r2 must be set to a low potential.

Therefore, the reference potential generation circuit CK and current source
Two each of I _r1 and I _r2 are required.

However, in this case, although the word line is shared by the two mats, two sets of reference potential generation circuits CK must be provided.
In order to have the same voltage drop between the reference potential supply line and the word line, two reference potential generation circuits must be placed on the word line driver circuit side.
In this case, the reference potential supply line to the mat remote from the word line driver circuit passes through the mat near the word line driver circuit, resulting in wasted chip area.

[Purpose of the invention]

An object of the present invention is to compensate for the potential drop of the word line even when the word line is multi-divided in this way,
It is an object of the present invention to provide circuit means for correctly reading or writing a memory.

[Summary of the invention]

To achieve the above object, the present invention changes the potential of the reference potential generating circuit CK for each mat in correspondence with the word line in order to compensate for the potential drop of the word line. Therefore, no matter how the word line is divided, it is possible to compensate for the potential drop in the word line.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 is an embodiment of the present invention, and shows an example in which the present invention is applied to a memory having a two-mat configuration in which a word line is divided into two.

As _shown in _FIG .
Since it is difficult to place between 0 and 0 due to lack of space, the reference potential generation circuit of MAT 1 is
CK and current sources I _r1 and I _r2 are arranged on the memory cell C ₁₁ side, and CK', I _r1 ', and I _r2 ' of the mat 2 are arranged on the cell C _1P side.

In this embodiment, word lines (W ₁ to W _M ) are arranged in common to mats 20 and 30, and Y
A selection signal is also commonly input to mats 20 and 30.

Therefore, when the X ₁ selection signal and the Y ₁ selection signal of the word line W ₁ are input, the mat 20 selects the cell C ₁₁
However, from the mat 30, C _{1 N+1} is selected at the same time.

Components that are the same as those in FIG. 2 are designated by the same reference numerals or the same reference numerals with a dash (') added.

Note that the current sources I _r1 , I _r2 , I _r1 ′, and I _r2 ′ are connected between the base and emitter of the output emitter followers in the circuits CK and CK′ (described in detail in FIG. 4 ₎ .
_T14 ) should be a small value that can maintain the voltage.
No potential drop occurs in the supply lines r1, r2, r1', r2'.

FIG. 3b shows, as an example, how to set the reference potentials V _r1 , V _r2 and V _r1 ', V _r2 ' at the time of reading. Now, when word line W ₁ is selected and its potential V _W1 drops as shown in the figure, the potential in the selected cell also drops, and as an example, the load switching type cell in Figure 1 case transistor Q
The base potentials V _B1 and V _B2 of 1 and Q2 are as shown in FIG. 3b.

In this setting method, the reference potential generation circuits CK and CK' are adjusted to a potential that is the average of the base potentials V _B1 and V _B2 of the cells at the center of each mat. on the other hand,
As mentioned above, reading cell information is performed using these potentials V _B1 , V _B2 and reference potentials V _r1 , V _r2 , V _r1 ′,
This is done using a potential difference of V _r2 ′. Therefore, _{V r1 ,}
When V _r2 is set to a high potential and V _r1 ′ and V _r2 ′ are set to a low potential, the above potential difference can be increased by ΔV, and reading can be performed more accurately.

Regarding writing, as mentioned earlier,
Base potentials V _B1 , V _B2 and reference potentials V _r1 , V _r2 , V _r1 ′,
It will be clear to those skilled in the art that what is carried out using the potential difference of V _r2 is exactly the same as when reading, and the above discussion holds true as is.

In Figure 3b, the potentials on the vertical axis are V _B1 and V _B2
The potential difference, the distance on the horizontal axis, and the total length of the word line are each standardized.

FIG. 4 shows the reference potential generation circuits CK and CK'. The read or write reference potentials V _r1 and V _r2 generated by the reference potential generation circuit CK are
To make the potential higher than V _r1 ′ and V _r2 ′, the resistor R may be made smaller than the resistor R′ or the current I may be made smaller than the current I′.

During read operation, WE is at low level, so the output of inverter A causes the transistor to
T ₁₅ turns on. Therefore, the transistor T ₁₁ ,
T ₁₂ turns off and the bases of transistors T ₁₃ and T ₁₄
The potential at one end N of the resistor R appears in N ₁ and N ₂ .

Transistors T ₁₃ and T ₁₄ are driven by this voltage.

On the other hand, during a write operation, WE becomes High level, and the output of inverter A causes transistor _T15
turns off. In this case, one of the transistors T ₁₁ and T ₁₂ is turned on by the write data DI, and different voltages are generated at N ₁ and N ₂ .

In addition to this, various other ways can be considered for the reference voltage generation circuit, such as making an appropriate difference in the power supply voltage of the reference voltage generation circuit (in Figure 4, CK and CK' are set to the same ground potential). However, these circuits can be easily constructed by those skilled in the art in accordance with the spirit of the present invention.

FIG. 5 is another embodiment of the present invention,
Divide the word line into four and connect four mats 30', 2
An example in which the present invention is applied to a memory in which a word driver circuit for driving word lines is arranged between mats (2) and (3) is shown. In this case, the reference potential generation circuits CK2 and CK3 of the mats 20 and 20' are connected to the word driver circuit side, and the reference potential generation circuits CK2 and CK3 of the mats 30 and 30'
1, CK4 is provided on the opposite side.

Components that are the same as those in FIG. 3 are given the same reference numerals.

Since the concentrated currents ΔI _ST12 and ΔI _ST34 flow as shown in FIG. 5a, the potential V _W of the word line drops as shown in FIG. 5b. Therefore, at the time of reading, the reference potentials V _r11 , V _r12 , V _r21 , V _r22 , V _r31 ,
As shown in the figure, reference potentials may be set for the levels of V _r32 , V _r41 , and V _r42 in accordance with the average values of V _B1 and V _B2 of the central cells of each mat.

So far, we have shown an example in which the reference potentials V _r1 and V _r2 generated by the reference potential generation circuit CK are supplied from the end of the reference potential supply line, but according to the present invention, the reference potential Generation circuit CK and current source
I _r1 and I _r2 may be placed anywhere, and the reference potentials V _r1 and
V _r2 may be supplied from any point on the supply line.

FIG. 6 shows yet another embodiment of the present invention, and shows an example in which the present invention is applied to a memory in which the word line is divided into four parts, similar to FIG. 5. The difference between Figures 4 and 5 is that in Figure 5, the reference potential is
V _r11 , V _r12 . . . are supplied from the middle of the supply lines r1, r2 . . . and are provided above each mat. Components that are the same as those in FIG. 3 are designated by the same reference numerals. The method of setting the level of the reference potential during reading may be exactly the same as that shown in FIG. 4b.

Now, the effects of the present invention have been shown above with reference to examples, but due to space constraints,
If the invention disclosed in Japanese Patent Publication No. 27552 can be used, it can be used in combination with the present invention to further improve compensation for word line voltage drops.

FIG. 7 is a diagram showing an embodiment thereof, and in FIG. They are placed on the opposite side, and this current causes a potential drop in the reference potential supply lines r11, r12, etc. In this case as well, a reference potential generation circuit and a current source are placed close to each mat. Components that are the same as those in FIG. 3 are designated by the same reference numerals. Furthermore, according to the invention, CK1 and CK
By making the reference potential generated at CK2 and CK3 lower than the reference potentials generated at CK2 and CK3, and by making the slopes of the potentials connect, the potential relationship shown in Figure 5b can be further changed as shown in Figure 7b. Improved.

So far, we have shown examples in which the present invention is applied to a memory in which the word line is divided into two or four parts.
It goes without saying that the present invention can generally be applied to memories in which word lines are multi-divided. Furthermore, it goes without saying that the present invention is applicable even when the read transistors and write transistors are different.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to compensate for the potential drop in the word line even in a memory in which the word line is multi-divided, and it is possible to read and write to the memory correctly. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a method of reading and writing information in a memory cell, FIG. 2 is a diagram showing a conventional method of supplying a reference potential, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing a reference potential generation circuit used in this embodiment, and FIGS. 5, 6, and 7 are diagrams showing other embodiments of the present invention. W...Word line, B...Bit line, C...Memory cell, SA...Sense amplifier, _Vr ...Reference potential, r...Reference potential supply line, CK...Reference potential generation circuit.

Claims (1)

[Scope of Claims] 1. A plurality of word lines, a plurality of bit lines, a plurality of memory cells respectively arranged at the intersections of the plurality of word lines and the plurality of bit lines, and a plurality of memory cells arranged respectively at the intersections of the plurality of word lines and the plurality of bit lines. In a semiconductor memory comprising a plurality of read/write transistors connected to each other for reading or writing signals to the memory cell, a plurality of reference potential generation circuits provide a read reference potential or a write reference potential to each of the plurality of read/write transistors. The reference potential generation circuit is formed such that the value of the reference potential generated by each of the plurality of reference potential generation circuits is composed of at least two or more different values. semiconductor memory. 2. The semiconductor memory is formed by arranging a plurality of mats each including a plurality of the memory cells, and each mat is equipped with at least one of the reference potential generation circuits. 1. The semiconductor memory according to 1. 3. The semiconductor according to claim 2, wherein the value of the reference potential generated by the reference potential generation circuit is set to a value corresponding to a word line potential supplied to the mat to which the reference potential is applied. memory. 4. A semiconductor memory according to claim 1, wherein said read/write transistors are bipolar transistors, each having an emitter connected to said bit line.