JPH0585043B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device having an arithmetic processing section that performs control processing of the entire system operation and an arithmetic processing section that performs display control. The present invention relates to a circuit configuration for activating a display-side arithmetic processing unit used in a processor, a personal computer, or the like.

[Conventional technology]

Various systems have been developed in the past with multiple processing units in one system, and examples of their configurations are also described in the iAPX86 Family User's Manual p4 to p11 (Intel Japan Co., Ltd.). .

[Problem that the invention seeks to solve]

However, most of these systems with multiple arithmetic processing units are used in expensive equipment such as EWS (engineering work stations), and are used in models that require high performance but are subject to intense price competition, such as word processors. Not much consideration was given to system applications.

Two processing units (CPU) in one system
and storage (i.e., a CPU that controls the operation of the entire system and a CPU that performs display processing)
In the circuit configuration of a word processor (such as a word processor with a CPU), each CPU generally requires a storage section to store a shareable program, and one program for each CPU to boot after a system reset. Become.

In addition, the startup program on the display CPU side,
Although it is possible to eliminate the storage section for the startup program by providing it in a storage section that can be shared by the two CPUs, this method uses a part of the storage section that can be shared. , there are restrictions on shared programs.

FIG. 4 is an overall block circuit diagram showing a specific example of a word processor, which is a conventional information processing device.
That is, FIG. 5 is a block circuit diagram of a word processor having two CPUs, and FIG. 5 is a memory map of the block circuit shown in FIG.

In FIG. 4, 101 is a host CPU that controls the entire system, and the host CPU 10
For example, Intel's 8086, 8088, etc. are suitable as No. 1. 102 is non-volatile memory (ROM)
The program loader A 103 stores programs to be executed when the power is turned on, and the program loader A 103 stores programs for controlling the entire system and document editing processing. It also has a memory (RAM) that can be read and written at any time and temporarily stores created documents. ); 105 is a keyboard for inputting characters and numbers; 104 is a keyboard control unit that sends input signals from the keyboard 105 to the host CPU 101; 115 is a flexible disk drive ( FDD), 114 is a flexible disk controller (FDC) that controls writing and reading of data to and from the FDD 115 according to commands from the host CPU 101, 108 is a display CPU that controls screen display, and 110 is for screen display. 113 is a CRT monitor, 11 is a character generator (CG) that stores character fonts for
Reference numeral 1 denotes a graphics memory 1 for writing text and graphic data to be displayed on the CRT monitor 113;
This is a display control unit that reads data from 11 and performs parallel-to-serial conversion.

107 is the host CPU 101 and display CPU
The shared memory 107 is a shared memory that can be accessed from any of the host CPU 108.
01 to display CPU108 or for display
It is used for exchanging data from the CPU 108 to the host CPU 101, or as a system program area for the display CPU 108. 106 is a competition circuit for adjusting accesses from the host CPU 101 and the display CPU 108 to the shared memory 107.

In the above configuration, when the power is turned on, the host CPU 101 first loads the program loader A.
According to the program 102, the program stored in the flexible disk of the FDD 115, that is, the program for operating as a word processor, is transferred to the system memory 103.

The host CPU 101 also controls the CRT monitor 11.
A program that operates the display CPU 108 for the purpose of displaying the screen in 3.
Furthermore, the initial program for starting the display CPU 108 is transferred to the shared memory 107, and each of the programs starts operating as a word processor.

Thus, the display CPU 108 starts its operation by the host CPU 101 sending a reset signal to the display CPU 108 and by the display CPU 108 reading the initial program stored in the shared memory 107.

When performing document input processing, it is performed according to a system program in system memory 103. That is, the shared memory 107 is stored on the display CPU 108 side by the input processing program.
When you send commands and data through
The CPU 108 forms a display screen on the CRT monitor 113 via the display control section 112 and graphics memory 111. Further, commands for processing associated with data input are performed based on data and function instructions input through the keyboard 105.
Repeat data entry until instructed to finish.

The circuit configuration and operation of a conventional word processor are as described above.
The display CPU startup program indicated by is stored in a shared memory indicated by reference numeral 107 in the figure, or in a nonvolatile memory.

However, for display purposes indicated by reference numeral 108 in FIG.
In the case of a method in which the CPU startup program is stored in the shared memory indicated by reference numeral 107 in the same figure, the fifth
As shown in the figure, since the shared memory area is also used as system memory on the display side, its address must be allocated starting from address 00000H, and the program loader section, which is the initial program for starting the display CPU 108, is ,
Therefore, as shown in the memory map in the same figure (Figure 5), the same area of program loader B1 and program loader B2 can be read by the display CPU 108 using different addresses assigned to each area. It must have a suitable structure. That is, when the above method is adopted, for example, on the display side, memory that is accessed only by the display CPU 108 is added to the address immediately following the shared memory section that can be accessed from both the host CPU 101 and the display CPU 108. In the case where the shared memory 107 must be used contiguously with the shared memory 107, in the above method, the presence of the program loader B1 results in a discontinuous state.

On the other hand, the display CPU shown with reference numeral 108 in FIG.
In the case of a method of storing the startup program in non-volatile memory, the capacity of the initial program for startup on the display CPU 108 side is only a few bytes, so using non-volatile memory is This is not a good idea from a cost standpoint.

The purpose of the present invention is to provide two CPUs: one that controls the entire system operation, and one that controls the display.
In an information processing device having two CPUs, the memory for the startup program used by the display CPU is simplified, and the information processing device does not have shared memory usage restrictions when creating programs for the entire system. It is about providing.

[Means for solving problems]

The purpose is to control the first CPU, which controls the entire system operation, and the second CPU, which controls the display.
a CPU, and the first CPU and the second CPU.
It has a memory that is shared with the CPU and stores the processing contents of the second CPU, and the first CPU is connected to the second CPU.
In an information processing device that writes processing contents after application of a start signal to a CPU, the first CPU
This is achieved by configuring so that the processing content after application of the activation signal given to the second CPU is written into a register provided within the address area of the second CPU.

[Effect]

According to the present invention having the above configuration,
The memory for the boot program after system reset on the CPU side that performs display processing can be simplified, and shared memory addresses can be used more effectively.

〔Example〕

Hereinafter, the present invention will be explained based on one embodiment of FIGS. 1 to 3. FIG. 1 is a block circuit diagram of a word processor to which the present invention is applied, and FIG. 3 is a memory map of the block circuit shown in FIG. 1. In FIG. 1, the same reference numerals as in the conventional word processor shown in FIG. A program loader B for storing a startup program for the display CPU 108 is shown, and in the present invention, the program loader B 109
is made up of registers.

Here, the details of the program loader B109 are as follows.
The explanation will be made based on FIG. 2 while referring to FIG. 1.

In FIG. 2, 201 and 202 are registers A and B, which are composed of 4-bit multiple word registers having separate input terminals for writing and output terminals for reading.
1. The data bus of the host CPU 101 is connected to the write terminal side of the register B 202, and according to the decoding result of the address given from the host CPU 101 and the write signal to the peripheral control unit,
Data is written to register A201 and register B202, respectively. Also, register A20
1. On the output terminal side of register B202, there is a display
The data bus of CPU108 is connected and used for display.
In response to a memory read signal from the CPU 108, data is read from register A201 and register B202, respectively. In addition, register A20
1. Register B202 is used to read data to the host CPU 101 side, and also to the CPU for display.
No data is written from the 108 side.

As can be seen from the memory map of the display CPU (108 in FIG. 1) in FIG. 3, which is a memory map of the block circuit shown in FIG. The program loader section that stores the program can be configured to be allocated to the highest address of the memory map, similar to when non-volatile memory is used, so the shared memory section and the system memory section of the display CPU 108 can be used consecutively. be able to.

〔Effect of the invention〕

The present invention is as described above, and as is clear from the description of the illustrated embodiments, according to the present invention, display
As the initial program section of CPU108,
Unlike in the past, it is not necessary to use a part of the shared memory 107 and there is no need to use non-volatile memory, which reduces circuit costs and reduces the address of the shared memory 107 on the display CPU 108 side. can be used effectively.

In addition, the program loader B10 shown in FIG.
Regarding the detailed circuit section of 9, for example, the display CPU
When a part of the circuit on the 108 side is made into a custom LSI, including it in the custom LSI is very effective in terms of both reducing the number of parts when mounting parts on the board and further reducing costs.

[Brief explanation of the drawing]

1 to 3 show an embodiment of an information processing apparatus according to the present invention, FIG. 1 is a block circuit diagram of a word processor to which the present invention is applied, and FIG. 3 is a memory map of the block circuit shown in FIG. 1, and FIG. 4 is an overall block circuit diagram showing a specific example of a word processor, which is a conventional information processing device. FIG. 5 is a memory map of the block circuit shown in FIG. 101...Host CPU, 107...Shared memory,
108...Display CPU, 109...Program loader B, 201...Register A, 202...Register B.

Claims (1)

[Claims] 1 It has a first arithmetic processing section that controls the entire system operation and a second arithmetic processing section that performs display control, and is shared by the first arithmetic processing section and the second arithmetic processing section. , an information processing device having a storage section for storing processing contents of the second arithmetic processing section, wherein the first arithmetic processing section writes the processing contents after application of the activation signal to the second arithmetic processing section; ,
The content of processing after application of the activation signal that the first arithmetic processing unit gives to the second arithmetic processing unit is determined by the second arithmetic processing unit.
An information processing device characterized in that the information processing device is configured to write to a register provided within an address area of an arithmetic processing unit.