JPH0583931B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for loading a microprogram, and more particularly to a method for loading a microprogram for controlling an input/output control device.

(Prior Art) FIG. 2 shows a configuration block diagram of a device system related to microprogram loading in a conventional input/output control device. In this diagram,
1 is a host device such as a central processing unit, 2 is a host device 1
3 is a flexible disk drive (hereinafter referred to as FDD), 4 is an FDD that controls the FDD.
A control device, 5 is an input/output device, 6 is an input/output control device main body that controls the input/output device 5, 7 is a microprocessor circuit that controls the input/output control device main body 6, and 8 is a program for storing a microprogram. Replaceable memory (RAM), 9 is host device 1
and a common bus connecting the FDD control device 4 and the input/output control device main body 6.

Next, a conventional microprogram loading method will be explained using FIG. Second
In the system having the configuration shown in the figure, the microprocessor circuit 7 of the input/output control device main body 6 executes a control procedure (microprogram) for the input/output control main body 6 for the flexibility, versatility, and ease of modification of the system. A method is adopted in which the information is stored in the FDD 3 in advance and is loaded and used as necessary. That is, the microprocessor circuit 7 is
When starting up the system, this microprogram is read from the FDD 3 using the FDD control device 4 and temporarily stored in the main storage section 2 of the host device 1.
Then, this microprogram is read out from the main memory section 2 using a microprogram loading program (MPL program) stored in advance in the read-only memory (ROM) 7a of the microprocessor circuit 7, and stored in the microprogram RAM 8. Due to this, loading was performed.

(Problems to be Solved by the Invention) However, in the conventional device having the above-described configuration, when it includes a plurality of input/output control device bodies, the control of the input/output control device bodies depends on the type of input/output control device body used. It was necessary to properly prepare a medium such as an FDD in which the microprogram for the system was stored at the initial stage, which caused problems in terms of preventing erroneous operations and ensuring maintainability and reliability.

The present invention eliminates the problem that the microprogram described above must be properly prepared in advance on a medium such as an FDD at the initial stage, and improves operability.
The purpose is to provide a microprogram loading method with excellent reliability and maintainability.

(Means for Solving the Problems) The present invention provides one or more input/output control device main bodies having a ROM that pre-holds its own control microprogram and a reading circuit for this microprogram, and A microprogram for an input/output control device, which has a RAM for storing a microprogram and is connected to a channel control device that controls the input/output control device based on the control microprogram based on instructions from a central processing unit. In this loading method, the control microprogram is initially loaded into the ROM of the input/output control device.
This microprogram loading method is characterized in that the steps of reading the data from the input/output control device via the readout circuit and then storing it in the RAM in the channel control device are performed sequentially for all input/output control device main bodies.

(Function) The input/output control device used in the present invention consists of an input/output control device main body and a channel control device.

The input/output control device main body has its own control microprogram stored in its ROM in advance.

Then, the channel control device reads out and loads the control microprogram for the main body of the input/output control device into its own RAM according to instructions from the CPU.

Therefore, in the method of the present invention, erroneous loading operations do not occur.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a drawing showing an input/output control device according to the method of the present invention, and is a block diagram of a device system in which three input/output control device bodies are connected to one channel control device as an example. Note that the input/output control device bodies may be of different types or may be the same. Further, the number of input/output control device bodies connected to one channel control device is not particularly limited.

In FIG. 3, 11 is a channel control device;
12a, 12b, 12c are input/output devices; 13a,
13b and 13c are input/output devices 12a and 12, respectively.
b, 12c, an input/output control device main body connected to the channel control device 11; 14 is the channel control device 11;
This is a microprocessor circuit mounted on the microprocessor circuit for controlling the channel control device 11 and input/output control device main bodies 13a, 13b, and 13c.
15 is a read-only memory (ROM) in which a microprogram for storing a microprocessor for operating the microprocessor circuit 14 is stored; 17a, 17b, and 17c are input/output control device bodies 13a, 13b, respectively; ROM on 13c
The contents of 16a, 16b, 16c are stored in the ROM1.
This is a rewritable memory (RAM) for initially storing an initial microprogram loading program (IMLP) that is pre-stored in 5. 18a, 18b, and 18c are read from ROM by instructions from the microprocessor circuit 14.
A peripheral circuit (initial microprogram loader circuit) for reading the contents of 16a, 16b, and 16c and storing them in the register 14a of the microprocessor circuit 14; The target input/output control device 13x (x=a, b, or c) controlled by 14 and the RAM 17x that stores the control microprogram
Register for uniquely selecting (x = a, b or c) (port select register; PSR)
It is. In addition, there are three input/output control device main bodies 13.
A, 13b, and 13c are given numbers to distinguish them for the sake of explanation, and these are hereinafter referred to as port numbers.

FIG. 1 shows a microprocessor circuit 14,
ROM15, and RAM17a, 17b, 17c,
This is a detailed block diagram of the ROM 16a in which the PSR 19, the IMPL circuit 18a, and the control microprogram for the input/output control device main body are stored. , 13c are sequentially selected. In this figure, 20 is a control memory (CM) bus, 21 is a CM address register (CMAR) for latching address information output to the CM bus 20, and 22 is a connection between the microprocessor circuit 14 and peripheral circuits. 23 is an address register (ADR) for latching the IO address information output to the ID bus, 24 is an IO data buffer (IDBF), 2
5 is a port control (PCTL) circuit for controlling hardware interface signals between the microprocessor circuit 14 and the input/output control device main body 13a; 26 is a channel control device 11;
A port data bus 27 is a port address bus for exchanging data between the input/output control device main body 13a and the input/output control device main body 13a.

The microprocessor circuit 14 connects to the CM bus 20
The address for addressing the ROM 15 is output to the CM address register 11 and latched to the CM address register 11.
The ROM 15 outputs CM data corresponding to the address latched in the CM address register 11 and inputs it to the microprocessor circuit 14. In this way, the microprocessor circuit 14 loads the ROM1
It operates according to the microprogram stored in 5.

Next, the microprogram loading method of the present invention will be explained using the detailed block diagram of FIG. 1 and the flowchart of FIG. 4.

The ROM 15 stores an initial microprogram loading program as shown in FIG. 4, and the microprogram loading is executed according to this program. In the following description, R0 to R5 indicate internal registers of the microprocessor circuit.

First of all, the microprocessor circuit 14 is
After initializing the port selection number (S1),
Output one port number to ID bus 22 and PSR
19 (S2). On the other hand, the microprocessor circuit 14 initializes the RAM address of internal register R2 (S3), and initializes the RAM address of internal register R3 (S3).
Initialization of addresses (S4), initialization of control data for the input/output control device main body in internal register R4 (S5), and initialization of byte positions for reading the same data one byte at a time (S6) are performed.

The PSR 19 that has latched the port number selects the only input/output control device main body (for example, 13a) that corresponds to the latched data, for example.
A selection signal is output to the RAM 17a and the PCTL circuit 25.

Next, the microprocessor circuit 14 uses a ROM 16 that stores a microprogram for controlling the input/output control device main body 13a on the ID bus 22.
Address information for addressing a is latched from internal register R3 to ADR 23 (S7). The ADR 23 outputs the latched address information to the address bus 27 of the port interface.

Then, the microprocessor circuit 14 reads 1 byte of the contents of the ROM 16a as follows (S8). First, a data request signal is output to the PCTL circuit 25. In response to the input data request signal, the PCTL circuit 25 transmits it to the channel control device 1.
1 and the input/output control device main body 13a into a signal that conforms to the interface (port interface) defined between the input/output control device main body 13a and the input/output control device main body 13a.
The signal is output to the IMPL circuit 18a. IMPL circuit 18
A returns a response signal to the requested command and turns on the output control signal of the ROM 16a. The ROM 16a transfers 1 byte of data corresponding to a predetermined address to the port data bus 2.
6, and sends the data to the microprocessor circuit 14 via the IDBF 24 and ID bus 22. At this time, the microprocessor circuit 14 performs data alignment and sets the data in the internal register R4 (S9). When the instruction word length of the microprocessor circuit 14 is 64 bits (8 bytes), the microprocessor circuit 14 updates the address information output to the ID bus 22 one by one (S10) and updates the byte position. (S11), and the data is read according to the above procedure eight times to complete the reading (S12). Then, the read 8-byte data is arranged so that it becomes a 64-bit wide instruction word.

Furthermore, the microprocessor circuit 14
Address information for addressing the RAM 17a is output to the CM bus 20 and latched into the CM address register 21. Then, the aligned 64-bit instruction word data is output to the CM bus 20, and the RAM 1
The data is stored at the address addressed after 7a (S13).

Repeat the above steps with the address of ROM16a and
By repeating a predetermined number of times while changing the address of RAM17a, ROM1
All contents of the microprogram stored in the microprogram 6a are stored in the RAM 17a (S14, 15).

Then update the port number if necessary (S16)
The control microprograms for other input/output control device bodies 13b and 13c are also stored in the RAM 17.
b, 17c, etc. (S17).

(Effects of the Invention) As described above in detail, according to the present invention,
By simply connecting the input/output control device main body corresponding to various input/output devices to the channel control device, the own control microprogram of the input/output control device main body is loaded into the RAM in the channel control device. A microprogram corresponding to the input/output control device is stored, such as
It is no longer necessary to properly prepare media such as FDD in advance, and it can be expected to improve device reliability, maintainability, operational methods, and eliminate operational errors.

[Brief explanation of the drawing]

FIG. 1 is a detailed block diagram of an input/output control device according to the method of the present invention, FIG. 2 is a block diagram of the configuration of a conventional input/output control device, and FIG. 3 is a block diagram of the configuration of an input/output control device according to the method of the present invention. , FIG. 4 is a flowchart of the initial microprogram loading program (initialization program). 11...Channel control device, 13a, 13
b, 13c...Input/output control device main body, 14...Microprocessor circuit, 15, 16a, 16b,
16c...ROM, 17a, 17b, 17c...
RAM, 18a, 18b, 18c...IMPL circuit (readout circuit).

Claims (1)

[Scope of Claims] 1. One or more input/output control device bodies having a ROM that pre-holds its own control microprogram and a reading circuit for this microprogram, and storing the control microprogram. A method for loading a microprogram of an input/output control device, comprising: a channel control device having a RAM for controlling the input/output control device and controlling the input/output control device based on the control microprogram according to instructions from a central processing unit; For all input/output control device main bodies, the control microprogram is initially read from the ROM of the input/output control device main body via the readout circuit, and then stored in the RAM in the channel control device. A microprogram loading method characterized by sequential loading.