JPH0583853A - Power supply equipment and control method therefor - Google Patents

Abstract

PURPOSE:To enhance reliability without enlarging a power supply section by recognizing the operating state of other power supply control section at the time of resetting and matching the operating state so that the designating state for the power supply section will be identical. CONSTITUTION:Each power supply control section 11 normally writes the operating state of its power supply control section 11 into a counterpart notification register 16 thus notifying the operating condition to other power supply control sections 11. At the time of resetting, operating state of other power supply control section 11 is read out from the notification register 16 and recognized. The operating states are then matched so that the designating states for the power supply section 13 will be identical at each power supply control section 11, and any one of the power supply control sections 11 delivers an operation command to the power supply section 13 through an OR circuit device 14. Consequently, the power supply section can feed power through a minimum necessary constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply unit for a computer system and a power supply control method.

[0002]

2. Description of the Related Art As shown in FIG. 14, power supply units 1a and 1b and a power supply control unit 2 are used to improve the reliability of a computer system.
It was realized by duplicating both a and 2b.
Here, 3 is a control panel for turning the power on / off
The switch 3a is provided. Reference numeral 4 is a power supply, and the power supplies 1a and 1b are built in dually having the same standard and performance. Reference numeral 5 denotes a diode, which connects the power sources 4 doubled in each of the power source units 1a and 1b at the output side of the diode 5 by the diode OR. In such a configuration, it is necessary to double the power sources 4 in each of the power source units 1a and 1b, and the power source units 1a and 1b become large.

[0003]

In the above-mentioned conventional technique, in the high reliability power supply device in the computer system,
Since it is necessary to have dual power supplies 4 built in the power supply units 1a and 1b, there is a problem that the entire power supply device becomes large.

The present invention is intended to solve the above-mentioned problems in the prior art, and an object thereof is to provide a power supply device and a power supply control method for increasing the reliability without increasing the size of the power supply unit. It is in.

[0005]

In order to achieve the above object, the present invention comprises a power supply device as shown in FIG. Here, in the power supply device, a plurality of the same power supply control units 11, 11 and the power supply control unit 11,
A power source unit 13 controlled by 11 and having a redundancy of a necessary number +1 consisting of the same number of power sources required to supply necessary power + 1, the same power sources 12, 12, 12, and the plurality of power sources on the transmission path. An OR circuit device 14 for taking the logical sum of the control signals output from the power supply control units 11, 11 to the power supply unit 13;
Notification registers 16 and 16 for holding the mutual operation state notification information via the connection between the power supply control units, and the power supply control units 11 and 11 always operate during the normal operation. The status is written in the notification register 16 to enable the other power supply control unit 11 to be notified of the operation status,
At the time of reset, the operating state of the other power supply control unit 11 is read from the notification register 16 and recognized, and the power supply unit 1 is read.
It is characterized in that the operation states are matched so that the instruction states for 3 are the same.

Further, in the power supply control method, a plurality of the same power supply control units 11, 11 and the power supply control unit 1 are provided.
1, the number of power supply units 1 and 11, plus a power supply unit 13 having a power supply 12, 12, 12, and notification registers 16 and 16 for holding operating state notification information. As shown in FIG. However, after issuing a power-off instruction to the power supply unit 13, the communication register 16 as an operation state input destination is set to the initial state (step 21). When the read contents are the power-on state (step 24), the power supply unit 1 is read.
3 to the power-on instruction, and newly set the state of the notification register 16 of the operation state input destination (step 2
5) When the power supply unit 13 is monitored (step 26) and a change in the power-on signal is recognized (step 27), a power-on instruction is issued to the power supply unit 13 and the notification register 16 of the operating state input destination is set. When a new state is set (step 28) and the power supply unit 13 is monitored to recognize a change in the power supply cutoff signal (step 29), a power supply cutoff instruction is issued to the power supply unit 13 and then the operation state input destination The initial state of the notification register 16 is set (step 30).

[0007]

With this configuration, when the power supply device is applied, the power supply control units 11 and 11 are
At any time, the operating state of the own power supply control unit 11 is written in the notification register 16 of the input destination so that the other power supply control unit 11 can be notified of the operating state, and at the time of reset, the other power supply control unit 1
The operation state of No. 1 is read and recognized from the notification register 16 of the reading source, and the states are matched so that the instruction states to the power supply unit 13 are the same in each of the power supply control units 11 and 11. The power supply unit 13 outputs an operation instruction via the OR circuit device 14. In the power supply unit 13 that has received the operation instruction, even if one of the power supplies 12, 12, 12 is abnormal, the other power supply 12, 12 supplies the required voltage and current, so that the power supply unit 13 can provide the minimum necessary power. Allow power to be supplied with the power supply configuration.

Further, in the power supply control method, the power supply control unit 11 for executing the main power supply control issues a power-off instruction to the power supply unit 13 at the time of setting the initial condition, and then the initial state is given to the notification register 16 of the operation state input destination. The setting is performed (step 21), and then the notification register 1 from which the operation status is read
The contents of the state setting of the other power supply control unit 11 are read from 6 (steps 22 and 23). When the read content is the power-on state (step 24), the power-on instruction is issued to the power source unit 13 and the notification register 16 of the operation state input destination is newly set (step 25). After that, when controlling the power supply unit, the power supply unit 13 is monitored (step 26), and when a change in the power-on signal is recognized (step 27), a power-on instruction is issued to the power supply unit 13 and a notification of the operating state input destination is issued. The state of the register 16 is newly set (step 28). When the power supply unit 13 is monitored and a change in the power supply disconnection signal is recognized (step 29), a power supply disconnection instruction is issued to the power supply unit 13 and the initial state of the notification register 16 of the operation state input destination is set (step 30). ). After that, the power supply unit 13 is continuously monitored.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following embodiments of the present invention, a case where two power supply control units are provided will be described.

FIG. 3 is a diagram showing the details of two power supply control units in one embodiment. Here, 11a and 11b are power supply control units, which are equipped with a required number of identical devices (two in the embodiment), and each power supply control unit 11a or 11b independently outputs an instruction signal. Reference numerals 16a and 16b denote state holding registers as notification registers, which are the power control unit 11
The instruction state from a, 11b to the power supply unit 13 (see FIG. 1) is written, and is held until the next instruction state is written. A control panel 17 is provided with an instruction switch 17a for instructing power-on or power-off. Signals from the control panel 17 are sent to the respective power control units 11a, 1a.
It is simultaneously output to 1b. Power control unit 11a (11b)
Is a power-on / power-off instruction receiving unit 111a that receives a pulse signal from the control panel 17 to instruct power-on or power-off.
(112a) and this input / output instruction receiving unit 111a (1
12a) according to the output signal of the power supply control unit 11a (11
a power on / off control unit 111b (112b) for executing power on or power off control in b);
A power on / off instruction holding unit 111c (112c) that holds a power on or power off instruction signal to be output to
The state holding register 16a (16b) indicates the state of the instruction from the turn-on / off control unit 111b (112b) to the power supply unit 13.
To the other power supply control unit 11b from the state writing unit 111d (112d) and the state holding register 16b (16a).
A state reading unit 111e (112e) for reading the instruction state of (11a) to the power supply unit 13 is provided.

FIG. 4 shows the state holding register 16a (16b).
Details of the data held in are shown below. In this data, a PON (Power ON) bit indicates an instruction state to the power supply unit 13, and when the PON bit is 1, it indicates a power-on state, and when it is 0, it indicates a power-off state. Also, AV
The (Availability) bit indicates whether the data held in the PON bit is valid or invalid. When the AV bit is 1, it is valid, and when it is 0, it is invalid.

FIG. 5 shows the structure of the OR circuit device 14 shown in FIG. Here, 14a is a D-FF (flip-flop), and the power-on / off instruction holding unit 1 of the power supply control unit 11a.
The power-on instruction signal (1 = ON) from 11c is input from the D input terminal, and in the case of normal operation, the power-on instruction signal (1) is input from the D input terminal and held from the inverted output terminal (〓). The power-on instruction signal (1) that was output at the same time is output, and when the abnormality display signal is input to the RST (reset) input terminal, the power-on instruction signal (1) is output from the inverted output terminal (〓).
Is output. Reference numeral 14b denotes a D-FF (flip-flop), which is a power-on / off instruction holding unit 112c of the power supply control unit 11b.
Input the power-on instruction signal (1) from the D input terminal, and in the case of normal operation, input the power-on instruction signal (1) from the D input terminal and the power held from the inverted output terminal (〓) Outputs the closing instruction signal (1) and outputs RST
(Reset) When the abnormality display signal is input to the input terminal, the power-on instruction signal (1) is output from the inverted output terminal (〓). 14c is an OR gate circuit, which includes D-FFs 14a and D-FFs.
The logical sum with the FF 14b is calculated and output.

FIG. 6 shows the configuration of the AND circuit device 15 shown in FIG. Here, 15a is a D-FF (flip-flop), and the power-on / off instruction holding unit 1 of the power supply control unit 11a.
The power-off instruction signal (0 = OFF) from 11c is input from the D input terminal, and in the normal operation, the power-off instruction signal (0) is input from the D input terminal and held from the inverting output terminal (〓). The power-off instruction signal (0) that has been output is output, and the power-off instruction signal (0) is output from the inverting output terminal (〓) when the abnormality display signal is input to the RST (reset) input terminal. Reference numeral 15b is a D-FF (flip-flop), which is a turn-on / off instruction holding unit 1 of the power supply control unit 11b.
The power-off instruction signal (0) from 12c was input from the D input terminal, and in the normal operation, the power-off instruction signal (0) was input from the D input terminal and held from the inverting output terminal (〓). Outputs a power-off instruction signal (0) and outputs R
When an abnormality display signal is input to the ST (reset) input terminal, the power-off instruction signal (0) is output from the inverting output terminal (〓). Reference numeral 14c is an AND gate circuit, which takes the logical product of the D-FF 14a and the D-FF 14b and outputs it.

As shown in FIG. 1, the power supply unit 13 can convert a power supply obtained from the outside into a stable voltage used in the computer system and supply a minimum necessary current required for the operation of the computer system. One power supply 12 having the same voltage is used for the number (2 in the embodiment) for supplying the required maximum current.
Equipped with an increased number of redundant power supplies, each power supply 1
The output side of 2 is connected to the input end of the diode 13a, the output sides of the diode 13a are connected to each other,
2 are connected in parallel and a reverse current to each power supply 12 is blocked. The required number of power supplies 12 provided in the power supply unit 13 is the number of power supplies required to maintain the computer system when the minimum power supply for supplying a necessary current at a certain voltage is used. Is. As a minimum power supply for supplying a necessary current at a certain voltage, for example, if a power supply of 5V, 50A is used,
If you need a power supply of 100A, 2V of 5V, 50A
It is only necessary to use three power supplies of 5V and 50A when 5V and 150A are required.
If you manufacture multiple 50A power supplies, each one will produce 5V, 100A
The cost is much lower than that of the case of manufacturing the power source of 5V and the power source of 5V, 150A. In this way, the required power source is 5V,
In the case of 100A, the required number is 2 when the minimum power source of 5V and 50A is used, and in the case of using the minimum power source of 5V and 50A, the required number is 3 when using the minimum power source of 5V and 150A. Becomes Therefore, the power supply unit 13 including the necessary number +1 and the same power supply 12, 12, 12 and having a redundancy of the necessary amount +1 requires the system power supply of 5V, 100A when the power supply of 5V, 50A is used. If you do, it will be equipped with 2 + 1 = 3 (pieces), 5V, 15
3 + 1 = 4 when 0A system power supply is required
It will be equipped with (pieces).

In the embodiment thus constructed, the control is performed as shown in FIGS. 7 to 13 show details of the embodiment with respect to FIG. When each unit is set to the initial state when the power is turned on, as shown in FIG. 7, when the power-on switch 17a of the control panel 17 is pressed to instruct the power-on, both the power control units 11a and 11b are instructed. It is input at the same time and is received by the closing and disconnecting instruction receiving units 111a and 112a, and the fact is notified to the closing and disconnecting control units 111b and 112b. The power-on / off control units 111b and 112b set the power supply control signal to 0 so that the power-on / off instruction holding units 111c and 112c hold the power-supply control signals and notify the power supply unit 13 side to set the PON bit and AV bit of the data to 1. State writing unit 111d, 11
State holding register (Reg1) 1 via 2d
6a and the state holding register (Reg2) 16b. In the OR circuit device 14 to which the power supply control signal (0) is input from both the power supply control units 11a and 11b, the D-FF 14a
And the output signal from the inverting output terminal of the D-FF 14b
The R gate circuit 14c takes the logical sum and outputs it to the power supply unit 13 as a power-on instruction signal. The power supply unit 13 which has received the power-on instruction signal starts supplying power to the system side. Assuming that each unit is set to the ON state when the power is turned off, as shown in FIG.
When the power-off switch 17a is pressed to instruct power-off, the power-off is input to both power-supply control units 11a and 11b at the same time, and the power-on / off instruction receiving units 111a and 112a receive and notify the power-on / off control units 111b and 112b. ..
The power-on / off control units 111b and 112b set the power supply control signal to 1 to cause the power-on / off instruction holding units 111c and 112c to hold the power-supply control signal and notify the power-source unit 13 to notify the
The ON bit is set to 0 and the AV bit is set to 1, and the status holding registers (Reg1) 16a and the status holding register (Reg2) 1 are set via the status writing units 111d and 112d, respectively.
Store in 6b. In the AND circuit device 15 to which the power supply control signal (1) is input from both the power supply control units 11a and 11b, the output signals from the inverting output terminals of the D-FF 15a and D-FF 15b are logically ANDed by the OR gate circuit 15c to supply the power. It is output to the power supply unit 13 as a disconnection instruction signal. The power supply unit 13 that has received the power-off instruction signal stops supplying power to the system side. Power control unit 11 while power is on
When an abnormality occurs in b, as shown in FIG. 9, the power supply control unit 11a sets the power supply control signal to 0, causes the closing / connecting instruction holding unit 111c to hold the power supply control signal, and notifies the power supply unit 13 side. Then, the PON bit of the data is 1, AV
Leave the bit set to 1. At this time, since the power supply control signal is set to 1 in the power supply control unit 11b, the content held in the closing / connecting instruction holding unit 111c changes,
The signal notified to the power supply unit 13 side also changes. Then, in the OR circuit device 14 to which the output signal of the power supply control unit 11a and the output signal of the power supply control unit 11b are input, the D-FF 14a
The output signal from the reverse output end of the
The OR gate circuit 14c logically ORs the output signal from the inverting output terminal of the D-FF 14b input to the input terminal, and outputs the output signal to the power supply unit 13. This output signal is a power-on instruction signal, and the power supply unit 13 that has received this output signal continues to supply power to the system side. When the power supply control unit 11b is pulled out during power-on, as shown in FIG. 10, the power supply control unit 11a sets the power supply control signal to 0 and causes the power-on / off instruction holding unit 111c to hold the power supply control signal, and the power supply unit 13 side. To notify. Then, the PON bit and the AV bit of the data remain set to 1. At this time, since it is not mounted on the power supply controller 11b side, the power supply controller 11 of the OR circuit device 14 is not mounted.
The same state as when the power-off signal is input to the b-side input terminal. Then, the OR circuit device 14 to which the output signal of the power supply control unit 11a and the output signal of the power supply control unit 11b are input
Then, the output signal from the inverting output terminal of the D-FF 14a,
D-FF14 with abnormal display signal input to RST input terminal
The output signal from the inverting output terminal of b is OR gate circuit 14
The logical sum is calculated by c and the output signal is output to the power supply unit 13. This output signal is a power-on instruction signal,
The power supply unit 13 receiving this output signal continues to supply power to the system side. When the power supply control unit 11b is pulled out during power-off, as shown in FIG. 11, the power supply control unit 11a sets the power supply control signal to 1 so that the power-on / off instruction holding unit 111c holds the power supply control signal and the power supply unit 13 side. To notify. Then, the PON bit of the data is 0, A
The V bit is set to 1 and stored in the state holding register (Reg1) 16a via the state writing unit 111d. At this time, since it is not mounted on the power supply control unit 11b side, O
The same state as when the power supply disconnection signal is input to the power control unit 11b side input end of the R circuit device 14 is obtained. Then, in the AND circuit device 15 to which the output signal of the power supply control unit 11a and the output signal of the power supply control unit 11b are input, the D-FF 15
The output signal from the inverted output terminal of a and the abnormality display signal are RS
The AND gate circuit 15c logically ANDs the output signal from the inverted output end of the D-FF 15b input to the T input end, and outputs the output signal to the power supply unit 13. This output signal is a power-off instruction signal, and the power supply unit 13 receiving this output signal maintains the stop of the power supply to the system side. When the power supply control unit 11b is mounted during power-on, as shown in FIG.
1a sets the power supply control signal to 0, holds it in the on / off instruction holding unit 111c, and causes the power supply unit 13 side to notify it. Then, the PON bit and the AV bit of the data remain set to 1. When the power supply control unit 11b is mounted, the power supply control unit 11b reads out the contents held in the state holding register 16a via the state reading unit 112e, sets the power supply control signal to 1, and sets the PON bit of data. 0, the AV bit is set to 1 and stored in the state holding register state holding register 16b via the state writing unit 112d, and the state of the power supply control unit 11a is recognized from the held contents of the read state holding register 16a, The power control signal is reset to 0 according to the state of the power control unit 11a, and the PON bit of data is set to 1 and AV.
The bit is set to 1 and stored in the state holding register state holding register 16b via the state writing unit 112d. In the OR circuit device 14 to which the output signals of the power supply control unit 11a and the power supply control unit 11b are input, the output signal from the inverting output end of the D-FF 14a and the output signal from the inverting output end of the D-FF 14b are OR gate circuit 14c. Then, the logical sum is obtained and output to the power supply unit 13. This output signal is a power-on instruction signal, and the power supply unit 13 receiving this output signal maintains the power supply to the system side. When the power supply control unit 11b is mounted during power-off, as shown in FIG. 13, the power supply control unit 11a sets the power supply control signal to 1 so that the power-on / off instruction holding unit 111c holds the power supply control signal and the power supply unit 13 Notify the side. Then, the PON bit of the data is set to 0 and the AV bit is set to 0, and the state writing unit 111d
It is stored in the state holding register state holding register 16a via. When the power supply control unit 11b is mounted, the power supply control unit 11b reads out the contents held in the state holding register 16a via the state reading unit 112e, sets the power supply control signal to 1, and sets the PON bit of data. 0 and the AV bit are set to 1 and stored in the state holding register state holding register 16b via the state writing unit 112d, and the contents held in the state holding register 16a are recognized,
The power supply control signal is reset to 1 according to the state of the power supply control unit 11a, and the PON bit of the data is set to 0 or A.
The V bit is set to 0 and stored again in the state holding register state holding register 16b via the state writing unit 112d.
In the AND circuit device 15 to which the output signals of the power supply control unit 11a and the power supply control unit 11b are input, the output signal from the inverting output end of the D-FF 15a and the output signal from the inverting output end of the D-FF 15b are AND gate circuit. A logical product is obtained by 15c and output to the power supply unit 13. This output signal is a power-off instruction signal, and the power supply unit 13 receiving this signal keeps stopping the power supply to the system side.

As described above, in the embodiment, although the plurality of power supply control units (power supply control unit 11a and power supply control unit 11b) are provided, the OR circuit device 14 or the AND circuit device 15 instructs the power supply to be turned on. The power supply control unit 11a or 11b can be operated in the same manner as when the power supply control unit 11a or 11b outputs the signal or the power supply cutoff instruction signal, and a plurality of power supply control units (the power supply control unit 11a and the power supply control unit 11b). In the case where one of the two causes an abnormality and is taken out or is mounted after repairing, the other can maintain the power-on state, and the state-holding register 16a or 16b supplies the power of the one causing the abnormality. When the control unit 11a or 11b returns to the normal state, the other normal power supply control unit 11a or 11b
Can be recognized and set to the same state, and the system control can be kept in a single state.
As a result, the power supply unit 13 can be downsized and the combination of the power supply unit 13 and the power supply control units 11a and 11b can be highly reliable, and a highly reliable and downsized power supply device can be realized.

[0017]

As described above, according to the present invention, in the power supply device, each of the power supply control units 11 and 11 has its own power supply control unit 11.
So that the other power source control unit 11 can be notified of the operating state by writing the operating state of the other power source to the notification register 16 of the input destination, and the operating state of the other power source control unit 11 can be read from the notification register 16 of the reading source and recognized. The power supply units 13 and 11 can be set to have the same instruction state, and any of the power supply control units 11 and 11 can cause the power supply unit 13 to output the same operation instruction. Therefore, the power supply unit 13 can reliably receive an operation instruction from any one of the power supply control units 11 and 11, and the operation instruction is unified as if it is an instruction from one power supply control unit 11. You can receive the instructions given. As a result, the power supply unit 13 can operate as if it received an instruction from one power supply control unit 11, and even if one of the power supplies 12, 12, 12 is abnormal, the voltage required by the other power supply 12, 12 is required. It is possible to realize the power supply unit 13 that can supply current and can supply power with the minimum necessary power supply configuration. Furthermore, the power supply control units 11, 1
Since the same operation instruction can be issued to the power supply unit 13 from any one of them, the other can be replaced or repaired while one is issuing the operation instruction, and the computer system can be operated without stopping the power supply. Can be operated.
Therefore, the power supply unit 13 can be downsized and the combination of the power supply unit 13 and the power supply control units 11a and 11b can be made highly reliable, and a highly reliable and downsized power supply device can be realized.

Further, in the power supply control method, the power supply control unit 11 for executing the main power supply control issues a power-off instruction to the power supply unit 13 at the time of setting the initial condition and then sets the initial state in the communication register 16 of the operation state input destination. After setting, the state setting contents of the other power source control unit 11 are read from the communication register 16 of the operation state reading source, and when the read contents are the power-on state, a power-on instruction is issued to the power source unit 13 and operation is performed. Since the communication register 16 of the status input destination is newly set, a plurality of power supply control units 11
Can set the same state, and can issue the same power-on instruction to the power supply unit 13. When controlling the power supply unit after setting the initial conditions, the power supply unit 13 is monitored, and when a change in the power-on signal is recognized, a power-on instruction is issued to the power supply unit 13 and the communication register 16 of the operation state input destination is newly added. When the change in the power-off signal is recognized, the power-off instruction is issued to the power supply unit 13 and the initial state of the communication register 16 of the operation state input destination is set. Part 11 is communication register 16
It is possible to control the power supply unit 13 by issuing the same instruction from any of the power supply control units 11 and 11 by making it possible to set the same condition via the.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a flowchart showing a power supply control method according to the present invention.

FIG. 3 is a configuration diagram showing a power supply control unit in the embodiment.

FIG. 4 is an explanatory diagram showing data in a state holding register in the embodiment.

FIG. 5 is a configuration diagram showing an OR circuit device according to an embodiment.

FIG. 6 is a configuration diagram showing an AND circuit device according to an embodiment.

FIG. 7 is a process flow chart showing an operation at power-on in the embodiment.

FIG. 8 is a process flow chart showing an operation at power-off in the embodiment.

FIG. 9 is a process flow chart showing an operation when an abnormality occurs in the power supply control unit during power-on in the embodiment.

FIG. 10 is a process flow chart showing an operation when the power supply control unit is removed during power-on in the embodiment.

FIG. 11 is a process flow chart showing an operation in the case where the power supply control unit is pulled out during power-off in the embodiment.

FIG. 12 is a process flow chart showing an operation when a power supply control unit is mounted during power-on in the embodiment.

FIG. 13 is a process flow chart showing an operation in the case where the power supply control unit is mounted while the power is off in the embodiment.

FIG. 14 is a configuration diagram showing a conventional power supply device.

[Explanation of symbols]

11 power supply control unit 12 power supply 13 power supply unit 13a diode 14 OR circuit device 15 AND circuit device 16 notification register 17 control panel 17a ON / OFF switch (turn-on / off instruction switch)

Claims (2)

[Claims] 1. A same power supply control unit (1) composed of a plurality of units.
1, 11) and the same power supply (1), which is controlled by the power supply control unit (11, 11) and is the number required to supply necessary power + 1
2, 12 and 12) and a power supply unit (13) having a necessary redundancy of +1 and a plurality of power supply control units (11, 11) on the transmission path to the power supply unit (13). An OR circuit device (14) that takes the logical sum of control signals and a notification register (16, 16) that mediates the connection between the power supply control units and holds mutual operation state notification information, the power supply control unit ( (11, 11) always writes the operating state of its own power source control unit (11) in the notification register (16) during normal operation to enable the other power source control unit (11) to be notified of the operating state, and at the time of resetting. The operation state of the other power supply control unit (11) is input from the notification register (16) and recognized, and the operation state is adjusted so that the instruction state to the power supply unit (13) becomes the same. Power supply. 2. The same power supply control unit (1) composed of a plurality of units.
1, 11) and the number of power supply control units (11, 11) +1
Power supply unit (13) having individual power supplies (12, 12, 12)
And a notification register (16,
16), the power supply control unit (11) sets an initial state of the notification register (16) as an operation state input destination after issuing a power-off instruction to the power supply unit (13) (step 21), After that, the state setting contents of the other power supply control unit (11) are read from the notification register (16) from which the operation state is read (steps 22 and 23), and when the read contents are in the power-on state (step 24), the power supply is turned on. The power-on instruction to the section (13) and the notification register (1
6) is newly set (step 25), the power supply unit (13) is monitored (step 26), and when a change in the power-on signal is recognized (step 27), the power supply unit (13) is powered on. When an instruction is issued and the notification register (16) of the operation state input destination is newly set (step 28) and the power supply unit (13) is monitored to recognize a change in the power-off signal (step 29). The power supply control method is characterized in that after issuing a power-off instruction to the power supply unit (13), the initial state of the notification register (16) as an operation state input destination is set (step 30).