JPH0583177A - Diversity receiver - Google Patents

Abstract

PURPOSE:To decrease the deterioration in a recovery clock characteristic such as jitter due to changeover of a detection output by implementing the changeover of a detection output in a timing dissident with the synchronization discrimination timing in the clock recovery. CONSTITUTION:A detection output changeover control circuit 18 outputs a detection output changeover clock 19 having a prescribed phase shift to a demodulation synchronizing clock synchronously with the synchronization discrimination timing of the clock recovery. A comparison discrimination output 12 is latched at a detection output changeover flip-flop 24 by using a detection output changeover clock 19 and the selection changeover of the detection output is implemented by a detection output changeover switch 13 synchronously with the clock 19. Thus, the selection changeover of the detection output is implemented in a deviated timing according to the phase shift set by the detection output changeover control circuit 18 with respect to the synchronization discrimination timing of the clock recovery. Thus, waveform distortion due to the changeover of the detection output is not generated around the synchronization discrimination timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a diversity receiver of post-detection selection type which reduces deterioration of transmission quality due to frequency selective fading in digital mobile communication and the like.

[0002]

2. Description of the Related Art A conventional selection type diversity receiver uses reception level information as a means for detecting a reception state,
There is a receiver having a configuration as shown in the block diagram of FIG. 5 which selects two series of receiving systems based on this. The operation of the above conventional example will be described below with reference to the block diagram of FIG. 5 and the timing chart of FIG. The signal received by the antenna (1) 1-1 is frequency-converted and amplified by the receiving unit (1) 2-1 and detected by the detector (1) 4-1 to be detected output (1) 5
-1 is input to the detection output changeover switch 13 and is also subjected to decoding processing in the data reproduction circuit (1) 6-1 and is output from the data parallel-serial conversion circuit (1) 7-1 as reproduction data output (1) 8-1. It is input to the data changeover switch 22. Similarly, the signal received by the antenna (2) 1-2 is similarly detected by the detection output (2) 5-2 of the detector (2) 4-2.
Is input to the detection output switch 13, and the reproduction data output (2) 8-2 is input to the data switch 22.

The comparison / determination unit 11 compares the reception level information 9-1, 9-2 from the reception unit (1) 2-1 and the reception unit (2) 2-2, which are changing instantaneously, and makes the determination. The output 12 is input to the data switching flip-flop 20, and the detection output switching switch 13 is operated. The clock regeneration circuit 15 regenerates the clock by the selective detection output 14 selected by the detection output changeover switch 13. The reproduction data output is selected by the data changeover switch 22, and the comparison / judgment output 12 is once outputted by the data changeover flip-flop 20 to the data synchronization clock 1
Since it is held by 6, it is switched in synchronization with the data synchronization clock 16. FIG. 6 shows the timing operation of switching the detection output and switching the reproduction data. The comparison / determination output 12 obtained by comparing the reception level information 9-1, 9-2 from the reception unit (1) 2-1 and the reception unit (2) 2-2,
When "L", the detection output (1) 5-1 is selected, and when "H", the detection output (2) 5-2 is selected. The selective detection output 14 output from the detection output selector switch 13 has waveform distortion at the time of switching, but the fluctuation on the time axis is small, and the clock recovery circuit 15 has a reception system of 1 or less.
The data synchronization clock 16 can be output more stably than in the two cases.

On the other hand, the comparison / determination output 12 is held in the data switching flip-flop 20 by the data synchronization clock 16 and becomes the data switching signal 21. Playback data output (1) 8 when this data switching signal 21 is "L"
When -1 is "H", reproduction data output (2) 8-2 is selected by the data changeover switch 22 to obtain a reception data output 23. In this way, by switching the reproduction data output of the reception system having a high reception level and few errors in synchronization with the data synchronization clock 16, a data signal with reduced errors can be obtained.

[0005]

By the way, the clock recovery circuit 15 determines the synchronization timing at the intersection of the median detection output and the selective detection output 14 shown by the alternate long and short dash line in FIG. 6 (8). .. Therefore, in the conventional detection output selection switching method, when the detection output switching timing is near this crossing point, the synchronization timing is determined near the point where waveform distortion occurs, and the reproduction clock such as jitter is reproduced. Characteristic deterioration will occur. SUMMARY OF THE INVENTION In order to solve the above-mentioned drawbacks, the present invention aims to reduce the deterioration of reproduction clock characteristics such as jitter due to switching of the detection output by controlling the switching of the detection output at a timing that does not coincide with the synchronization determination timing in clock reproduction. And

[0006]

In order to achieve the above object, the present invention is provided with a detection output switching control circuit, controls the demodulation synchronous clock from the clock reproduction, and rises to a timing that does not coincide with the synchronization determination timing. It outputs the detection output switching clock having the above, and controls the timing of the detection output switching with this clock.

[0007]

As a result, the selective switching of the detection output can be performed at a timing that does not coincide with the synchronization determination timing, and the characteristic deterioration of the reproduced clock due to the switching of the detection output can be considerably reduced.

[0008]

Embodiments of the present invention will be described below with reference to FIGS. 1, 2 and 3-1, FIG. 3-2, FIG. 4-1, and FIG. FIG. 1 is a block diagram of a diversity receiver showing an embodiment of the present invention having a two-series reception system. Similarly to the conventional example, the signal received by the antenna (1) 1-1 is frequency-converted and amplified by the receiving unit (1) 2-1 and detected by the detector (1) 4-1 to detect the detection output ( 1) Input to the detection output changeover switch 13 as 5-1 and
The data reproduction circuit (1) 6-1 performs decoding processing, and the data parallel-serial conversion circuit (1) 7-1 outputs reproduction data (1) 8
-1 is input to the data changeover switch 22.
Similarly, the signals received by the antenna (2) 1-2 are
The detection output (2) 5-2 of the detector (2) 4-2 is output to the detection output changeover switch 13 as the reproduction data output (2) 8-2.
Is input to the data changeover switch 22.

The comparison / determination unit 11 receives the reception level information 9-1, 9- from the receiving unit (1) 2-1 and the receiving unit (2) 2-2.
2 is compared, and the judgment output 12 is combined with the data switching flip-flop 20 and the detection output switching flip-flop 20.
Input to the flop 24. The reproduction data output is selected by the data changeover switch 22, and the comparison judgment output 12
Is once held by the data switching clock 16 in the data switching flip-flop 20, so that it is switched in synchronization with the data synchronizing clock 16. On the other hand, the detection output is selected by the detection output switching switch 13, and the comparison / determination output 12 is held by the detection output switching flip-flop 24 by the detection output switching clock 19 output from the detection output switching control circuit 18. ，
Switching is performed in synchronization with the detection output switching clock 19. The detection output switching clock 19 uses the demodulation synchronization clock 17 that is synchronized with the synchronization determination timing of the clock reproduction, so that the inverter circuit 26 in FIG.
It is output by the detection output switching control circuit 18 using the one-shot multivibrator circuit 27, etc., and in the case of the inverter circuit 26, as shown in the timing chart of FIG. Phase shift, one-shot multivibrator circuit 27
In this case, as shown in the timing chart of FIG. 4-2, an arbitrary phase shift is set for the demodulation synchronization clock 17. Therefore, the selection switching of the detection output is performed with a timing shift with respect to the synchronization determination timing of the clock reproduction according to the phase shift set by the detection output switching control circuit 18.

FIG. 2 shows the timing operation of the detection output switching and the reproduction data output switching. Regarding the detection output switching control circuit 18, the timing operation of the (4-1) detection output switching clock 19 is shown assuming that the inverter circuit 26 of FIG. 3-1 is used. Comparison judgment device 1
1 compares the reception level information 9-1, 9-2 from the receiving unit (1) 2-1 and the receiving unit (2) 2-2, and the receiving unit (1)
When the reception level information 9-1 of 2-1 is high, "L" is output, and when the level of the reception level information 9-2 of the receiving unit (2) 2-2 is high, "H" is output. Demodulation synchronization clock 17 output from the clock recovery circuit 15
Is inverted by the detection output switching control circuit 18 to become a detection output switching clock 19. The comparison judgment output 12 is
When the detection output switching signal 25, which is held in the detection output switching flip-flop 24 by the detection output switching clock 19 and is output, is "L", the detection output (1)
When the output 5-1 is "H", the detection output (2) 5-2 is switched by the detection output switching switch 13 to output the selected detection output 14. Clock recovery circuit 15
Performs clock recovery with this selective detection output 14,
The demodulation synchronization clock 17 is output together with the stable data synchronization clock 16.

On the other hand, the comparison / judgment output 12 is the data switching flip-flop 2 by the data synchronization clock 16.
It is also held at 0 to become the data switching signal 21, and when the data switching signal 21 is “L”, the reproduction data output (1) 8-1 is output, and when it is “H”, the reproduction data output (2) 8 is output.
-2, data change switch 2
In step 2, the received data output 23 is obtained. As can be seen from the waveform of the (8) selective detection output 14 in FIG. 2, although waveform distortion occurs at the time of switching the detection output, it does not coincide with the synchronization judgment timing of clock reproduction, and the characteristic deterioration such as jitter due to switching does not occur. A small amount of stable recovered clock output can be obtained, and a better diversity effect can be obtained. Although the case where the reception system has two series has been described here, the same configuration can be realized when the reception system has three or more series. Further, as a method of detecting the reception state, there is also a method of detecting a change in the detection output (eye pattern) on the time axis or an eye opening.

[0012]

As described above, according to the present invention, a diversity receiver capable of obtaining a stable recovered clock output and obtaining a good diversity effect when receiving a digital modulation signal including a multi-valued system is configured. it can. Further, the present invention can be applied to general wireless communication systems as well as mobile communication.

[Brief description of drawings]

1 is a block diagram of a diversity receiver showing an embodiment of the present invention. 2 is a timing chart diagram in FIG. 3-1 and 4-1 are examples of circuits used in the detection output switching control circuit in the block diagram of the embodiment of the present invention. FIGS. 3-2 and 4-2 are timing charts of the respective circuits. 5 is a block diagram of a conventional diversity receiver. 6 is a timing chart diagram in FIG.

[Explanation of symbols]

 1-1 Antenna (1) 1-2 Antenna (2) 2-1 Receiver (1) 2-2 Receiver (2) 3-1 Received output (1) 3-2 Received output (2) 4-1 Detection Detector (1) 4-2 Detector (2) 5-1 Detection output (1) 5-2 Detection output (2) 6-1 Data recovery circuit (1) 6-2 Data recovery circuit (2) 7-1 Data Parallel-serial conversion circuit (1) 7-2 Data parallel-serial conversion circuit (2) 8-1 Reproduction data output (1) 8-2 Reproduction data output (2) 9-1 Reception level information (1) 9-2 Reception level Information (2) 10-1 Reception system (1) 10-2 Reception system (2) 11 Comparison judgment device 12 Comparison judgment output 13 Detection output changeover switch 14 Selection detection output 15 Clock recovery circuit 16 Data synchronization clock 17 Demodulation synchronization clock 18 Detection output switching control circuit 19 Detection output Toggles clock 20 data switching flip-flop 21 data switching signal 22 data selector switch 23 receives data output 24 detection output switching flip-flop 25 detects the output switching signal 26 inverter circuit 27 one-shot multivibrator circuit

Claims (1)

[Claims] 1. A receiver of a digital communication device for receiving a digitally modulated signal including a multi-valued system, comprising a receiver having a function of detecting a reception state, a detector, a data regenerating circuit and a data parallel-serial conversion circuit. A plurality of reception systems configured, a comparison / determination device that compares detection results of reception states, a clock recovery circuit that performs clock recovery, a changeover switch that selects detection output to the clock recovery circuit and its switching control circuit, and a reception system It is composed of a changeover switch that selects the reproduction data output, and becomes a switching signal that switches the judgment output from the comparison judgment unit at the timing that does not become the synchronization judgment timing in the clock reproduction by the reproduction clock from the clock reproduction in the switching control circuit. Control, the clock output is selected by the detection output selected by this signal, and received. A diversity receiver characterized by selectively switching the output of the reproduction data of the communication system in synchronization with the reproduction clock and outputting the reception data.