JPH0582719A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0582719A
JPH0582719A JP23840691A JP23840691A JPH0582719A JP H0582719 A JPH0582719 A JP H0582719A JP 23840691 A JP23840691 A JP 23840691A JP 23840691 A JP23840691 A JP 23840691A JP H0582719 A JPH0582719 A JP H0582719A
Authority
JP
Japan
Prior art keywords
chips
semiconductor device
chip
pads
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23840691A
Other languages
Japanese (ja)
Other versions
JP2568771B2 (en
Inventor
Atsushi Hatakeyama
淳 畠山
Fumio Baba
文雄 馬場
Junichi Kasai
純一 河西
Mitsutaka Sato
光孝 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3238406A priority Critical patent/JP2568771B2/en
Publication of JPH0582719A publication Critical patent/JPH0582719A/en
Application granted granted Critical
Publication of JP2568771B2 publication Critical patent/JP2568771B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements

Abstract

PURPOSE:To provide a semiconductor device which is capable of using chips whose circuit layout is identical and incorporate a plurality of chips into a package without using mirror-inversion chips as for a semiconductor device, and especially a semiconductor device into which a plurality of chips are encapsulated in one package. CONSTITUTION:In terms of a semiconductor device into which a plurality of chips 20 and 22 are encapsulated in one package 24, each of the chips 20 and 22 is provided with the same circuit layout while there are installed a plurality of pads D to D and D' to D' in the center of the package in such a fashion that they may be laid out virtually in one row. A pair of chips 20 and 22 out of the chips 20 and 22 are arranged so that their identical characteristic sides may be joined with each other.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置、特に、複
数のチップ１が１つのパッケージに封入された半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of chips 1 are enclosed in one package.

【０００２】半導体記憶装置の１つ当たりのビット容量
は、３年で４倍という高い割合で増加している。そし
て、ある時代に達成できるビット容量は、その時代に達
成できる露光技術のレベルによって、ほぼ決められる。
ところが、近年の情報処理装置には、小型化、低コスト
化、高機能化が要求されており、このため、半導体記憶
装置には、ビット容量の更なる増加が求められている。The bit capacity per semiconductor memory device has increased at a high rate of four times in three years. The bit capacity that can be achieved in a certain era is almost determined by the level of exposure technology that can be achieved in that era.
However, recent information processing apparatuses are required to be small in size, low in cost, and highly functional, and therefore, the semiconductor memory device is required to further increase the bit capacity.

【０００３】上記ビット容量の更なる増加に対処するた
め、１つのパッケージ内に複数のチップを封入する技術
が提案されている。ところが、１つのパッケージに複数
のチップを封入するためには、回路配置をミラー反転し
た２種類のチップを準備しなければならず、これは、半
導体記憶装置の製造上の容易化及び効率化を妨げてい
た。本発明は、このような問題を解決した半導体装置を
提供するものである。In order to cope with the further increase of the bit capacity, a technique of enclosing a plurality of chips in one package has been proposed. However, in order to enclose a plurality of chips in one package, it is necessary to prepare two types of chips in which the circuit arrangement is mirror-reversed, which facilitates manufacturing of semiconductor memory devices and increases efficiency. It was hindering me. The present invention provides a semiconductor device that solves such a problem.

【０００４】[0004]

【従来の技術】図７には、従来の半導体装置が示され、
（Ａ）は平面図、（Ｂ）は底面図、（Ｃ）は断面図であ
る。2. Description of the Related Art FIG. 7 shows a conventional semiconductor device,
(A) is a plan view, (B) is a bottom view, and (C) is a sectional view.

【０００５】半導体装置は、２つのチップ１０、１２を
含み、該チップ１０、１２は、その回路素子が形成され
た面１０ａ、１２ａの裏面１０ｂ、１２ｂが互いに接合
され、このように接合されたチップ１０、１２は、１つ
のパッケージ１４内に封入されている。ここで、前記チ
ップ１０は、通常の汎用品と同一のチップであるが、前
記チップ１２は、チップ１０の回路配置をミラー反転し
た回転配置を有する特殊なチップである。なお、符号１
６、１８は、チップ１０、１２を区別するためのマーク
である。The semiconductor device includes two chips 10 and 12, and the chips 10 and 12 are bonded to each other at the back surfaces 10b and 12b of the surfaces 10a and 12a on which the circuit elements are formed. The chips 10 and 12 are enclosed in one package 14. Here, the chip 10 is the same chip as a general-purpose product, but the chip 12 is a special chip having a rotational arrangement in which the circuit arrangement of the chip 10 is mirror-inverted. Note that reference numeral 1
Reference numerals 6 and 18 are marks for distinguishing the chips 10 and 12.

【０００６】前記チップ１０のパッドＤ１〜Ｄ６、Ｄ８
〜Ｄ１２は、それぞれ、ピンＰ１〜Ｐ６、Ｐ８〜Ｐ１２
にリード（例えばボンディング）Ｒ１〜Ｒ６、Ｒ８〜Ｒ
１２で接続され、チップ１２のパッドＤ１′〜Ｄ６′、
Ｄ８′〜Ｄ１２′は、それぞれ、ピンＰ１〜Ｐ６、Ｐ８
〜Ｐ１２にリードＲ１′〜Ｒ６′、Ｒ８′〜Ｒ１２′で
接続されている。なお、ピンＰ７は、チップ１０、１２
に接続されないノンコネクティングピンであり、また、
ピンＰ１３、Ｐ１４は、それぞれ、チップ１０のパッド
Ｄ１３、チップ１２のパッドＤ１４′にリードＲ１３、
Ｒ１４′で接続されるチップセレクトピンである。Pads D1 to D6 and D8 of the chip 10
To D12 are pins P1 to P6 and P8 to P12, respectively.
Leads (for example, bonding) R1 to R6, R8 to R
12 and the pads D1 ′ to D6 ′ of the chip 12,
D8 'to D12' are pins P1 to P6 and P8, respectively.
To P12 are connected by leads R1 'to R6' and R8 'to R12'. The pin P7 is connected to the chips 10 and 12
Is a non-connecting pin that is not connected to
The pins P13 and P14 are connected to the pad D13 of the chip 10 and the pad R14 'of the chip 12 with leads R13 and
It is a chip select pin connected by R14 '.

【０００７】上記の構成において、ピンＰ１３、１４以
外のピンＰ１〜Ｐ６、Ｐ８〜Ｐ１２は、チップ１０のパ
ッドＤ１〜Ｄ６、Ｄ８〜Ｄ１２に接続され、更に、チッ
プ１２のパッドＤ１′〜Ｄ６′、Ｄ８′〜Ｄ１２′に接
続されており、すなわち、チップ１０、１２に共通に接
続されている。従って、図７の半導体装置によれば、１
つのチップをもつ半導体装置と比較して、ほぼ同じ大き
さで２倍の容量をもつ半導体記憶装置が達成される。In the above structure, the pins P1 to P6 and P8 to P12 other than the pins P13 and 14 are connected to the pads D1 to D6 and D8 to D12 of the chip 10, and the pads D1 'to D6' of the chip 12 are further connected. , D8 ′ to D12 ′, that is, they are commonly connected to the chips 10 and 12. Therefore, according to the semiconductor device of FIG.
As compared with a semiconductor device having one chip, a semiconductor memory device having almost the same size and twice the capacity can be achieved.

【０００８】[0008]

【発明が解決しようとする課題】上記従来の半導体装置
においては、回路配置の異なる２種類のチップ１０、１
２が使用される。ここで、チップ１０は、汎用品である
ため、通常の１チップのパッケージにも使用できるが、
チップ１２は、特殊な回路配置のため、本構成のパッケ
ージ以外には使用できない。このため、チップ１２は、
これと同数のチップ１０がないとパッケージに組み込む
ことができない。In the above conventional semiconductor device, two types of chips 10 and 1 having different circuit arrangements are used.
2 is used. Here, since the chip 10 is a general-purpose product, it can be used for an ordinary one-chip package.
Since the chip 12 has a special circuit arrangement, it cannot be used for any package other than this package. Therefore, the chip 12
Without the same number of chips 10, it cannot be incorporated into a package.

【０００９】ところが、通常、１チップの半導体装置の
注文が大量にあった場合等には、当初２チップの半導体
装置に組み込む予定であったチップ１０を使用すること
になる。このため、チップ１２は、パッケージに組み込
まれずに保管されることとなり、生産管理や在庫管理が
非常に煩雑になるという問題がある。However, when there is a large number of orders for a one-chip semiconductor device, the chip 10 originally intended to be incorporated in a two-chip semiconductor device is used. Therefore, the chip 12 is stored without being incorporated in the package, and there is a problem that production management and inventory management become very complicated.

【００１０】また、チップ１０、１２は、製造工程が同
一であるにもかかわらず、そのマスクパターンが異なっ
ており、これは、生産ラインに負担をかけることにな
る。本発明は、上記従来の課題に鑑みてなされたもので
あり、その目的は、ミラー反転したチップを使用するこ
となく、同一の回路配置をもつチップを使用して、複数
のチップをパッケージに組み込むことができる半導体装
置を提供することにある。Further, the chips 10 and 12 have different mask patterns even though the manufacturing processes are the same, which puts a burden on the production line. The present invention has been made in view of the above conventional problems, and an object thereof is to incorporate a plurality of chips into a package by using a chip having the same circuit arrangement without using a mirror-inverted chip. An object is to provide a semiconductor device that can be manufactured.

【００１１】[0011]

【課題を解決するための手段】本発明は、複数のチップ
（２０、２２）が１つのパッケージ（２４）に封入され
た半導体装置において、前記複数のチップ（２０、２
２）のそれぞれは、同一の回路配置であり、その中央に
はほぼ１列に配置された複数のパッド（Ｄ〜Ｄ、Ｄ′〜
Ｄ′）を有しており、前記複数のチップ（２０、２２）
のうち一対のチップ（２０、２２）は、その同一特性面
（２０ａ、２２ａ：２０ｂ、２２ｂ）が互いに接合され
ていることを特徴とする。According to the present invention, in a semiconductor device in which a plurality of chips (20, 22) are enclosed in one package (24), the plurality of chips (20, 2) are provided.
Each of 2) has the same circuit arrangement, and a plurality of pads (D to D, D ′ to) arranged in almost one column are arranged in the center thereof.
D ') and the plurality of chips (20, 22)
The pair of chips (20, 22) is characterized in that the same characteristic surfaces (20a, 22a: 20b, 22b) are bonded to each other.

【００１２】[0012]

【作用】本発明において、チップ（２０、２２）の中央
には、複数のパッド（Ｄ〜Ｄ、Ｄ′〜Ｄ′）がほぼ１列
に配置されているので、１つのチップ（２２）を裏返し
て他のチップ（２０）に接合した場合に、ピン（Ｐ〜
Ｐ）から見たパッド（Ｄ〜Ｄ、Ｄ′〜Ｄ′）の位置は、
両チップ１０、１２で同一になる。それゆえ、２つのチ
ップ（２０、２２）を貼り合わせた場合に、ピン（Ｐ〜
Ｐ）からパッド（Ｄ〜Ｄ、Ｄ′〜Ｄ′）への接続を、両
チップ（２０、２２）で同様に行うことができる。In the present invention, a plurality of pads (D to D, D'to D ') are arranged in a line in the center of the chip (20, 22), so that one chip (22) is formed. When flipped over and joined to another chip (20),
The positions of the pads (D to D, D'to D ') viewed from P) are
Both chips 10 and 12 are the same. Therefore, when the two chips (20, 22) are bonded together, the pins (P ~
Connections from P) to pads (D-D, D'-D ') can be made in both chips (20, 22) as well.

【００１３】[0013]

【実施例】以下、図面に基づいて本発明の好適な実施例
を説明する。図１には、本発明の第１実施例による半導
体装置が示され、（Ａ）は平面図、（Ｂ）は底面図、
（Ｃ）は断面図、（Ｄ）は斜視図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor device according to a first embodiment of the present invention, (A) is a plan view, (B) is a bottom view,
(C) is a sectional view and (D) is a perspective view.

【００１４】半導体装置は、２つのチップ２０、２２を
含み、該チップ２０、２２は、その回路素子が形成され
た面２０ａ、２２ａの裏面２０ｂ、２２ｂが互いに接合
され、このように接合されたチップ２０、２２は、１つ
のパッケージ２４内に封入されている。ここで、チップ
２０、２２は、従来装置（図７参照）と異なり、同一の
回路配置を有している。The semiconductor device includes two chips 20 and 22, and the chips 20 and 22 are bonded to each other at the back surfaces 20b and 22b of the surfaces 20a and 22a on which the circuit elements are formed. The chips 20 and 22 are enclosed in one package 24. Here, the chips 20 and 22 have the same circuit arrangement, unlike the conventional device (see FIG. 7).

【００１５】チップ２０、２２の回路素子形成面２０
ａ、２２ａには、中央の長手方向を除いて、絶縁膜２
６、２８が形成されている。そして、チップ２０、２２
の中央では、長手方向に沿って、複数のパッドＤ１〜Ｄ
６、Ｄ８〜Ｄ１２、及び、複数のパッドＤ１′〜Ｄ
６′、Ｄ８′〜Ｄ１２′が１列に配置されている。チッ
プ１０のパッドＤ１〜Ｄ６、Ｄ８〜Ｄ１２は、ピンＰ１
〜Ｐ６、Ｐ８〜Ｐ１２にリード（例えばボンディング）
Ｒ１〜Ｒ６、Ｒ８〜Ｒ１２で接続されている。同様にし
て、チップ１２のパッドＤ１′〜Ｄ６′、Ｄ８′〜Ｄ１
２′は、ピンＰ１〜Ｐ６、Ｐ８〜Ｐ１２にリードＲ１′
〜Ｒ６′、Ｒ８′〜Ｒ１２′で接続されている。Circuit element forming surface 20 of the chips 20, 22
a and 22a, except for the central longitudinal direction, the insulating film 2
6, 28 are formed. And the chips 20, 22
At the center of the plurality of pads D1 to D along the longitudinal direction.
6, D8-D12, and a plurality of pads D1'-D
6'and D8 'to D12' are arranged in one row. The pads D1 to D6 and D8 to D12 of the chip 10 are pin P1.
~ P6, P8 ~ P12 lead (eg bonding)
They are connected by R1 to R6 and R8 to R12. Similarly, the pads D1 'to D6' and D8 'to D1 of the chip 12 are
2'leads R1 'to pins P1 to P6 and P8 to P12.
~ R6 ', R8' to R12 'are connected.

【００１６】なお、ピンＰ７は、チップ１０、１２に接
続されないノンコネクティングピンであり、また、ピン
Ｐ１３、Ｐ１４は、それぞれ、チップ１０のパッドＤ１
３、チップ１２のパッドＤ１４′にリードＲ１３、Ｒ１
４′で接続されるチップセレクトピンである。また、リ
ードＲ１〜Ｒ６、Ｒ８〜Ｒ１２、Ｒ１３は、チップ２０
の絶縁膜２６上に配置され、同様にして、リードＲ１′
〜Ｒ６′、Ｒ８′〜Ｒ１２′、Ｒ１４′は、チップ２２
の絶縁膜２８上に配置されている。The pin P7 is a non-connecting pin not connected to the chips 10 and 12, and the pins P13 and P14 are the pads D1 of the chip 10, respectively.
3. Leads R13 and R1 on the pad D14 'of the chip 12
4'is a chip select pin connected. Further, the leads R1 to R6, R8 to R12, and R13 are connected to the chip 20.
Of the lead R1 'in the same manner.
~ R6 ', R8' to R12 ', R14' are chip 22
Is disposed on the insulating film 28.

【００１７】上述した第１実施例の半導体装置によれ
ば、チップ２０、２２の中央には、長手方向に沿って、
パッドＤ〜Ｄ、Ｄ′〜Ｄ′が１列に配置されているの
で、チップ２０、２２の裏面２０ｂ、２２ｂを互いに接
合した場合に、ピンＰ〜Ｐから見たパッドＤ〜Ｄ、Ｄ′
〜Ｄ′の位置は、両チップ１０、１２で同一になる。そ
れゆえ、２つのチップ２０、２２を貼り合わせた場合
に、ピンＰ〜ＰからパッドＤ〜Ｄ、Ｄ′〜Ｄ′への接続
を、両チップ２０、２２で同様に行うことができる。According to the above-described semiconductor device of the first embodiment, the chips 20 and 22 are provided at the centers thereof along the longitudinal direction.
Since the pads D to D and D'to D'are arranged in one row, the pads D to D and D'as seen from the pins P to P when the back surfaces 20b and 22b of the chips 20 and 22 are bonded to each other.
The positions of ~ D 'are the same for both chips 10,12. Therefore, when the two chips 20 and 22 are bonded together, the connection from the pins P to P to the pads D to D and D'to D'can be similarly performed in both chips 20 and 22.

【００１８】次に、図２には、本発明の第２実施例によ
る半導体装置が示され、（Ａ）は断面図、（Ｂ）は斜視
図である。前記第１実施例の半導体装置（図１参照）に
おいては、チップ２０、２２の裏面２０ｂ、２２ｂを互
いに接合しているが、本第２実施例の半導体装置におい
ては、チップ２０、２２の回路素子形成面２０ａ、２２
ａを互いに接合している。この場合に、チップ２０、２
２は、ピンＰ〜Ｐから直接延びたリードＲ〜Ｒを間に挟
み込む状態にて、接合され、パッケージ２４に封入され
ている。なお、リードＲ〜Ｒは、チップ２０、２２のパ
ッドＤ〜Ｄ、Ｄ′〜Ｄ′に接続されている。Next, FIG. 2 shows a semiconductor device according to a second embodiment of the present invention, wherein (A) is a sectional view and (B) is a perspective view. In the semiconductor device of the first embodiment (see FIG. 1), the back surfaces 20b and 22b of the chips 20 and 22 are bonded to each other, but in the semiconductor device of the second embodiment, the circuits of the chips 20 and 22 are connected. Element forming surfaces 20a, 22
a is joined to each other. In this case, the chips 20, 2
2 are joined and encapsulated in a package 24 with the leads R to R extending directly from the pins P to P sandwiched therebetween. The leads R to R are connected to the pads D to D and D'to D'of the chips 20 and 22, respectively.

【００１９】次に、図３には、本発明の第３実施例によ
る半導体装置が示され、（Ａ）は平面図、（Ｂ）は底面
図である。前記第１実施例（図１参照）及び第２実施例
（図２参照）においては、チップ２０、２２の中央の長
手方向に沿って、複数のパッドＤ〜Ｄ、Ｄ′〜Ｄ′が１
列に配置されているが、本第３実施例の半導体装置にお
いては、チップ２０、２２の中央にあり短辺に平行な方
向に沿って、複数のパッドＤ〜Ｄ、Ｄ′〜Ｄ′が１列に
配置されている。このように複数のパッドＤ〜Ｄ、Ｄ′
〜Ｄ′を配置することによっても、本発明は実施可能で
ある。Next, FIG. 3 shows a semiconductor device according to a third embodiment of the present invention, wherein (A) is a plan view and (B) is a bottom view. In the first embodiment (see FIG. 1) and the second embodiment (see FIG. 2), a plurality of pads D to D and D ′ to D ′ are arranged along the central longitudinal direction of the chips 20 and 22.
Although arranged in rows, in the semiconductor device of the third embodiment, a plurality of pads D to D and D'to D'are provided along the direction in the center of the chips 20 and 22 and parallel to the short side. They are arranged in one row. In this way, a plurality of pads D to D, D '
The present invention can be implemented by arranging ~ D '.

【００２０】上記第１実施例（図１参照）及び第２実施
例（図２参照）を応用することにより、１つのパッケー
ジ内に４つ、６つ、８つ、…のように複数のチップを組
み込むことが可能であり、図４には、１つのパッケージ
内に４つのチップを封入した第４実施例の半導体装置が
示されている。By applying the first embodiment (see FIG. 1) and the second embodiment (see FIG. 2), a plurality of chips such as four, six, eight, ... In one package. FIG. 4 shows a semiconductor device of a fourth embodiment in which four chips are enclosed in one package.

【００２１】図４は、断面図を示し、４つのチップ３
０、３２、３４、３６が１つのパッケージ３８内に封入
されている。ここで、チップ３０、３２の接合及びチッ
プ３４、３６の接合に際しては、裏面３０ｂ、３２ｂが
接合され、且つ、裏面３４ｂ、３６ｂが接合されている
（図１の第１実施例参照）。また、チップ３２、３４の
接合に際してはピンＰ〜Ｐから直接延びたリードＲ〜Ｒ
を間に挟み込んだ状態にて、チップ３２、３４の回路素
子形成面３２ａ、３４ａが接合されている（図２の第２
実施例参照）。なお、ピンＰ〜Ｐには、リードＲ′〜
Ｒ′、Ｒ″〜Ｒ″が接続され、リードＲ′〜Ｒ′は、チ
ップ３０のパッドに接続され、リードＲ″〜Ｒ″は、チ
ップ３６のパッドに接続されている。FIG. 4 shows a cross-sectional view showing four chips 3
0, 32, 34 and 36 are enclosed in one package 38. Here, when the chips 30 and 32 are bonded and the chips 34 and 36 are bonded, the back surfaces 30b and 32b are bonded and the back surfaces 34b and 36b are bonded (see the first embodiment of FIG. 1). Further, when the chips 32 and 34 are joined, the leads R to R extending directly from the pins P to P
The circuit element forming surfaces 32a and 34a of the chips 32 and 34 are bonded to each other with the chip sandwiched therebetween (second part of FIG. 2).
See Examples). It should be noted that the leads R ′ to
R ′ and R ″ to R ″ are connected, leads R ′ to R ′ are connected to pads of the chip 30, and leads R ″ to R ″ are connected to pads of the chip 36.

【００２２】次に、図５には、本発明の第５実施例によ
る半導体装置が示され、（Ａ）は斜視図、（Ｂ）は断面
図である。本第５実施例の半導体装置は、前記図４の第
４実施例の半導体装置を２段に重ねたものである。すな
わち、４つのチップ３０、３２、３４、３６から第１ユ
ニットＵ１を構成し、４つのチップ４０、４２、４４、
４６から第２ユニットＵ２を構成し、両ユニットＵ１、
Ｕ２を１つのパッケージ３８に封入したものである。Next, FIG. 5 shows a semiconductor device according to a fifth embodiment of the present invention, wherein (A) is a perspective view and (B) is a sectional view. The semiconductor device of the fifth embodiment is obtained by stacking the semiconductor device of the fourth embodiment of FIG. 4 in two stages. That is, the four chips 30, 32, 34, 36 form the first unit U1, and the four chips 40, 42, 44,
The second unit U2 is composed of 46, and both units U1,
U2 is enclosed in one package 38.

【００２３】なお、前記第１〜５実施例において、パッ
ドＤとピンＰとの接続は、ボンディング等のリードＲに
よりなされているが、本発明は、これに限られず、他の
手段でパッドＤとピンＰとを接続することが可能であ
る。In the first to fifth embodiments, the connection between the pad D and the pin P is made by the lead R such as bonding, but the present invention is not limited to this, and the pad D can be formed by other means. And pin P can be connected.

【００２４】また、チップ２０、２２に配置されるパッ
ドＤ〜Ｄは、厳密に一直線状である必要はなく、図３の
パッドＤ１１、Ｄ１１′のように、両チップ２０、２２
でパッドＤ１１、Ｄ１１′とピンＰ１１との間の接続状
態（抵抗やインダクタンス等）に差がないもしくは差が
無視できるほど小さい範囲においてならば、パッドＤ〜
Ｄはずれていてもよい。すなわち、パッドＤ〜Ｄは、厳
密に一直線状（図６（Ａ））である必要はなく、図６
（Ｂ）に示されるように、パッドＤ〜Ｄは、中心線ｌか
らある程度ずれていてもよい。Further, the pads D to D arranged on the chips 20 and 22 do not have to be exactly in a straight line, and like the pads D11 and D11 'in FIG.
If there is no difference in the connection state (resistance, inductance, etc.) between the pads D11, D11 'and the pin P11, or if the difference is small enough to be ignored, the pad D ~
D may be offset. That is, the pads D to D do not need to be exactly in a straight line shape (FIG. 6A).
As shown in (B), the pads D to D may be displaced from the center line 1 to some extent.

【００２５】また、前記各実施例においては、チップを
選択する手段として、ＣＳ（チップセレクト）ピンをチ
ップごとに設けているが、チップセレクトピンがなくと
も、本発明は実施可能である。Further, in each of the above embodiments, a CS (chip select) pin is provided for each chip as means for selecting a chip, but the present invention can be implemented without the chip select pin.

【００２６】更に、本発明は、複数のチップを組み込ん
だあらゆる形式の半導体装置に適用可能である。Furthermore, the present invention can be applied to all types of semiconductor devices incorporating a plurality of chips.

【００２７】[0027]

【発明の効果】以上説明したように、本発明によれば、
ミラー反転したチップを使用することなく、同一の回路
配置をもつチップを使用して、複数のチップをパッケー
ジに組み込むことができる。それゆえ、本発明は、半導
体記憶装置のビット容量増加に寄与するところが大き
い。As described above, according to the present invention,
Multiple chips can be incorporated into a package using chips with the same circuit layout without the use of mirror-inverted chips. Therefore, the present invention largely contributes to the increase of the bit capacity of the semiconductor memory device.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１実施例による半導体装置を示し、
（Ａ）は平面図、（Ｂ）は底面図、（Ｃ）は断面図、
（Ｄ）は斜視図である。FIG. 1 shows a semiconductor device according to a first embodiment of the present invention,
(A) is a plan view, (B) is a bottom view, (C) is a sectional view,
(D) is a perspective view.

【図２】本発明の第２実施例による半導体装置を示し、
（Ａ）は断面図、（Ｂ）は斜視図である。FIG. 2 shows a semiconductor device according to a second embodiment of the present invention,
(A) is a cross-sectional view and (B) is a perspective view.

【図３】本発明の第３実施例による半導体装置を示し、
（Ａ）は平面図、（Ｂ）は底面図である。FIG. 3 shows a semiconductor device according to a third embodiment of the present invention,
(A) is a plan view and (B) is a bottom view.

【図４】本発明の第４実施例による半導体装置を示す断
面図である。FIG. 4 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

【図５】本発明の第５実施例による半導体装置を示し、
（Ａ）は斜視図、（Ｂ）は断面図である。FIG. 5 shows a semiconductor device according to a fifth embodiment of the present invention,
(A) is a perspective view and (B) is a sectional view.

【図６】パッドの配置例を示し、（Ａ）はパッドが一直
線状に配置されている状態を示し、（Ｂ）はパッドが中
心線からある程度ずれて配置されている状態を示す。6A and 6B show examples of arrangement of pads, FIG. 6A shows a state in which the pads are arranged in a straight line, and FIG. 6B shows a state in which the pads are arranged with some deviation from the center line.

【図７】従来の半導体装置を示し、（Ａ）は平面図、
（Ｂ）は底面図、（Ｃ）は断面図である。FIG. 7 shows a conventional semiconductor device, (A) is a plan view,
(B) is a bottom view and (C) is a sectional view.

【符号の説明】[Explanation of symbols]

２０、２２…チップ ２４…パッケージ ２６、２８…絶縁膜 Ｐ〜Ｐ…ピン Ｄ〜Ｄ、Ｄ′〜Ｄ′…パッド Ｒ〜Ｒ、Ｒ′〜Ｒ′…リード 20, 22 ... Chip 24 ... Package 26, 28 ... Insulating film P-P ... Pins D-D, D'-D '... Pads R-R, R'-R' ... Lead

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/50 Ｓ 9272−4Ｍ (72)発明者 佐藤 光孝 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Reference number within the agency FI Technical indication location H01L 23/50 S 9272-4M (72) Inventor Mitsutaka Sato 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 複数のチップ（２０、２２）が１つのパ
ッケージ（２４）に封入された半導体装置において、 前記複数のチップ（２０、２２）のそれぞれは、同一の
回路配置であり、その中央にはほぼ１列に配置された複
数のパッド（Ｄ〜Ｄ、Ｄ′〜Ｄ′）を有しており、 前記複数のチップ（２０、２２）のうち一対のチップ
（２０、２２）は、その同一特性面（２０ａ、２２ａ：
２０ｂ、２２ｂ）が互いに接合されていることを特徴と
する半導体装置。1. A semiconductor device in which a plurality of chips (20, 22) are enclosed in one package (24), wherein each of the plurality of chips (20, 22) has the same circuit arrangement and a center thereof. Has a plurality of pads (D to D, D'to D ') arranged in almost one row, and the pair of chips (20, 22) among the plurality of chips (20, 22) are The same characteristic surface (20a, 22a:
20b, 22b) are joined together. 【請求項２】 請求項１記載の装置において、前記複数
のチップ（２０、２２）のうち一対のチップ（２０、２
２）は、その回路素子が形成された面（２０ａ、２２
ａ）の裏面（２０ｂ、２２ｂ）同士が互いに接合されて
いることを特徴とする半導体装置。2. The device according to claim 1, wherein a pair of chips (20, 2) among the plurality of chips (20, 22).
2) is the surface (20a, 22) on which the circuit element is formed.
A semiconductor device in which the back surfaces (20b, 22b) of a) are joined to each other. 【請求項３】 請求項１記載の装置において、前記複数
のチップ（２０、２２）のうち一対のチップ（２０、２
２）は、その回路素子が形成された面（２０ａ、２２
ａ）同士が間にリード（Ｒ〜Ｒ）を挟んで互いに接合さ
れていることを特徴とする半導体装置。3. The device according to claim 1, wherein a pair of chips (20, 2) among the plurality of chips (20, 22).
2) is the surface (20a, 22) on which the circuit element is formed.
A semiconductor device characterized in that a) are bonded to each other with a lead (R to R) interposed therebetween. 【請求項４】 請求項１記載の装置において、前記複数
のチップ（３０、３２、３４、３６）のうち第１の一対
のチップ（３０、３２）は、その回路素子が形成された
面の裏面（３０ｂ、３２ｂ）同士が互いに接合され、前
記複数のチップ（３０、３２、３４、３６）のうち第２
の一対のチップ（３４、３６）は、その回路素子が形成
された面の裏面（３４ｂ、３６ｂ）同士が互いに接合さ
れており、前記第１の一対のチップ（３０、３２）及び
第２の一対のチップ（３４、３６）は、間にリード（Ｒ
〜Ｒ）を挟んで互いに接合されていることを特徴とする
半導体装置。4. The device according to claim 1, wherein the first pair of chips (30, 32) among the plurality of chips (30, 32, 34, 36) are provided on a surface on which the circuit element is formed. The back surfaces (30b, 32b) are bonded to each other, and the second one of the plurality of chips (30, 32, 34, 36) is
Of the first pair of chips (30, 32) and the second pair of chips (34, 36), the back surfaces (34b, 36b) of the surfaces on which the circuit elements are formed are bonded to each other. The pair of chips (34, 36) have a lead (R
To R) are bonded to each other with the semiconductor device interposed therebetween.
JP3238406A 1991-09-18 1991-09-18 Semiconductor device Expired - Fee Related JP2568771B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3238406A JP2568771B2 (en) 1991-09-18 1991-09-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3238406A JP2568771B2 (en) 1991-09-18 1991-09-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0582719A true JPH0582719A (en) 1993-04-02
JP2568771B2 JP2568771B2 (en) 1997-01-08

Family

ID=17029734

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP2568771B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337521B1 (en) 1999-09-22 2002-01-08 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6836007B2 (en) 2002-10-01 2004-12-28 Renesas Technology Corp. Semiconductor package including stacked semiconductor chips

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337521B1 (en) 1999-09-22 2002-01-08 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6576498B2 (en) 1999-09-22 2003-06-10 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6836007B2 (en) 2002-10-01 2004-12-28 Renesas Technology Corp. Semiconductor package including stacked semiconductor chips

Also Published As

Publication number Publication date
JP2568771B2 (en) 1997-01-08

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