JPH0582482A - Via-hole formation method of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a fine via-hole to be etched away by a method wherein a mixed gas or gas plasma capable of negatively charging the surface of an insulator exposed in the plasma is used. CONSTITUTION:A mixed gas or gas plasma capable of negatively charging the surface of the element including an insulator exposed in plasma, e.g. a floating gate oxide film 203 and a gate oxide film 204, is used so as to form a via-hole. As for such a mixed gas, a single element gas of fluorocarbon gas including carbon and fluorine or another mixed gas using multiple kinds of gasses or the other mixed gas containing oxygen, nitrogen or hydrogen gas added thereto is used preferably not to be mixed with an inert gas. Through these procedures, a fine via-hole can be etched away.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming via holes in a semiconductor device, and more particularly to a method for forming fine via holes.

[0002]

2. Description of the Related Art In a conventional via hole forming process of a semiconductor device, a via hole is formed in an interlayer film by using a resist obtained by a lithography process as a mask as shown in FIG. The etching is performed by using a plasma mode in a narrow gap etching apparatus using a mixed gas of an inert gas, in most cases argon.

In the above process, a mixed gas of Ar + CHF ₃ + CF ₄ is generally used. The pressure region used here is in the range of 1 Torr to 0.5 Torr, and as a high frequency power source, 100 kHz to 5 Torr.
00 kHz is used. Input power is 500W
Approximately 800 W is used. By using this gas system under the above etching conditions, the etching rate of the thermal oxide film is 5000 angstrom / m.
In is obtained, and in the pattern up to a diameter of 0.6 μm, a vertical or forward tapered via hole is obtained. At this time, the selection ratio with respect to the resist is about 3 and the selection ratio with respect to the polysilicon is about 15.

[0004]

As described above, by using the plasma mode in the narrow gap etching apparatus using the mixed gas of Ar + CHF ₃ + CF _{4 as} the reactive gas, it is possible to reduce the diameter up to 0.6 μm. Via hole etching is possible.

However, a via hole having a diameter of 0.6 μm or less becomes difficult to etch as the diameter becomes smaller. In general, the phenomenon that the etching rate decreases as the pattern size decreases is known as the microloading effect. This is said to be a phenomenon caused by the disorder of the directionality of the ions, which play a major role in dry etching, particularly in the etching of an oxide film.

In order to suppress the microloading effect and perform etching, it is necessary to perform etching in a low vacuum region in order to suppress collision between ions and neutral radicals as much as possible. For this reason, magnetron reactive ion etching that can obtain high-density plasma even at low pressure is effective. However, with a via hole pattern of 0.6 μm or less, the microloading effect cannot be suppressed only by increasing the degree of vacuum, and there is a problem that etching cannot be performed with a via hole of about 0.4 μm. According to our research, the wafer exposed to the etching plasma is positively charged, and the electric field generated from this electric charge receives repulsive force to the ions incident on the wafer, which inhibits the etching in the fine pattern. It became clear.

[0007]

A method for forming via holes in a semiconductor device according to the present invention uses a mixed gas or gas plasma in which the surface of an insulator exposed to plasma is negatively charged, thereby forming fine via holes. Allows etching.

Preferably, the mixed gas is a single gas of a fluorocarbon gas containing carbon and fluorine, or a mixed gas using a plurality of kinds or a mixed gas obtained by adding a gas containing oxygen, nitrogen or hydrogen to the mixed gas. Fine via holes can be etched by not mixing inert gas.

[0009]

The present invention will be described in detail below.

FIG. 1 is a characteristic diagram showing the effect of the present invention.

FIG. 1 shows a mixed gas of Ar + CHF ₃ + CF ₄ and CHF ₃ + in a magnetron RIE apparatus.
The results of investigating the relationship between the etching depth and the pattern diameter when using a mixed gas of CF ₄ are shown. The sample used at this time was a boron-phosphorus-doped oxide film with a thickness of 1.5 μm formed on a wafer, a resist with a thickness of 1 μm was used, and a via-hole pattern with a diameter of 0.35-1.2 μm was formed. did. Using this as a mask, etching was performed to a depth of 1 μm, and the cross section was observed with a reflection electron microscope to determine the depth. Etching conditions include an etching pressure of 30.
mTorr, an applied magnetic field of 125 gauss on the wafer surface, the frequency of the introduced high frequency was 13.56 MHz, and 700 W of electric power was applied.

Further, the total flow rate of the mixed gas is 200 sccm.
In the case of a mixed gas of Ar + CHF ₃ + CF ₄ ,
Each flow rate is 75, 20, 5 sccm, CH
In the case of a mixed gas of F ₃ + CF ₄ , the respective flow rates were 80 and 20 sccm. The etching rate obtained at this time is 6000 Å / min when Ar is added, and 7,000 Å / min when Ar is not added.

In FIG. 1, an etching depth of 90% or more can be obtained in the range of 0.6 μm to 1.2 μm regardless of whether the mixed gas of Ar + CHF ₃ + CF ₄ or CHF ₃ + CF ₄ is used. However, for diameters less than this,
Differences occur in both gas diameters. Ar + CHF ₃ + CF
_{When 4} is used, the etching depth is drastically reduced below 0.6 μm. On the other hand, when a mixed gas of CHF ₃ + CF ₄ is used, even when the diameter is 0.35 μm,
It can be seen that a depth of 0% or more is secured. Therefore, in order to open a fine via hole, it is more preferable not to add Ar.

The charged state of the wafer exposed to the same gas plasma was investigated for the purpose of investigating the cause of the difference in the etching characteristics of the fine via hole depending on the presence or absence of Ar.
For this research, a non-volatile memory cell composed of a two-layer electrode made of polysilicon as shown in FIG. 2 was used. By exposing this element to plasma, a charge corresponding to the charge charged on the floating gate polysilicon electrode 201 is accumulated in the gate polysilicon electrode 202, and the accumulated charge amount is measured by measuring the flat band voltage later. It can be obtained as a variation value of the flat band voltage. The element used for this measurement is the floating gate oxide film 20.
3 and the gate oxide film 204 have a thickness of 150 Å, and the area of the gate and the area of the floating gate polysilicon electrode are 2.5 × 10 ⁵ μm ² . Ar +
It was found that when exposed to plasma using a mixed gas of CHF ₃ + CF ₄ , the flat band voltage was shifted in the positive direction by about 2 to 5 V, and the surface exposed to plasma was positively charged. On the other hand, when a mixed gas of CHF ₃ + CF ₄ was used, the flat band voltage was slightly shifted in the negative direction, and it was found that the surface exposed to plasma was negatively charged.

From this charging, it is considered that the positive ions, which play a leading role in the etching of the insulating film, receive an electric force. In the fine via hole, the lines of electric force generated from this electric charge become dense as shown in FIG. 4, and it is considered that the above charging has a great influence on the etching of the via hole. A
When positively charged by using a mixed gas of r + CHF ₃ + CF ₄ , positive ions receive repulsive force, and etching is hindered in the fine via hole. On the other hand, CHF ₃ +
When negatively charged with a mixed gas of CF ₄ , positive ions are rather attracted and etching is not hindered.
That is, it has been clarified through this study that a plasma that does not generate positive charging is used in the fine via hole etching.

Next, the outline of another embodiment will be described.

In this embodiment, a case where a CHF ₃ + CO mixed gas is used as a reaction gas will be described.

In this example, a magnetron reactive ion etching apparatus was used. Using a high frequency of 13.56 MHz, applying 700 W of electric power, the magnetic field is
A magnetic field of 150 Gauss was applied on the surface of the wafer. CHF ₃ with a total flow rate of mixed gas of 150 cc / min
Was 50 cc / min and CO was 100 cc / min. Under this condition, the surface exposed to the plasma becomes negatively charged,
Via holes having a diameter of 0.35 μm and a depth of 2 μm could be formed. At this time, the etching rate of the oxide film with boron and phosphorus added is 4000 angstroms / minute, and a selection ratio of 45 to polysilicon is obtained.

[0019]

As described above, according to the present invention, in forming a via hole of a semiconductor device, a fine via hole is formed by using a mixed gas or a gas plasma that negatively charges the surface of an insulator exposed to the plasma. It enables etching. Specifically, as the mixed gas, a single gas of fluorocarbon gas containing carbon and fluorine, a mixed gas using plural kinds or a mixed gas obtained by adding a gas containing oxygen, nitrogen or hydrogen to the mixed gas is used. By not mixing the active gas, the surface of the insulator exposed to the plasma is negatively charged, and the fine via hole can be etched.

[Brief description of drawings]

FIG. 1 Ar + CH in a magnetron RIE device
6 is a graph showing the relationship between etching depth and pattern diameter when a mixed gas of F ₃ + CF _{4 and} a mixed gas of CHF ₃ + CF ₄ is used.

FIG. 2 is a cross-sectional view showing the structure of a nonvolatile memory cell composed of a two-layer electrode of polysilicon used for investigating the charged state of a wafer exposed to gas plasma.

3A to 3C are explanatory diagrams in order of steps of a conventional technique.

FIG. 4 is an explanatory diagram of an effect of charge-up on via hole etching.

[Explanation of symbols]

 201 floating gate polysilicon electrode 202 gate polysilicon electrode 203 floating gate oxide film 204 gate oxide film 301 oxide film 302 resist 401 resist 402 oxide film 403 charge potential 405 ions

Claims (3)

[Claims] 1. Regarding formation of a via hole of a semiconductor device,
A method of forming a via hole in a semiconductor device, characterized in that, in a dry etching process using gas plasma, a mixed gas or gas plasma that negatively charges the surface of an insulator exposed to this plasma is used. 2. The mixed gas in the dry etching is a single gas of fluorocarbon gas containing carbon and fluorine, or a mixed gas using plural kinds or a gas containing oxygen, nitrogen or hydrogen. The method for forming a via hole of a semiconductor device according to claim 1, wherein the added mixed gas is used. 3. The method for forming a via hole in a semiconductor device according to claim 1, wherein an inert gas is not mixed with the mixed gas.