JPH0582454A - Manufacture of semiconductor epitaxial layer - Google Patents

Manufacture of semiconductor epitaxial layer

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Publication number
JPH0582454A
JPH0582454A JP24386591A JP24386591A JPH0582454A JP H0582454 A JPH0582454 A JP H0582454A JP 24386591 A JP24386591 A JP 24386591A JP 24386591 A JP24386591 A JP 24386591A JP H0582454 A JPH0582454 A JP H0582454A
Authority
JP
Japan
Prior art keywords
layer
inp
trap concentration
type
impurity level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP24386591A
Other languages
Japanese (ja)
Inventor
Katsumi Sugiura
勝己 杉浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24386591A priority Critical patent/JPH0582454A/en
Publication of JPH0582454A publication Critical patent/JPH0582454A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To decrease the trap concentration of an impurity level, by growing an InxGa1-xAsyP1-y layer on an InP substrate by an organic metal vapor epitaxial growth method, while the InP substrate temperature is kept higher than or equal to a specified value. CONSTITUTION:By using an MOVPE method and keeping the temperature of a substrate at 610 deg.C, the following are epitaxially grown in order on an n<+>InP substrate 1; a buffer layer 2 composed of n<+>InP, an N-type In0.84Ga0.16 As0.36P0.64 layer 3, and an N-type InP layer 4. The thickness of the N-type In0.84Ga0.16As0.36P0.64 layer 3 and that of the N-type InP layer 4 are 2mum. A p<+>n junction diode is formed by diffusing Zn in the N-type InP layer 4, and the trap concentration of the impurity level Et2 in the N-type In0.84Ga0.16As0.36 P0.64 layer 3 is measured by an ICTS method. Said trap concentration is lower than or equal to 2X10<11>cm<-3> which is the detection limit of an ICTS equipment. That is, the trap concentration can be decreased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は1μm 帯の光通信に使用
される半導体レーザを構成し、InP基板上にエピタキシ
ャル成長して形成するInx Ga1-x Asy 1-y 層の製造方
法に関する。
The present invention relates to a method for manufacturing an In x Ga 1-x As y P 1-y layer which constitutes a semiconductor laser used for optical communication in the 1 μm band and is formed by epitaxial growth on an InP substrate. Regarding

【0002】[0002]

【従来の技術】半導体レーザは発振波長により各種の化
合物半導体が使用されているが、発振波長が1μm 帯の
ものはInPを基板とし、これにInx Ga1-x Asy 1-y
をエピタキシャル成長させ、この層を発振源としてレー
ザが構成されている。すなわち、図2に示すようにn+
- InP基板1の上に有機金属気相エピタキシャル成長法
(MOVPE)法によりn+ - InPよりなるバッファ層
2,Inx Ga1-x Asy 1-y 層3,n- InP層4と順次に
形成した後、亜鉛(Zn)をn-InP層4の中に拡散してp
+ 層5を作り、これによりp+ n接合ダイオードが形成
されている。
2. Description of the Related Art Semiconductor lasers use various compound semiconductors depending on the oscillation wavelength. In the case of an oscillation wavelength of 1 μm band, InP is used as a substrate and an In x Ga 1-x As y P 1-y layer is used. Is epitaxially grown, and a laser is constituted by using this layer as an oscillation source. That is, as shown in FIG. 2 n +
On the InP substrate 1, a n + -InP buffer layer 2, an In x Ga 1-x As y P 1-y layer 3, and an n-InP layer 4 are sequentially formed on the InP substrate 1 by metal organic vapor phase epitaxy (MOVPE). Then, zinc (Zn) is diffused into the n-InP layer 4 to form p.
The + layer 5 is formed so that a p + n junction diode is formed.

【0003】こゝで、エピタキシャル成長したInx Ga
1-x Asy 1-y 半導体層の性質はこの層を構成するAsの
組成比により一義的に決まるもので、この化合物半導体
のエネルギーダイヤグラムは図3のように表すことがで
きる。すなわち、Asの組成をyで表すと、yの値が0の
場合は充満帯8と伝導帯9との間にある禁止帯10のエネ
ルギーギャップは約1.3eVと大きいが、yの値が増すに
従ってエネルギーギャップは次第に1.0eV以下にまで減
少する。また、禁止帯には同図でEt1とEt2で表される
不純物準位が存在している。
In x Ga epitaxially grown here
The properties of the 1-x As y P 1-y semiconductor layer are uniquely determined by the composition ratio of As forming the layer, and the energy diagram of this compound semiconductor can be expressed as shown in FIG. That is, when the composition of As is represented by y, when the value of y is 0, the energy gap of the forbidden band 10 between the filling band 8 and the conduction band 9 is large at about 1.3 eV, but the value of y increases. The energy gap gradually decreases to less than 1.0 eV. Further, impurity levels represented by E t1 and E t2 in the figure exist in the forbidden band.

【0004】こゝで、InPレーザの発光波長は、このレ
ーザ光を伝播する光ファイバの伝送損失を少なくする必
要から1.3 μm または1.55μm の波長帯域が使用される
が、この帯域のレーザ光を発振するためには図3のエネ
ルギーダイヤグラムにおいてyの値が0.03〜0.36の領域
と0.66〜0.98の領域の組成のものが使用されている。
Here, the emission wavelength of the InP laser uses a wavelength band of 1.3 μm or 1.55 μm because it is necessary to reduce the transmission loss of the optical fiber that propagates this laser beam. In order to oscillate, those having a composition in which the y value is in the region of 0.03 to 0.36 and the region of 0.66 to 0.98 in the energy diagram of FIG. 3 are used.

【0005】然し、この組成をとるInx Ga1-x Asy
1-y 半導体層でEt1とEt2で表される不純物準位の何れ
かは同図で1/2 Eg で表したミッドギャップ(Mid-gap)
と交叉しているか、或いは接近していると云う問題があ
る。こゝで、ミッドギャップ付近に存在する不純物準位
はレーザ光の発振動作において、伝導体9にある電子と
充満帯8にある正孔との再結合中心として働き、発光効
率を低下させたり、漏れ電流を増加させるために、不純
物準位のトラップ濃度を少なくすることが必要である。
However, In x Ga 1-x As y P having this composition
In the 1-y semiconductor layer, one of the impurity levels represented by E t1 and E t2 is a mid-gap represented by 1/2 E g in the figure.
There is a problem that it is crossing or approaching. Here, the impurity level existing in the vicinity of the midgap acts as a recombination center between the electron in the conductor 9 and the hole in the filling band 8 in the oscillation operation of the laser beam, and lowers the light emission efficiency. In order to increase the leakage current, it is necessary to reduce the trap concentration of the impurity level.

【0006】然し、ミッドギャップ近傍の不純物準位の
トラップ濃度とInx Ga1-x Asy 1- y 層の成長条件との
関係については今まで充分な研究は行われていない。
However, the relationship between the trap concentration of the impurity level near the midgap and the growth condition of the In x Ga 1-x As y P 1- y layer has not been sufficiently studied so far.

【0007】[0007]

【発明が解決しようとする課題】ミッドギャップ付近に
存在する不純物準位は再結合中心として働き発光効率を
低下させたり、漏れ電流を増加させることが知られてい
る。そのため、この不純物準位のトラップ濃度を減少さ
せることが必要であり、これを実現することが課題であ
る。
It is known that the impurity level existing in the vicinity of the midgap acts as a recombination center to reduce the light emission efficiency and increase the leakage current. Therefore, it is necessary to reduce the trap concentration of this impurity level, and it is a challenge to realize this.

【0008】[0008]

【課題を解決するための手段】上記の課題はInP基板上
に有機金属気相エピタキシャル成長法によりInx Ga1- x
Asy 1-y 層の成長を行う際に、InP基板温度を610 ℃
以上に保持することを特徴として半導体エピタキシャル
層の製造方法を構成することにより解決することができ
る。
[Means for Solving the Problems] The above-mentioned problems are caused by In x Ga 1- x on the InP substrate by metalorganic vapor phase epitaxial growth.
When growing the As y P 1-y layer, the InP substrate temperature was set to 610 ° C.
This can be solved by configuring the method for manufacturing a semiconductor epitaxial layer, which is characterized by holding the above.

【0009】[0009]

【作用】先に図3に示したようにMOVPE法により成
長したInx Ga1-x Asy 1-y 層の中にはEt1とEt2の不
純物準位が存在しており、1.3 μm の発振波長を生ずる
Asの組成が0.03〜0.36の領域においてはy =0.1 の付近
で不純物準位Et2がミッドギャップに交叉している。ま
た、Asの組成が0.66〜0.98の領域においてはy =0.7 の
付近で不純物準位Et1がミッドギャップに交叉してい
る。
In the In x Ga 1-x As y P 1-y layer grown by the MOVPE method as shown in FIG. 3, the impurity levels of E t1 and E t2 are present. produces an oscillation wavelength of μm
In the area of the composition of As is 0.03 to 0.36 impurity level E t2 near the y = 0.1 is cross to the mid-gap. Further, in the region where the composition of As is 0.66 to 0.98, the impurity level E t1 crosses the midgap near y = 0.7.

【0010】こゝで、yの値が0.1 付近および0.7 付近
の組成をとるInx Ga1-x Asy 1-y 層においては勿論、
不純物準位Et2およびEt1が再結合中心として働いてい
るが、これより多少外れた0.03〜0.36および0.66〜0.98
の領域においても再結合中心として働いていると思われ
る。
Here, of course, in the In x Ga 1-x As y P 1-y layer having a composition in which the value of y is around 0.1 and around 0.7,
Impurity levels E t2 and E t1 act as recombination centers, but are slightly deviated from 0.03 to 0.36 and 0.66 to 0.98.
It seems that it also acts as a recombination center in the region of.

【0011】すなわち、前者について言えば、yの値が
0.1 より少なくなるに従って伝導帯にある電子の捕獲量
は増加し、充満帯にある正孔の捕獲量は減少する。また
yの値が0.1 より大きくなるに従って伝導帯にある電子
の捕獲量は減少し、充満帯にある正孔の捕獲量は増加す
るが、この0.03〜0.36の範囲では不純物準位Et2は再結
合中心として働いている。そこで、発光効率を増加させ
るには再結晶中心として働くEt2のトラップ濃度を減少
させることが必要である。
That is, regarding the former, the value of y is
As it becomes less than 0.1, the trapped amount of electrons in the conduction band increases and the trapped amount of holes in the filling band decreases. Further, as the value of y becomes larger than 0.1, the trapped amount of electrons in the conduction band decreases and the trapped amount of holes in the filling band increases, but the impurity level E t2 is reset within the range of 0.03 to 0.36. It works as a bond center. Therefore, in order to increase the luminous efficiency, it is necessary to reduce the trap concentration of E t2 which acts as a recrystallization center.

【0012】発明者はInx Ga1-x Asy 1-y 半導体に存
在する不純物準位のトラップ濃度を減少する方法とし
て、この化合物半導体を構成する5族元素の欠如を補充
することが必要であると考えた。すなわち、この4元化
合物を構成する元素の沸点はInは約2000℃, Gaは2403
℃,Asは613 ℃で昇華(28 気圧),Pは280.5 ℃であり、
5族元素であるAsとPは3族元素であるInやGaに較べる
と遙かに低い。
As a method of reducing the trap concentration of the impurity level existing in the In x Ga 1-x As y P 1-y semiconductor, the inventor can supplement the lack of the group 5 element constituting this compound semiconductor. I thought it was necessary. That is, the boiling points of the elements constituting this quaternary compound are about 2000 ° C. for In and 2403 for Ga.
℃, As sublimate at 613 ℃ (28 atm), P is 280.5 ℃,
The group 5 elements As and P are much lower than the group 3 elements In and Ga.

【0013】そこで、発明者は化合物半導体を構成する
AsとPの欠如の補充がトラップ濃度を減少させる方法と
考えた。すなわち、MOVPE法によるInx Ga1-x Asy
1-y 層の成長過程において、成長層よりAsおよびP成
分が蒸発して欠陥を生じ、これにより不純物準位のトラ
ップ濃度が増加していると考えた。
Therefore, the inventor has constructed a compound semiconductor.
It was considered that supplementation of the lack of As and P would reduce the trap concentration. That is, In x Ga 1-x As y by the MOVPE method
In the growth process of the P 1-y layer, it was considered that As and P components were evaporated from the growth layer to generate defects, which increased the trap concentration of the impurity level.

【0014】通常、Inx Ga1-x Asy 1-y 層やInP層の
エピタキシャル成長に当たってはAsおよびP成分の蒸発
を防ぐ観点から、基板温度を600 ℃以下の温度例えば57
0 ℃に保って成長が行われている。然し、発明者はMO
VPE法でInx Ga1-x Asy 1-y 層を形成する場合は逆
に基板温度を高めて行うほうが、ソースガスの分解を促
進しエピタキシャル成長領域が過飽和となることにより
AsおよびP成分の蒸発を防げるのではないかと考え、In
0.84Ga0.16As0.360.64の組成を選び、基板温度を変え
てMOVPE法により化合物半導体層を形成しICTS
(Isothermal Capacitance Transient Spectroscopy)法
により不純物準位Et2のトラップ濃度を測定した。
Usually, in the epitaxial growth of the In x Ga 1-x As y P 1-y layer and the InP layer, from the viewpoint of preventing the evaporation of As and P components, the substrate temperature is 600 ° C. or less, for example 57
Growth is carried out at 0 ° C. However, the inventor is MO
On the contrary, when the In x Ga 1-x As y P 1-y layer is formed by the VPE method, it is better to increase the substrate temperature because the decomposition of the source gas is accelerated and the epitaxial growth region becomes oversaturated.
We thought it might prevent the evaporation of As and P components,
The composition of 0.84 Ga 0.16 As 0.36 P 0.64 is selected, the compound semiconductor layer is formed by the MOVPE method while changing the substrate temperature, and the ICTS
The trap concentration of the impurity level E t2 was measured by the (Isothermal Capacitance Transient Spectroscopy) method.

【0015】図1はこの結果であって、基板温度を570
℃に保ってエピタキシャル成長させた化合物半導体層で
不純物準位Et2のトラップ濃度は6.2 ×1013cm-3である
のに対し、基板温度を615 ℃としてエピタキシャル成長
させた場合のトラップ濃度は検出限界である2×1011cm
-3以下であり、基板温度を650 ℃とする場合も変わらな
かった。このことは発明者の予測が正しいことを意味す
る。そこで、本発明は基板温度を610 ℃以上の温度に保
ってMOVPEを行うことにより不純物準位のトラップ
濃度を少なくし、これにより半導体レーザの発光効率を
高め、また電力消費を少なくするものである。
FIG. 1 shows the result, and the substrate temperature is 570
° C. trap concentration impurity level E t2 compound semiconductor layer epitaxially grown while maintaining the contrast is 6.2 × 10 13 cm -3, the trap concentration when epitaxially grown at a substrate temperature of 615 ° C. at a detection limit Yes 2 × 10 11 cm
It was -3 or less, and did not change even when the substrate temperature was 650 ° C. This means that the inventor's prediction is correct. Therefore, the present invention reduces the trap concentration of the impurity level by carrying out MOVPE while keeping the substrate temperature at 610 ° C. or higher, thereby improving the emission efficiency of the semiconductor laser and reducing the power consumption. ..

【0016】[0016]

【実施例】図2に示すようにn+ InP基板1の上にMO
VPE法を用い、基板温度を610℃としてn+ InPより
なるバッファ層2,n-In0.84Ga0.16As0.360.64
3,n- InP層4と順次にエピタキシャル成長させた。
こゝで、n-In0.84Ga0.16As0.360.64層3とn- InP
層4の厚さはそれぞれ2μm である。次に、Znをn- In
P層4の中に拡散させてp+ n接合ダイオードを形成
し、ICTS法によりn-In0.84Ga0.16As0.360.64
3の中の不純物準位Et2のトラップ濃度を測定した結
果、ICTS装置の検出限界である2×1011cm-3以下で
あった。
EXAMPLE As shown in FIG. 2, MO was formed on the n + InP substrate 1.
Using the VPE method, the substrate temperature was set to 610 ° C., and a buffer layer made of n + InP 2, an n-In 0.84 Ga 0.16 As 0.36 P 0.64 layer 3, and an n-InP layer 4 were sequentially epitaxially grown.
Here, n-In 0.84 Ga 0.16 As 0.36 P 0.64 Layer 3 and n-InP
The thickness of each layer 4 is 2 μm. Next, Zn is changed to n-In
As a result of measuring the trap concentration of the impurity level E t2 in the n-In 0.84 Ga 0.16 As 0.36 P 0.64 layer 3 by diffusing in the P layer 4 to form a p + n junction diode, the ICTS method was used. The detection limit of the device was 2 × 10 11 cm −3 or less.

【0017】一方、従来のように基板温度を570 ℃とし
てp+ n接合ダイオードを形成したものについてICT
S法により測定したn-In0.84Ga0.16As0.360.64層3
の中の不純物準位Et2のトラップ濃度は6×1013cm-3
あり、これに較べて2桁以上低減することができた。
On the other hand, as in the conventional case, the substrate temperature is 570 ° C. and the p + n junction diode is formed in the ICT.
N-In 0.84 Ga 0.16 As 0.36 P 0.64 layer 3 measured by S method
The trap concentration of the impurity level E t2 in the above was 6 × 10 13 cm −3 , and it was possible to reduce the trap concentration by two digits or more as compared with this.

【0018】[0018]

【発明の効果】本発明の実施によりInx Ga1-x Asy
1-y エピタキシャル層の成長に当たって不純物準位のト
ラップ濃度を減らすことができ、これにより半導体レー
ザの発光効率が向上すると共に電力消費を少なくするこ
とができ、従って半導体レーザの寿命を延長することが
可能となった。
INDUSTRIAL APPLICABILITY By implementing the present invention, In x Ga 1-x As y P
It is possible to reduce the trap concentration of the impurity level during the growth of the 1-y epitaxial layer, which improves the emission efficiency of the semiconductor laser and reduces the power consumption, thus extending the life of the semiconductor laser. It has become possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】n-In0.84Ga0.16As0.360.64層の成長温度と
トラップ濃度の関係図である。
FIG. 1 is a relationship diagram between a growth temperature and a trap concentration of an n-In 0.84 Ga 0.16 As 0.36 P 0.64 layer.

【図2】半導体レーザの構成を示す模式図である。FIG. 2 is a schematic diagram showing a configuration of a semiconductor laser.

【図3】Inx Ga1-x Asy 1-y 化合物半導体層のエネル
ギーダイアグラムである。
FIG. 3 is an energy diagram of an In x Ga 1-x As y P 1-y compound semiconductor layer.

【符号の説明】[Explanation of symbols]

1 n+ InP基板 3 n-Inx Ga1-x Asy 1-y 層 4 n- InP層1 n + InP substrate 3 n-In x Ga 1-x As y P 1-y layer 4 n- InP layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 InP基板上に有機金属気相エピタキシャ
ル成長法によりInx Ga1-x Asy 1-y 層の成長を行う際
に、該InP基板温度を610 ℃以上に保持して行うことを
特徴とする半導体エピタキシャル層の製造方法。
1. When the In x Ga 1-x As y P 1-y layer is grown on the InP substrate by the metalorganic vapor phase epitaxial growth method, the InP substrate temperature is kept at 610 ° C. or higher. A method for manufacturing a semiconductor epitaxial layer, comprising:
JP24386591A 1991-09-25 1991-09-25 Manufacture of semiconductor epitaxial layer Withdrawn JPH0582454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24386591A JPH0582454A (en) 1991-09-25 1991-09-25 Manufacture of semiconductor epitaxial layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24386591A JPH0582454A (en) 1991-09-25 1991-09-25 Manufacture of semiconductor epitaxial layer

Publications (1)

Publication Number Publication Date
JPH0582454A true JPH0582454A (en) 1993-04-02

Family

ID=17110129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24386591A Withdrawn JPH0582454A (en) 1991-09-25 1991-09-25 Manufacture of semiconductor epitaxial layer

Country Status (1)

Country Link
JP (1) JPH0582454A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8870676B2 (en) 2010-12-27 2014-10-28 Sri Sports Limited Golf club

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8870676B2 (en) 2010-12-27 2014-10-28 Sri Sports Limited Golf club

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