JPH0581887A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To exactly measure cell condition after erasing information by providing a memory cell array, a raw decoder and a sense circuit and providing a voltage switching means and a load switching means. CONSTITUTION:At the time of detecting the cell condition, the output voltage of the raw decoder 20 is switched by the voltage switching means 1. Thus, the gate voltage of the selected cell transistor of a cell matrix 40 is changed and the cell condition is decided by the read result of the sense circuit 30 at this time. At this time, when the voltage switched by the voltage switching means 1 is unstable like at the time of detecting the cell condition after erasing the information, load ability in the sense circuit 30 is made larger effectively than at the time of normal operation by the load switching means 2 and decided by changing a sense current from read out condition at the time of the normal operation. Thus, the cell condition after erasing the information is measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an electrically writable semiconductor memory device having a cell state detection circuit.

In recent years, electrically writable semiconductor memory devices such as EPROMs (Erasable and Programmable Res
ad Only Memory), EEPROM (Electrically Erasa)
bleand Programmable Read Only Memory), flash EEPROM, etc. are widely used for program / data storage in microcomputer systems. Since these semiconductor memory devices store information depending on the amount of charge stored in the memory cell, it is desirable to accurately measure the amount of charge written during programming in order to develop a highly reliable element. In addition, it is desirable to be able to measure the charge amount after writing in order to improve the reliability of the system.

Further, in recent highly integrated semiconductor memory devices,
Since cell miniaturization is progressing, cell transistors are sensitive to process variations and various pollutions, and it is important to measure not only the cell state after writing but also the cell state after erasing in detail. Is becoming

[0004]

2. Description of the Related Art A conventional EPROM according to FIGS.
The cell state detection in will be described.

FIG. 5 shows a schematic diagram of a cell in an EPROM and its peripheral circuit. In the figure, 20 is a row decoder circuit, 30 is a sense circuit, 40 is a cell matrix in which cells for storing information are arranged, and 50 is a column gate circuit. In the column gate circuit 50, TYO to TYN are column gate transistors, and in the cell matrix 40, T00 to TMN are cell transistors, all of which are N channel transistors. Row decoder circuit 20
Outputs X0 to XM are connected to the gates of the cell transistors T00 to TMN, and the outputs of a column decoder circuit (not shown) are connected to the gates Y0 to YN of the column gate transistors.

In the above structure, the row decoder inputs (X0 ...
XM) and a bit line (one of B0 to BN) selected by the output of the column decoder (one of Y0 to YN) selected by a column address input circuit (not shown).
The current flowing through the cell (one of T00 to TMN) at the intersection of is detected by the sense circuit 30 and output as cell information by the output circuit (not shown).

FIG. 6 shows a conceptual diagram of the cell structure of the EPROM. The cell is a double polysilicon gate transistor, and as shown in the figure, the upper gate (control gate, hereinafter referred to as “CG”) 100 is connected to the output of the row decoder circuit 20. The lower gate (floating gate, hereinafter referred to as “FG”) 110 is electrically insulated from other circuits and operates as a charge storage layer. CG1
When Vcc (5V) is applied to 00, the FG 110 outputs C
The potential increases due to the capacitance formed between G100 and
State in which electric charge is not accumulated in FG110 (erased state)
Then, it becomes about 3V. In the state where charges are accumulated in the FG 110 (write state), the potential of the FG 110 is determined according to the amount of accumulated charges, and the more the charges (electrons) are, the lower the potential of the FG 110 is.

FIG. 7 shows the relationship between the gate potential and cell current of the EPROM cell. In the figure, (1) is F
The relationship between the G110 potential and the cell current is shown in (2) and (3).
Shows the relationship between the potential of CG100 and the cell current.
(2) shows the case where the charge accumulated in the FG 110 is small,
(3) shows a case where a large amount of charge is accumulated in the FG 110. Since the current flowing through the cell transistor is determined by the potential of the FG 110, the relationship between the potential of the FG 110 and the cell current does not depend on the amount of charge accumulated in the FG 110. On the other hand, regarding the relationship between the potential of the CG100 and the cell current, the potential of the FG110 with respect to the same CG100 potential depends on the amount of charge accumulated in the FG110. The cell current is greater than the cell current when there is more.

When the cell current is larger than the sense current determined by the sense circuit 30, the sense circuit 30 determines that the cell is in the erased state, and when the cell current is small, the cell is in the written state. Therefore, in the normal operation state, only the result of comparison between the cell current and the sense current is output, and the detailed state of the cell is unknown. In order to know the detailed state of the cell, it is necessary to change the cell current by changing the potential of the CG 100 and obtain the potential of the CG 100 at which the output changes (the potential of the CG at which the cell current matches the sense current).

In the circuit shown in FIG. 5, the potential of the CG 100 (outputs X0 to XM of the row decoder circuit 20) is determined by the power supply VCC of the row decoder circuit 20. C
When the potential of Vcc is changed to change the potential of G100, since Vcc is also input to the sense circuit 30 at the same time, changing Vcc also changes the characteristics (sense current) of the sense circuit 30. , Vcc change (ΔVC
There is a drawback that the potential change (ΔVCG) of the CG 100 for flowing the same cell current as C) is not necessarily the same.

FIG. 8 is a schematic diagram of an EPROM provided with a cell state detecting circuit for improving the above drawbacks. In the figure, the same components as those shown in FIG. 5 are designated by the same reference numerals, and the description thereof is incorporated. In the configuration shown in FIG.
3 is different from that of FIG. 1 in that a circuit shown by a dotted line is newly added, and a circuit 10 shown by a dotted line is a power supply switching circuit of the row decoder circuit 20. The power supply switching circuit 10 forms a cell state detection circuit, and T0 and T1 are N
The channel depletion transistor is configured as a power supply switching transistor.

The operation of detecting the cell state in FIG. 8 will be described below. In the power supply switching circuit 10, during normal operation, the gate signal R of the power supply switching transistor T0 is "H" and the gate signal M of the power supply switching transistor T1.
Is set to "L", and as a result, the internal power supply (VINT) of the row decoder circuit 20 becomes VCC. The cell read operation in this case is the same as that in the case of the circuit shown in FIG. On the other hand, when the cell state is detected, the gate signal R of the power source switching transistor T0 is set to "L" and the gate signal M of the power source switching transistor T1 is set to "H". As a result, the internal power source of the row decoder circuit 20 ( VIN
T) becomes VPP, and the "H" level of the row decoder circuit 20 becomes VPP.

With the above structure, the voltage applied to the gate (CG) of the cell and the power supply voltage V of the sense circuit 30.
It can be changed independently of CC. Therefore, the power supply switching circuit 1 with the power supply voltage Vcc kept constant.
Change the voltage of the power supply VPP supplied to
If the point where the output of 0 changes is calculated, the change of VPP (ΔVP
Since P) and the change in CG100 potential (ΔVCG) are the same, accurate cell state detection was possible.

[0014]

However, in the conventional cell state detecting circuit shown in FIG. 8, since the N-channel depletion transistor is used for the power supply switching transistor, the power supply switching circuit 10 is supplied. If the VPP voltage generated is higher than the VCC voltage, VINT becomes VPP correctly, but if the VPP voltage is lower than the VCC voltage,
More precisely, when the threshold voltage of the power switching transistor T0 is Vth0 (Vth0> 0), VINT is -V.
When the voltage becomes th0 or less, the power supply switching transistor T0 becomes conductive and a current flows from VINT to VCC, so that VIN
There was a problem that the value of T was not determined correctly.

Therefore, the conventional circuit shown in FIG. 8 has a drawback in that the state of the written cell can be measured correctly, but the state of the cell after erasure cannot be measured correctly.

In view of the above points, it is an object of the present invention to provide a conductor memory device capable of correctly measuring the cell state after erasing in cell state detection.

[0017]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, the same parts as those in FIGS. 5 and 8 are designated by the same reference numerals, and the description thereof is incorporated.

As shown in FIG. 1, a means of the present invention for achieving the above object is to provide a cell matrix 40, which is a memory cell array in which a plurality of cells including cell transistors for storing information are arranged, and a cell transistor. What is claimed is: 1. A rewritable semiconductor memory device, comprising: a row decoder 20 for selecting a gate; and a sense circuit 30 for determining information stored by detecting a current flowing through the cell transistor. A voltage switching unit 1 for switching the output voltage of the row decoder 20 and a load switching unit 2 for effectively switching the load capability of the sense circuit 30 at the time of detecting the cell state are configured.

[0019]

According to the present invention, when the cell state after erasing is detected, the sense current of the sense circuit is set to be, for example, larger than that in the normal read state to solve the problem. That is, when the cell state is detected, the output voltage of the row decoder 20 is switched by the voltage switching means 1, whereby the gate voltage of the selected cell transistor of the cell matrix 40 is changed, and the cell read is read by the sense circuit 30 at that time. The state is determined. At this time, when the voltage switched by the voltage switching means 1 becomes unstable like when detecting the cell state after erasing information, the load switching means 2 causes the load capacity in the sense circuit 30 to be higher than that in the normal operation. Effectively, for example, increase. That is, the determination is performed by changing the sense current from the read state in the normal operation. As a result, it becomes possible to measure the cell state after erasing information.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 2 shows a schematic diagram of an EPROM according to the first embodiment of the present invention.

In the figure, the same parts as those in FIGS. 5 and 8 are designated by the same reference numerals, and the description thereof is incorporated. In this embodiment, as shown in FIG.
A power supply switching circuit 10 having the same configuration as that shown in FIG. 8 is configured, and a load transistor T2 is added to the sense circuit 30 as load switching means. The load transistor T2 conducts during the cell state detection operation in the erased state, and increases the sense current more than in the normal state.

The operation of the circuit shown in FIG. 2 will be described below. In the power supply switching circuit 10, the gate signal R is set to "H" and the gate signal M is set to "L" during normal operation, and as a result,
The internal power supply (VINT) of the row decoder circuit 20 is set to VCC. Also, the gate signal M'of the load transistor T2
Is also set to "L" level, and load transistor T2
Is non-conductive, the sense current of the sense circuit 30 is in the optimum state in the normal operation, which is determined by the state after the cell is erased and the state after the cell is written.

At the time of detecting the cell state after writing the information, in the power supply switching circuit 10, the gate signal R is set to "L" and the gate signal M is set to "H". As a result, the internal power supply of the row decoder circuit 20 ( VINT) becomes VPP,
The "H" level of the row decoder circuit 20 is set to VPP.
At this time, the gate signal M'of the load transistor T2 is likewise set to "L". Cell state detection in this state is the same as the operation described in FIG. At this time, even if the gate signal M ′ is “H”, the sense circuit 3
Since the sense current of 0 increases, the value of VPP required to change the output becomes higher than that when the gate signal M ′ is “L”, but the difference between the VPP voltage (ΔVPP) and the CG voltage difference. (ΔVCG) is the same and there is no essential difference.

At the time of detecting the cell state after erasing the information, the power supply switching circuit 10 similarly sets the gate signal R to "L" and the gate signal M to "H", and as a result, the internal power supply of the row decoder circuit 20. (VINT) becomes VPP,
The "H" level of the row decoder circuit 20 is set to VPP.
At this time, the gate signal M'of the load transistor T2 is set to "H". As a result, the load transistor T2
Is conducted, the sense current of the sense circuit 30 increases, so that the output changes only at the CG voltage (VPP) at which the cell current has a large value corresponding to the sense current. That is,
The state of the cell after erasing can be detected with a relatively high voltage applied to VPP.

FIG. 3 is a detailed block diagram of the first embodiment. In the figure, the same parts as those in FIGS. 2, 5 and 8 are designated by the same reference numerals, and the description thereof is incorporated. As shown in FIG. 3, the sense circuit 30 includes a load transistor T3 used during normal operation and a detection circuit 35 for detecting the state of the cell. The detection circuit 35 detects the state of the cell from the level of the data bus line BUS. The current of the load transistor T3 that gives the level of the data bus line BUS that changes the output of the detection circuit 35 is the sense current.

When detecting the state of the cell after erasing the information, the load transistor T2 provided as load switching means becomes conductive, so that the load of the sense circuit 30 is a combination of the load transistor T2 and the load transistor T3. Becomes Therefore, in order to bring the data bus line BUS to a level that changes the output of the detection circuit 35,
A large cell current is required, and the CG voltage requires a higher level than in normal operation.

Second Embodiment FIG. 4 shows a block diagram of an EPROM according to a second embodiment of the present invention. 4, the same parts as those of the first embodiment shown in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, as shown in FIG. 4, a reference cell TRX is provided in addition to the memory cell array 40 for storing information, and a column gate transistor TRY and a load transistor T4 are connected to the reference cell TRX. .. In this circuit, the column gate transistor TRY is composed of the column gate transistors TY0 to TYN of the column gate circuit 50 and the reference cell TRX.
Are cell transistors T00 to TMN of the cell matrix 40.
Same dimension as, but load transistor T
4 has approximately twice the dimension of the load transistor T3. Further, the reference cell TRX always operates in the erased state.

In the EPROM of the present embodiment having the above-mentioned structure, in reading information, the cell state is not read by the level of one data bus line, but the level of the data bus line DBUS and the level of the reference bus line RBUS are read. The cell state is read out by comparison. That is, when reading a cell in the erased state,
The current flowing through the information storage cells (T00 to TMN) of the cell matrix 40 and the current flowing through the reference cell TRX are substantially the same, but the levels of the data bus line DBUS are different because the capacities of the load transistors T3 and T4 are different. It becomes lower than the level of the bus line RBUS. This is detected by the detection circuit 36 to determine the erased state. Also, when reading a cell in the written state,
Since the electric charge is accumulated in the floating gate of the cell, the current flowing through the information storing cell (T00 to TMN) becomes considerably smaller than the current flowing through the reference cell TRX.
The level of the data bus line DBUS is the reference bus line R
It will be higher than the BUS level. This is detected to recognize the writing state.

In this embodiment, when the cell state after erasing information is detected, the gate signal R of the power supply switching circuit 10 is set to "L" and the gate signal M is set to "H", whereby the row decoder circuit is set. The internal power supply (VINT) of 20 becomes VPP, and the "H" level of the row decoder circuit 20 is made VPP. At the same time, the gate signal M of the load transistor T2
′ Is set to “H”, and the load transistor T2 is made conductive. As a result, the capacity of the load transistor is effectively increased, and a higher CG voltage (VPP voltage) is required to make the level of the data bus line DBUS lower than the level of the reference bus line RBUS. Therefore, C
When the G voltage is high, the cell state after erasing can be detected.

In the second embodiment, the load connected to the information storage cells of the cell matrix 40 is increased when the cell state after erasing information is detected.
Similar effects reduce (1) the capacity of the load transistor T4 connected to the reference cell TRX.
(2) It is also realized by effectively increasing the capacity of the reference cell TRX.

For example, in the case of the above (1), as a load switching means for reducing the load capacity of the load transistor T4 instead of the load transistor T2, as shown in FIG.
This is achieved by providing a load transistor T5 connected in parallel with the load transistor T4, as indicated by the dotted line in FIG. In this case, the gate signal R1 of the load transistor T5 is set to "H" level during normal operation, and is set to "L" level when the cell state after erasing information is detected, so that the load capability of the load transistor T4 is higher than that during normal operation. Also effectively decreases. In the case of the above (2), as reference switching means for effectively increasing the capacity of the reference cell TRX instead of the load transistor T2, it is connected in parallel with the reference cell TRX as shown by the dotted line in FIG. This is achieved by providing a reference transistor T6 which is In this case, the gate signal R2 of the reference transistor T6 is set to "L" level during normal operation, and set to "H" level when the cell state after erasing information is detected.
Abilities increase effectively more than normal.

[0032]

As described above, according to the semiconductor memory device of the present invention, not only the written cell but also the erased cell can be measured in detail. It largely contributes to improving the reliability of a system using a writable semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a schematic diagram of an EPROM according to the first embodiment of the present invention.

FIG. 3 is a detailed configuration diagram of the first embodiment.

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is a schematic diagram of a cell and its peripheral circuits in an EPROM.

FIG. 6 is a conceptual diagram of a cell structure of EPROM.

FIG. 7 is a relationship diagram between a gate voltage and a cell current.

FIG. 8 is a schematic diagram of an EPROM including a conventional cell state detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Voltage switching means 2 ... Load switching means 10 ... Power supply switching circuit 20 ... Row decoder circuit 30 ... Sense circuit 35, 36 ... Detection circuit 40 ... Cell matrix 50 ... Column gate circuit T2, T3, T4, T5 ... Load transistor T6 … Reference transistor TRX… Reference cell TRY… Column gate transistor DBUS… Data bus line RBUS… Reference bus line

Claims (5)

[Claims] 1. A memory cell array (40) in which a plurality of cells including cell transistors for storing information are arranged, and a row decoder (2) for selecting a gate of the cell transistor.
0), and a sense circuit (30) for determining the stored information by detecting the current flowing through the cell transistor,
A rewritable semiconductor memory device having: a voltage switching means (1) for switching an output voltage of the row decoder (20) at the time of detecting a cell state, and a sense circuit (30) in the sense circuit (30) at the time of detecting a cell state. A semiconductor memory device comprising: load switching means (2) for effectively switching load capacity. 2. A memory cell array (40) in which a plurality of cells including cell transistors for storing information are arranged, and a row decoder (2) for selecting a gate of the cell transistor.
0), and a sense circuit (30) for determining the stored information by detecting the current flowing through the cell transistor,
A rewritable semiconductor memory device having: a voltage switching means (1) for switching an output voltage of the row decoder (20) at the time of detecting a cell state, and a sense circuit (30) in the sense circuit (30) at the time of detecting a cell state. A semiconductor memory device, comprising: load switching means (T2) for switching the load capacity for the cell transistor so as to be effectively larger than in a normal state. 3. A memory cell array (40) having a plurality of cells including a cell transistor for storing information, and a row decoder (2) for selecting a gate of the cell transistor.
0), a reference cell (TRX) used at the time of reading information, a current flowing through the cell transistor and a current flowing through the reference cell (TRX) are compared to determine a stored information circuit (30) When,
A rewritable semiconductor memory device having: a voltage switching means (1) for switching an output voltage of the row decoder (20) at the time of detecting a cell state, and a sense circuit (30) in the sense circuit (30) at the time of detecting a cell state. A semiconductor memory device, comprising: load switching means (T2) for switching the load capacity for the cell transistor so as to be effectively larger than in a normal state. 4. A memory cell array (40) having a plurality of cells including a cell transistor for storing information, and a row decoder (2) for selecting a gate of the cell transistor.
0), a reference cell (TRX) used at the time of reading information, a current flowing through the cell transistor and a current flowing through the reference cell (TRX) are compared to determine a stored information circuit (30) When,
A rewritable semiconductor memory device having: a voltage switching means (1) for switching an output voltage of the row decoder (20) at the time of detecting a cell state, and a sense circuit (30) in the sense circuit (30) at the time of detecting a cell state. A semiconductor memory device, comprising: load switching means (T5) for switching the load capacity for the reference cell (TRX) so as to be effectively smaller than that during normal operation. 5. A memory cell array (40) having a plurality of cells including a cell transistor for storing information, and a row decoder (2) for selecting a gate of the cell transistor.
0), a reference cell (TRX) used at the time of reading information, a current flowing through the cell transistor and a current flowing through the reference cell (TRX) are compared to determine a stored information circuit (30) When,
A rewritable semiconductor memory device having: a voltage switching means (1) for switching an output voltage of the row decoder (20) at the time of detecting a cell state; and a reference cell (TR
A semiconductor memory device, comprising: a reference switching means (T6) for switching so that the capability of (X) is effectively increased compared to the normal operation.