JPH0581873A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a device improving the level margin of an ECL output signal by separating a voltage supplying line of the high level side of a differential transistor circuit from the voltage supplying line of other internal circuit. CONSTITUTION:An emitter-follower output transistor T3 is driven by differential transistors T1, T2 circuit forming the output signal corresponding to an ECL level by receiving an internal signal to output. The voltage supplying line L1 of the high level side of the differential transistors T1, T2 circuit is arranged so as to be separated from the voltage supplying line L2 of other internal circuit LOG forming the internal signal to output. Thus, since an operational current is dispersed by separating the voltage supplying lines, a voltage drop generated in the circuit is reduced and the high level margin of the output signal is increased in accordance with this matter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when used for an input / output interface having ECL compatibility.

[0002]

2. Description of the Related Art Bi as a high-speed static RAM
There is a CMOS circuit technology in which the memory array section is configured as a CMOS circuit and the peripheral circuit is an ECL compatible BiCMOS circuit. As such a static RAM, "VLSI Circuit Symposium Proceedings" page 44
(1990 Symposiumon VLSI Circuits P.44).

[0003]

In a semiconductor integrated circuit device having an ECL interface, an ECL level signal to be output formed by an internal circuit LOG as shown in FIG. 4 is driven by differential transistors T1 and T2. It is output through an emitter follower output transistor T3 driven by the stage. In this case, the operating voltage of the internal circuit LOG as described above and the operating voltage line of the differential transistor circuit forming the driving stage are supplied by the same wiring L. In the present inventor, since the operating current of the internal circuit LOG and the differential transistor circuit of the driving stage flows through the distributed resistance r of the power supply line L, a relatively large DC voltage drop occurs and the voltage is output from the external terminal. I have noticed that the high level (V _OH ) lower limit margin in the output signal is reduced. An object of the present invention is to provide a semiconductor integrated circuit device in which the level margin of the ECL output signal is improved. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the emitter follower output transistor is driven by a differential transistor circuit that receives an internal signal to be output and forms an output signal corresponding to the ECL level, and the high-level side voltage supply line of the differential transistor circuit is output as described above. It is arranged separately from the voltage supply lines of other internal circuits that form the internal signals to be generated.

[0005]

According to the above-mentioned means, since the operating current is dispersed by the separation of the power supply lines, the voltage drop generated there can be reduced, and the high level margin of the output signal can be increased accordingly.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows a concrete circuit diagram of one embodiment of a memory array portion of a static RAM and its peripheral circuit to which the present invention is applied. Each circuit element in the figure is
Known CMOS technology or bipolar transistor and C
It is formed on a single semiconductor substrate such as single crystal silicon by Bi-CMOS technology combined with a MOS circuit. In the figure, a P channel type M
OSFET is its channel part (back gate part)
N-channel MOS by adding an arrow to the
It is distinguished from the FET. Static type RA of this embodiment
The M input / output interface is made compatible with the ECL circuit. Therefore, the negative power supply voltage VEE is used with respect to the ground potential of the circuit.

In the memory array, two memory cells connected to complementary data lines D0 and D0B are shown as a representative. Each of the memory cells MC has the same configuration as each other, and as its one specific circuit is representatively shown, the gate and the drain are cross-connected to each other and the source is coupled to the negative power supply voltage VEE. N-channel type storage MOSFETs Q1 and Q2 and the above MOSFET
High resistances R1 and R made of a poly (polycrystalline) silicon layer provided between the drains of Q1 and Q2 and the ground potential of the circuit
Includes 2 and. N-channel type transmission gate MOSFETs Q3 and Q4 are provided between the common connection point of the MOSFETs Q1 and Q2 and the complementary data lines D0 and D0B. Transmission gates MO of memory cells arranged in the same row
The gates of the SFETs Q3, Q4, etc. are commonly connected to corresponding corresponding word lines W0, Wn, etc., and the input / output terminals of the memory cells arranged in the same column are exemplarily shown as the above representative. Connected to a pair of complementary data lines (also referred to as complementary bit lines or complementary digit lines) D0 and D0B.

In the memory cell MC, the MOSFET Q
1, Q2 and resistors R1, R2 form a kind of flip-flop circuit, but the operating point in the information holding state is quite different from that of the flip-flop circuit in the ordinary sense. That is, in order to reduce the power consumption of the memory cell MC, the resistance R1 of the memory cell MC is
MOSFETQ when ETQ1 is turned off
It has a remarkably high resistance value such that the gate voltage of 2 can be maintained at a voltage slightly higher than its threshold voltage. Similarly, the resistance R2 is also set to a high resistance value. In other words, the resistors R1 and R2 are made high enough to compensate the drain leak currents of the MOSFETs Q1 and Q2. The resistors R1 and R2 have a current supply capability that prevents the information charges accumulated in the gate capacitance (not shown) of the MOSFET Q2 from being discharged.

According to this embodiment, the memory cell MC is an N-channel MOS as described above, even though the RAM is manufactured by the CMOS-IC technique in the memory section.
It is composed of a FET and a polysilicon resistance element. As a memory cell of the static RAM, a P-channel MOSFET can be used instead of the polysilicon resistance element. The memory cell MC is a P channel MO
The size can be reduced as compared with the case of using the SFET. That is, when a polysilicon resistor is used, the driving M
It can be formed on the gate electrode of the OSFET Q1 or Q2, and the size of itself can be reduced. And P
Drive M as when using a channel MOSFET
Since it is not necessary to separate the OSFETs Q1 and Q2 with a relatively large distance, there is no useless blank portion.

In the figure, although not particularly limited, between the complementary data lines D0 and D0B and the ground potential of the circuit,
P-channel type load MOSFETs Q9 and Q10, which act as resistance elements when the power supply voltage VEE is constantly supplied to their gates, are provided. These load MOSFETs Q9 and Q10 are formed to have a relatively small size so that they have a small conductance. These load MOSFETs Q9, Q1
0 is the load MO of P-channel type in parallel form.
SFETs Q11 and Q12 are provided. These loads M
The OSFETs Q11 and Q12 are formed to have a relatively large size so that they have a relatively large conductance. The MOSFETs Q9 to Q12
Conductance and memory cell M in the ON state
The ratio of the combined conductance of the transmission gate MOSFET and the storage MOSFET of C is such that in the read operation of the memory cell MC, the complementary data lines D0 and D0B are
The value is selected so as to have a desired potential difference according to the stored information. An internal write signal WE, which is set to a high level such as the ground potential of the circuit during the write operation, is supplied to the gates of the load MOSFETs Q11 and Q12.
As a result, during the write operation, the load MOSFET
TQ11 and Q12 are turned off. Therefore, the load means of the complementary data line in the write operation is only the MOSFETs Q9 and Q10 having the small conductance.

In this embodiment, although not particularly limited, in order to make the signal amplitude of the read signal of the memory cell read through the column switch substantially constant regardless of the address of the memory cell, the load MOSFET Q as described above is used.
9 to Q12 are not on the far end side of the complementary data lines D0 and D0B, in other words, on the side opposite to the end of the data line connected to the column switch side, but near the complementary data line and the column switch. Is provided. More specifically, the load MOSFETs Q9 to Q12 are arranged between the column switch and the memory cell arranged closest to the column switch.

In the figure, the word line W0 is selected by the X decoder circuit XDCR and the word driver WD. In the figure, in order to prevent the drawing from being complicated,
X decoder circuit X by NOR gate circuit G1
It also serves as DCR and word driver WD. This also applies to the word line Wn shown as another representative. The X decoder circuit XDCR is composed of NOR gate circuits G1 and G2 which are similar to each other. An internal complementary address signal formed by an address buffer XB for receiving an X-system external address signal AX (AX0 to AXi) consisting of a plurality of bits supplied from the outside is predetermined at the input terminals of these NOR gate circuits G1, G2 and the like. Are applied in combination. In addition, in fact,
The X decoder circuit XDCR is divided into multiple stages such as by providing a predecoder, and this is functionally shown by one NOR gate circuit in this embodiment.

Complementary data line D in the memory array
Between 0 and the common complementary data line RCD for reading,
A column switch is provided which conforms to the P-channel MOSFET Q5. A P-channel type M is also provided between the other data line D0B and the common complementary data line RCDB for reading.
A column switch including the OSFET Q6 is provided.
A column switch consisting of an N-channel MOSFET Q7 is provided between the complementary data line D0 and the write common complementary data line WCD in the memory array. The N-channel MOSFET Q is also provided between the other data line D0B and the common complementary data line WCDB for writing.
A column switch consisting of 8 is provided. A column selection signal Y0 is supplied to the gates of the N-channel MOSFETs Q7 and Q8, and the P-channel MOSFET Q
The column selection signal Y0 inverted by the inverter circuit N1 is supplied to the gates of 5 and Q6. As a result, when the column selection signal Y0 is set to the high selection level, the N-channel MOSFETs Q7 and Q8 and the P-channel MOSFETs Q5 and Q6 are turned on. The column selection signal Y0 is formed by an X decoding circuit (not shown) composed of a circuit similar to the X decoder circuit XDCR.

In the read operation, the voltage drop caused by the memory current flowing through the data line load resistance or the like with respect to the ground potential of the circuit is output as a read signal. Therefore, as described above, the P-channel MOSFET
Is used as a column switch, the read signal of the memory cell on the data line can be directly transmitted to the common complementary data lines CD and CDB side without causing level loss due to the threshold voltage of the MOSFET. In the write operation, the complementary data line D
One of 0 and D0B is set to a low level such as the ground potential of the circuit, and the memory MO of the memory cell connected thereto is
By turning off the SFET, the other memory MO
Switch the SFET on. Therefore, by using the N-channel MOSFET as a column switch as described above, the low level of the ground potential of the circuit can be transmitted to the data line as it is.

In this embodiment, the common complementary data lines RCD and RCD for reading are load MO of P-channel type for supplying power to the common complementary data line for reading.
SFETs Q15 and Q14 are provided. These loads M
A low level such as the ground potential of the circuit is constantly supplied to the gates of the OSFETs Q15 and Q14, thereby acting as a resistance element. This load MOSFET Q1
The resistance values of Q5 and Q14 are set to have sufficiently large resistance values with respect to the load MOSFETs Q11 and Q12 provided on the data lines D0 and D0B.

Common complementary data line RC for reading
D and RCDB are coupled to the input terminal of the sense amplifier SA. The output signal of the sense amplifier SA is transmitted to the input terminal of the data output circuit DOB which outputs the output signal from the external terminal. The common complementary data line WCD for writing,
WCDB is coupled to the output terminal of write amplifier WA. The output signal of the data input circuit DIB that receives the write data supplied from the external terminal is supplied to the input terminal of the write amplifier WA. By thus separating the common data line for reading and for writing, the load condition of the common complementary data line can be optimally set for the operations of the sense amplifier SA and the write amplifier WA. Then, although not particularly limited, common complementary data lines RCD and RC for reading are used for high-speed reading.
P channel MOSFET Q for equalizing between DB
13 is provided. An equalizing pulse EQ is supplied to the gate of the MOSFET Q13.

The equalizing pulse EQ is formed by the pulse generating circuit EQG. This pulse generation circuit EQG
Receives the pulse ADX formed by the X-system address signal change detection circuit XATD, the pulse ADY formed by the Y-system address signal change detection circuit YATD, and the write control signal WE. Alternatively, when any one-bit address signal of the Y system changes, the equalize pulse EQ is generated correspondingly.

The static RAM of this embodiment
The read operation from the memory cell is as follows. The storage MOSFET in which the memory cell is turned on can be regarded as a constant current source. Therefore, the read low level from the memory cell is equal to the load MOSFETs Q11 and Q12.
The memory cell MCn closest to the
A voltage drop occurs due to the memory current Io flowing through the resistance component RL of the FETs Q11 and Q12. The memory current Io and the resistance RY of the column switch provided in parallel with the resistance RL and the common data line load MOSFET
The resistance component RP of Q15 and Q14 is also shunted and flows, but the series combined resistance of these resistors RY and RP is
Since it is sufficiently larger than L, it can be substantially ignored. On the other hand, in the memory cell MC0 arranged farthest from the load MOSFET, the memory current Io flows through the resistance RL and the resistance RD of the data line. Therefore, at the input / output node of the memory cell, a large signal amplitude is set by the resistor RL + RD, but on the column switch side, there is only a voltage drop caused by the memory current Io flowing through the resistor RL as described above. Therefore, the read signal of the memory cell transmitted to the input of the sense amplifier SA through the common read complementary data lines RDC and RCDB can be made substantially constant regardless of the X-system address.

FIG. 1 shows a circuit diagram of an embodiment of the ECL output circuit according to the present invention. Although the circuit symbols given to the respective circuit elements in the same drawing partially overlap with those in FIG. 3, it should be understood that each realizes a separate circuit function. In the figure, the internal circuit LOG is
The read output signal formed by the sense amplifier, which includes the memory unit of the static RAM and the address selection circuit thereof and the sense amplifier SA, is not particularly limited, but is a differential as a drive stage of the data output circuit DOB. It is supplied to the base of the transistor T1. The reference voltage VBB is supplied to the base of the other differential transistor T2. Instead of this configuration, a complementary ECL level signal may be formed in the sense amplifier and supplied to the bases of the differential transistors T1 and T2.

Emitter follower output transistor T3
Is an ECL whose level is shifted by the base-emitter voltage VBE in response to the output signal of the differential transistor circuit.
A level output signal is formed and output from the external terminal Vout. Although not particularly limited, a load resistor R3 is provided between the emitter of the output transistor T3 and the operating voltage VTT such as -2V. The output transistor T3
May omit the load resistor R3 and provide a common load circuit in the external circuit so as to adopt the wired OR logic.

In this embodiment, the power supply line on the high level side for the differential transistor circuit is the power supply voltage VCC.
The wiring L1 is branched from the bonding pad that supplies (GND). For the other internal circuit LOG, the wiring L2 branched from the bonding pad is provided. Thereby, the power supply line L1 of the differential circuit is different from the power supply line L2 of the internal circuit LOG.
Are separated. In this configuration, each distributed resistance r
The voltage drops at 1 and r2 correspond to the operating currents flowing through them. As a result, the distributed resistance values of the power supply lines are the same (r =
Even if r1 = r2), the operating current of the internal circuit LOG flows through the corresponding distributed resistance r2, and only the constant current Io of the differential transistor circuit flows through the distributed resistance r1. Therefore, the voltage drop generated there is greatly reduced. It As a result, the high-level output signal formed by the differential transistor circuit has only a small voltage drop corresponding to the distributed resistance r1 and the constant current Io, so that the high-level margin of the output signal can be expanded.

In FIG. 1, the operating voltage VCC (GND) supplied to the collector of the output transistor T3 may use either the wiring L1 or L2. Output signal Vout
Is a voltage level-shifted by the base-emitter voltage VBE of the transistor T3 from the output signal of the differential transistor circuit forming the drive stage, and is independent of the collector voltage of the transistor T3. However, the collector of the output transistor T3 is connected to the power supply line L
When connected to 1, the distributed resistance r
Increase the voltage drop of 1. Therefore, as the collector of the output transistor T3, it is desirable to use the power supply line L2 on the internal circuit LOG side or to newly provide an independent wiring.

FIG. 2 is a circuit diagram of another embodiment of the ECL output circuit according to the present invention. In this embodiment, the bonding pads VCC1 and VCC2 respectively correspond to the power supply line L1 of the differential transistor circuit forming the drive stage and the power supply line L2 of the other internal circuits LOG and the like.
Is provided. This bonding pad VCC1 and VC
C2 may be connected to a common external lead in wire bonding, or may be connected to independent external leads. With this configuration, the power supply lines can be more reliably separated, so that the level margin can be expanded.

When the present invention is applied to the static RAM as shown in FIG. 3, the power supply lines are connected to the memory array section, the input circuit such as the address buffer, and the address selection circuit such as the decoder circuit. Alternatively, a power supply line branched from the bonding pad may be provided. Further, when outputting data in units of multiple bits such as 4 bits or 8 bits, a power supply line is separately configured for each differential transistor circuit corresponding to each bit, and a difference corresponding to each bit is provided. A power supply line may be provided commonly to the moving transistor circuits.

The operational effects obtained from the above embodiment are as follows. (1) An emitter follower output transistor is driven by a differential transistor circuit that receives an internal signal to be output and forms an output signal corresponding to the ECL level, and a voltage supply line on the high level side of this differential transistor circuit Is separated from the voltage supply lines of other internal circuits that form the internal signal to be output, the voltage drop generated in the power supply line due to the dispersion of the operating current can be reduced, and the high level of the output signal This has the effect of increasing the margin. (2) By using the power supply line branched from the common bonding pad, the high level margin of the output signal can be increased without increasing the number of bonding pads having a relatively large occupied area. Be done. (2) By providing a bonding pad corresponding to the internal power supply line and connecting it to the external terminals in common by wire bonding, the power supply impedance can be made smaller without increasing the number of external terminals, so the output signal high level. The effect that the margin can be increased can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
Alternatively, in FIG. 2, an additional circuit such as a level limiter circuit may be provided between the collectors of the differential transistors T1 and T2. In addition to the static type RAM having ECL compatibility, the present invention is Bi compatible with ECL.
-It can be widely used for various semiconductor integrated circuit devices having an ECL output circuit such as a CMOS gate array or ECL logic.

[0027]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the emitter follower output transistor is driven by a differential transistor circuit that receives an internal signal to be output and forms an output signal corresponding to the ECL level, and the high-level side voltage supply line of the differential transistor circuit is output as described above. By separating from the voltage supply line of other internal circuits that form the internal signal to be
The voltage drop that occurs in the power supply line due to the dispersion of the operating current can be reduced, and the high level margin of the output signal can be increased accordingly.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an ECL output circuit according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the ECL output circuit according to the present invention.

FIG. 3 is a specific circuit diagram showing an embodiment of a memory array section of a static RAM and its peripheral circuits to which the present invention is applied.

FIG. 4 is a circuit diagram showing an example of a conventional ECL output circuit.

[Explanation of symbols]

LOG ... Internal circuit, VCC, VCC1, VCC2 ... Bonding pad, L, L1, L2 ... Power supply line, r, r
1, r2 ... distributed resistance, T1 to T3 ... transistor, SA
Sense amplifier, XB ... X address buffer, XDC
R ... X system decoder circuit, DOB ... Data output circuit, DI
B ... Data input circuit, XATD, YATD ... Address signal change detection circuit, EQG ... Equalize pulse generation circuit,
MC ... Memory cell, W0, Wn ... Word line, D0, D0
B ... Complementary data lines, RCD, RCDB ... Read common complementary data lines, WCD, WCDB ... Write common complementary data lines, Q1 to Q15 ... MOSFETs.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/018 6959-5J H03K 19/092

Claims (3)

[Claims] 1. A differential transistor including a differential transistor circuit for receiving an internal signal to be output and forming an output signal corresponding to an ECL level, and an emitter follower output transistor driven by the differential transistor circuit. A semiconductor integrated circuit device characterized in that a voltage supply line on a high level side of a circuit is arranged separately from a voltage supply line of another internal circuit which forms the internal signal to be output. 2. The semiconductor integrated circuit according to claim 1, wherein the voltage supply line corresponding to the differential transistor circuit is branched from the bonding pad and separated from the voltage supply lines of other internal circuits. Circuit device. 3. The voltage supply line corresponding to the differential transistor circuit is separated from the voltage supply lines of other internal circuits by wiring means extending from an independent bonding pad. Item 1. A semiconductor integrated circuit device according to item 1.