JPH0581365A - Estimating method for wiring parasitic capacity - Google Patents

Abstract

PURPOSE:To improve the estimation/verification accuracy of the inter-wiring parasitic capacity. CONSTITUTION:In a symbolic circuit having three sticks A, B and C, A is a net (a) consisting of 11 grinds, B is a net (b) consisting of three grids, and the stick C is shown by a net (c) consisting of seven grids. The net (a) is selected, and subsequently, a parallel running distance and a parallel running interval of the nets (b) and (a) are calculated from the number of grids. The parallel running distance is given by La$-b corresponding to one-piece of the grid. The following expression (1) is an expression for deriving the wiring parasitic capacity (fringing capacity Ca-b) between the nets a-b. In the same way, the fringing capacity Ca-c between the nets a-c is derived. A procedure with the stick A as a reference is repeated until the stick A is all eliminated or the parallel running interval from the stick A exceeds a prescribed value and becomes a degree of the parasitic capacity can be disregarded. Ca-b=epsilonXLa- cXT/{Da-b-(Wa-Wb)/2}...(1). In the expression, epsilon, T and Wa(b) denote a dielectric constant of an insulating film, thickness of the wiring, and wiring width of the nets a(b), respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of estimating wiring parasitic capacitance, and more particularly to a method of estimating wiring parasitic capacitance from symbolic circuit data (so-called stick figure). Logic verification of LSI (for example, master slice LSI) layout data using a simulation method does not require a sample LSI, so that the development period can be significantly shortened, but the accuracy of simulation parameters is Since it affects the verification accuracy, a correct estimation of parameters is required.

[0002]

2. Description of the Related Art One of the parameters that determines the operating speed of an LSI is the parasitic capacitance of wiring. This parasitic capacitance is divided into a parasitic capacitance between the wiring and the bulk (hereinafter, parasitic capacitance to ground) and a parasitic capacitance between the wiring (hereinafter, parasitic capacitance between wirings). Further, the parasitic capacitance between wirings is within the same wiring layer. The inter-wiring parasitic capacitance (see FIG. 5, hereinafter, fringing capacitance) and the inter-wiring parasitic capacitance between different wiring layers (see FIG. 6, hereinafter, different-layer wiring parasitic capacitance). The following table shows the relationship between these capacities. Here, the present applicant has previously proposed the “wiring load calculation method” (Japanese Patent Application No. 03-034430, February 2, 1991).
8th application).

In this method, the number of grids (the number of squares) of wirings and contacts is calculated from the symbolic circuit data of the grid representation, and the wiring load of one grid unit is multiplied by the number of the above-mentioned calculation to obtain the ground for each wiring. Seeking the parasitic capacitance.

[0004]

However, in the method of the prior application, although the "parasitic capacitance to ground" of the parasitic capacitance of the wiring can be obtained, the "inter-wiring parasitic capacitance" cannot be estimated. There is a problem in that the parameters become inaccurate and therefore the verification accuracy cannot be improved.

Therefore, it is an object of the present invention to provide a method of estimating a wiring parasitic capacitance which can estimate the inter-wiring parasitic capacitance and contribute to the improvement of verification accuracy.

[0006]

According to a first aspect of the present invention, the position of each portion of an actual transistor pattern and a wiring route are previously included in the symbolic circuit data representing grid information for each wiring layer. The wiring width information is added, and one wiring route belonging to the same wiring layer and one wiring route running in parallel with the wiring route are extracted from the circuit data, and the two wiring routes run in parallel. The distance and the parallel running distance are calculated from the number of grids, and these parallel running distances,
It is characterized in that the parasitic capacitance between the two wiring paths is estimated based on the parallel running distance and the wiring width information of the two wiring paths.

According to a second aspect of the present invention, the wiring width information of the wiring route and the insulating film are previously included in the symbolic circuit data representing the position of each portion of the actual transistor pattern and the wiring route by grid information for each wiring layer. Thickness information is added to detect the matching portion of the wiring route between the two wiring layers, the length information of the matching portion is calculated from the number of grids, and the length information and the two wirings in the matching relation are detected. It is characterized in that the matching area is obtained from the wiring width information of the path, and the wiring parasitic capacitance between different wiring layers is estimated based on the matching area and the insulating film thickness information between the two wiring layers.

[0008]

According to the present invention, the wiring width information of the wiring path and / or the thickness information of the insulating film is added to the symbolic circuit data in advance. Then, the parasitic capacitance (fringed capacitance) between the two wiring routes is calculated based on the parallel running distances and the parallel running intervals of the two wiring routes and the wiring width information of the two wiring routes, which are calculated from the number of grids. Or
Based on the matching area of the wiring route between the two wiring layers calculated from the number of grids and the wiring width information and the insulation film thickness information,
Wiring parasitic capacitance between different wiring layers (parasitic capacitance between different wiring layers)
Is required.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are diagrams showing an embodiment of a method of estimating wiring parasitic capacitance from symbolic circuit data according to the present invention. FIG. 1A is a layout of an actual transistor pattern TR, and FIG. 1B is a diagram of circuit data DT expressing it in a grid map. Figure 1
Numbers 1 to 8 in (a) are numbers of respective parts (contacts and terminals) of the transistor pattern, and the same numbers are written in the corresponding grids. For example, power supply wiring (V
The symbolic layout data of the (DD line) is created by connecting 1 grid of number 3 and 1 grid of number 4 with a stick line.

Here, in the present invention, wiring width information is added to the symbolic layout data. For example, information on the wiring width Wx is added to the data on the VDD line. Next, the procedure for estimating the inter-wiring parasitic capacitance in the same wiring layer, that is, the "fringing capacitance" will be described with reference to FIG.

FIG. 2 is an example of symbolic circuit data having three sticks A, B and C. The stick A is represented by a net a consisting of 11 grids, the stick B is represented by a net b consisting of 3 grids, and the stick C is represented by a net c consisting of 7 grids. First, one stick, for example, the stick A (net a) is selected, and then the parallel running distance and the parallel running distance between the stick A and the stick B (net b) adjacent to the stick A are calculated from the number of grids. The parallel running distance is given by L _ab corresponding to three grids, and the parallel running distance is given by D _ab corresponding to one grid.
The following equation (1) is an equation for obtaining the wiring parasitic capacitance between the nets a and b, that is, the fringing capacitance C _ab between two wiring paths belonging to the same wiring layer.

C _ab = ε × L _ab × T / {D _ab − (Wa−Wb) / 2} (1) where ε: dielectric constant of insulating film T: thickness of wiring (for example, process target value) Wa: Wiring width of net a Wb: Wiring width of net b When the fringing capacitance between the nets a and b is calculated,
The parallel running distance and the parallel running distance between the stick C (net c) and the remaining part of the stick A excluding the parallel running distance L _ab are similarly calculated from the number of grids. The parallel running distance is given by L _ac corresponding to three grids, and the parallel running distance is given by D _ac corresponding to two grids. The following equation (2) is the fringing capacity C _ac between the nets a and c.
Is an expression for obtaining.

C _ac = ε × L _ac × T / {D _ac − (Wa−Wc) / 2} (2) However, Wc: wiring width of net c Stick A
Is removed, or the parallel running distance from the stick A is equal to or larger than a predetermined value and the parasitic capacitance is reduced to a negligible level.

By repeating the above procedure with the stick B as the reference and repeating the procedure with the stick C as the reference, the inter-wiring parasitic capacitance (fringing capacitance) of the same wiring layer can be estimated. .. As shown in FIG. 3, when the same net (net d and net e) runs in parallel, the parallel running sections L _de and L
_A wiring inter-wiring parasitic capacitance (fringing capacitance) is also generated in _ed . Since the parasitic capacitances are parallel to C _de and C _ed, it is sufficient to simply add the two parasitic capacitances.

Next, the procedure for estimating the wiring parasitic capacitance between different wiring layers, that is, the "parasitic capacitance between different layer wirings" will be described with reference to FIG. FIG. 4A is a grid (lattice) map of the first metal wiring layer, and FIG. 4B is a grid map of the second metal wiring layer. The first layer has nets f and g. A net h is formed on the second layer.

First, two grid maps are overlapped with each other to check the overlap between nets. In the example of FIG. 4, two grids of the net f on the first layer and four grids of the net g overlap with six grids of the net h on the second layer.
Next, the area of these polymerized nets (f, g and h)
The parasitic capacitance between different layers is estimated based on the number of grids and the width information of each wiring, and further based on the obtained area and the thickness of the insulating film between the wiring layers (for example, from the process target value).

When a parasitic capacitance between wirings of different layers occurs between nets having a fringing capacitance, this parasitic capacitance and the above-mentioned estimated capacitance are in parallel, so it is sufficient to simply add them. In the case of multi-layer wiring that exceeds two layers,
After performing the process shown in Fig. 4 on the grid map of the top layer and the grid map of one layer below, the overlapping portion of the net is removed from the grid map of the top layer, and the grid map of the top layer and the grid map of two layers below The same processing is executed for, and this is repeated up to the grid map in the lowermost layer.
Hereinafter, by replacing the uppermost layer with the second layer, the third layer, ..., And repeating, it is possible to estimate the different layer wiring parasitic capacitance in the case of a multilayer wiring exceeding two layers.

Furthermore, for a net forming a critical path in the same wiring layer, the fringing capacitance is extracted in both left and right directions of the net, or for a net forming a critical path between different wiring layers, By extracting the parasitic capacitance between different wiring layers in the stacking direction of the wiring layers, it is possible to extract the wiring parasitic capacitance for a specific net.

[0019]

According to the present invention, it is possible to provide a method for estimating the parasitic capacitance between wirings, which contributes to the improvement of verification accuracy.

[Brief description of drawings]

FIG. 1 is a transistor pattern layout of one embodiment and a grid map thereof.

FIG. 2 is an estimated diagram of fringing capacity according to an embodiment.

FIG. 3 is an estimated diagram of a parallel fringing capacity according to an embodiment.

FIG. 4 is an estimated diagram of parasitic capacitance between different-layer wirings according to an embodiment.

FIG. 5 is a conceptual diagram of fringing capacity.

FIG. 6 is a conceptual diagram of parasitic capacitance between different layer wirings.

[Explanation of symbols]

 TR: Transistor pattern DT: Circuit data Wx: Wiring width

Claims (2)

[Claims] 1. The wiring width information of the wiring route is added in advance to symbolic circuit data that represents the position of each portion of the actual transistor pattern and the wiring route by grid information for each wiring layer. One wiring route belonging to the same wiring layer and one wiring route running in parallel with the wiring route are extracted from the data, and the parallel running distance and the parallel running interval of the two wiring routes are calculated from the number of grids, A method for estimating a wiring parasitic capacitance, characterized in that the parasitic capacitance between the two wiring paths is estimated based on the parallel running distance, the parallel running distance, and the wiring width information of the two wiring paths. 2. The symbolic circuit data representing the position of each part of the actual transistor pattern and the wiring path by grid information for each wiring layer is previously provided with the wiring width information of the wiring path and the insulating film thickness information. Is added, the matching portion of the wiring route between the two wiring layers is detected, the length information of the matching portion is calculated from the number of grids, and the length information and the wiring width information of the two wiring routes having the matching relation are detected. A wiring parasitic capacitance between different wiring layers is estimated based on the obtained matching area and information on the insulating film thickness between the two wiring layers.