JP3786791B2 - Capacity calculation device and capacity calculation method - Google Patents

Description

尚、形状モデル作成工程で作成された形状モデルは、図１に示すようにデータベースＤＡ１に記憶される。これにより、形状モデル作成工程で作成された形状モデルを再利用することが可能となる。
【００７６】
また、形状モデル作成工程において、形状実測工程で実測された配線部の形状に関するデータをプロットすることにより形状モデルを作成したが、これに代えて、形状実測工程で実測された配線部の形状に関するデータに対して、例えば最小２乗法等の統計的な方法を用いることにより形状モデルを作成してもよい。
【００７７】
また、形状モデル作成工程において、ボイドの形状の配線間隔に対する依存関係が表現された形状モデルを作成したが、これに限られず、他の形状モデル、例えば層間絶縁膜のテーパ部の形状の配線幅に対する依存関係が表現された形状モデル等も同様に作成することができる。
【００７８】
また、形状モデル作成工程において、形状モデルの作成のために原型データの形状種別として長方形を用いたが、これに限られず、他の形状種別、例えば多角形、円又はこれらの図形の複合した図形等を用いることができる。
【００７９】
次に、ステップＳＡ３において、疑似構造生成手段により行なわれる疑似構造生成工程について説明する。すなわち、疑似構造生成工程においては、形状モデル作成工程で作成された形状モデルに配線層の形状、例えば配線間隔を入力することにより、絶縁層の形状、例えばパッシベーション膜に生じたボイドの形状を求めた後、該絶縁層の形状を用いて疑似構造を生成する。
【００８０】
以下、疑似構造生成工程において疑似構造を生成する方法について、複数の配線層を有する配線部における複数の配線容量成分を計算するために複数の疑似構造を生成する場合を例として、図６に示すフロー図を参照しながら説明する。尚、ここで、配線部における複数の配線層は、互いに電気的な接触を回避するため、且つ素子間、セル間、又はブロック間配線等の目的を区別するため、層間絶縁膜により物理的に上下方向に分離されているものとする。
【００８１】
ステップＳＡ３１において、配線層数、配線層の膜厚及び層間絶縁膜の誘電率等を入力する。
【００８２】
ステップＳＡ３２において、疑似構造の生成手順が抽象的に記述されたテンプレートを多数蓄積しているデータベースＤＡ２から、配線容量成分の計算に必要なテンプレートを順次選択する。
【００８３】
［表１］はテンプレートの一例を示している。
【００８４】
【表１】

【００８５】
［表１］において、配線層ｍｎのｍは配線層であることを示しており、ｎは各配線層の区別を示している。例えば、ｍ１は接地配線層ｍ０を除く最下層の配線層、ｍ３はｍ１から２層上の配線層というように決めておく。
【００８６】
ステップＳＡ３３において、ステップＳＡ３２で選択されたテンプレートに含まれる配線層を順次選択する。
【００８７】
ステップＳＡ３４において、形状モデル作成工程で作成された形状モデル、例えば図５に示すボイドの形状の配線間隔に対する依存関係が表現された形状モデルに、表１に示すテンプレートに記述された配線間隔を入力することによりボイドの形状を求めた後、該ボイドの形状、並びにステップＳＡ３１で入力された配線層の膜厚及び層間絶縁膜の誘電率等をテンプレートに付加して、配線容量成分の計算に必要な疑似構造の形状決定値の組み合わせである形状数値表を生成すると共に該形状数値表をデータベースＤＡ３に蓄積する。
【００８８】
［表２］は形状数値表の一例を示している。
【００８９】
【表２】

【００９０】
ステップＳＡ３５において、ステップＳＡ３２で選択されたテンプレートに含まれる全ての配線層について処理を終了したか否かの判断をする。処理が終了していれば、ステップＳＡ３６に進み、処理が終了していなければ、ステップＳＡ３３に戻る。
【００９１】
ステップＳＡ３６において、計算対象となる配線容量成分に対応する全てのテンプレートについて処理を終了したか否かの判断をする。処理が終了していれば、ステップＳＡ３７に進み、処理が終了していなければ、ステップＳＡ３２に戻る。
【００９２】
ステップＳＡ３７において、配線容量成分の計算に必要な形状数値表をデータベースＤＡ３から順次選択した後、該形状数値表に基づき疑似構造を順次生成する。
【００９３】
図７は、［表２］に示す形状数値表において太い実線で囲まれた一の形状決定値の組み合わせに基づき生成された疑似構造の一例を示す断面図である。図７において、１１０は接地配線層となる第１の配線層、１１１は第２の配線層、１１２は第１の層間絶縁膜、１１３は第２の層間絶縁膜、１１４はパッシベーション膜、１１４ａはパッシベーション膜１１４に生じたボイドを示している。また、図７において、太い実線により囲まれている部分は配線容量シミュレーションの対象となる一の解析領域を示している。図７に示すように、一の解析領域に隣接する部分である他の解析領域は一の解析領域を折り返した形状と同等であるため、一の解析領域が表現された疑似構造を他の解析領域に流用できるので、疑似構造の生成に要する時間を短縮することができる。
【００９４】
次に、ステップＳＡ４において、配線容量計算手段により行なわれる配線容量計算工程について説明する。すなわち、配線容量計算工程においては、疑似構造生成工程で生成された疑似構造に基づき、配線容量シミュレーションを用いて配線容量計算を行なった後、該配線容量計算の結果に基づき配線容量成分の計算を行なう。
【００９５】
第１の実施形態によると、形状モデル作成工程において、形状実測工程で実測された配線部の形状に関するデータに基づき、絶縁層の形状の、配線層の形状に対する依存関係が表現された形状モデルを作成した後、疑似構造生成工程において、形状モデル作成工程で作成された形状モデルに配線層の形状を入力して絶縁層の形状を求めると共に該絶縁層の形状を用いて疑似構造を生成するため、絶縁層の形状が正確に表現された疑似構造を生成できるので、配線部の容量計算の精度を向上させることができる。
【００９６】
尚、第１の実施形態においては、２次元の疑似構造を用いたが、これに代えて、３次元の疑似構造を用いても同等の効果が得られる。
【００９７】
（第２の実施形態）
以下、本発明の第２の実施形態に係る容量計算装置及び容量計算方法について、図面を参照しながら説明する。
【００９８】
図８は第２の実施形態に係る容量計算方法のフロー図である。
【００９９】
まず、ステップＳＢ１において、疑似構造生成手段により行なわれる疑似構造生成工程について説明する。すなわち、疑似構造生成工程においては、半導体装置の製造工程を所定の製造条件下において再現できる数式である製造モデル、例えばスパッタリング法を用いた薄膜形成工程における薄膜成長速度の、所定の製造条件（スパッタ温度、スパッタ時間又は成長物質等）に対する依存関係が表現された製造モデルに、所定の製造条件を入力することにより、半導体装置の製造工程を再現した後、該製造工程を再現した結果を用いて疑似構造を生成する。
【０１００】
尚、本実施形態においては、予め作成され、データベースに記憶されている製造モデル及び製造条件等を用いるものとする。
【０１０１】
以下、疑似構造生成工程において疑似構造を生成する方法について、複数の配線層を有する配線部における複数の配線容量成分を計算するために必要となる複数の疑似構造を生成する場合を例として、図８に示すフロー図を参照しながら説明する。
【０１０２】
ステップＳＢ１１において、疑似構造の生成手順が抽象的に記述されたテンプレートを多数蓄積しているデータベースＤＢ１から、配線容量成分の計算に必要なテンプレートを順次選択する。
【０１０３】
［表３］はテンプレートの一例を示している。
【０１０４】
【表３】

【０１０５】
ステップＳＢ１２において、ステップＳＢ１１で選択されたテンプレートに含まれる配線層を順次選択する。
【０１０６】
ステップＳＢ１３において、後のステップＳＢ１８における製造工程の再現により得られる形状決定値の組み合わせが付加される形状数値表を、テンプレートに基づき生成すると共に該形状数値表をデータベースＤＢ２に記憶する。
【０１０７】
［表４］は形状数値表の一例を示している。
【０１０８】
【表４】

【０１０９】
ステップＳＢ１４において、ステップＳＢ１１で選択されたテンプレートに含まれる全ての配線層について処理を終了したか否かの判断をする。処理が終了していれば、ステップＳＢ１５に進み、処理が終了していなければ、ステップＳＢ１２に戻る。
【０１１０】
ステップＳＢ１５において、計算対象となる配線容量成分に対応する全てのテンプレートについて処理を終了したか否かの判断をする。処理が終了していれば、ステップＳＢ１６に進み、処理が終了していなければ、ステップＳＢ１１に戻る。
【０１１１】
ステップＳＢ１６において、半導体装置を製造するための一連の工程（以下、プロセスと称する）の種類を指定する。
【０１１２】
ステップＳＢ１７において、ステップＳＢ１６で指定されたプロセスに含まれる各製造工程を再現する製造モデルの種類を指定する。
【０１１３】
ステップＳＢ１８において、プロセスの製造工程順序及び製造条件からなるプロセスデータが蓄積されたデータベースＤＢ３から、ステップＳＢ１６で指定されたプロセスの製造工程順序及び製造条件を抽出すると共に、製造モデル及び該製造モデルのパラメータからなるモデルデータが蓄積されたデータベースＤＢ４から、ステップＳＢ１７で指定された製造モデル及び該製造モデルのパラメータを抽出した後、抽出された製造工程順序に従って、抽出された製造モデルに抽出された製造条件を入力していく。これにより、製造工程が順次再現されて、例えば半導体装置を構成する複数の構成要素の形状又は誘電率が求められる。次に、製造工程を再現した結果に基づき、疑似構造の形状決定値の組み合わせを作成した後、該形状決定値の組み合わせを、データベースＤＢ２に記憶されている形状数値表に付加して形状数値表を完成させる。
【０１１４】
ステップＳＢ１９において、配線容量成分の計算に必要な形状数値表をデータベースＤＢ２から順次選択した後、該形状数値表に基づき疑似構造を順次生成する。
【０１１５】
図９は、疑似構造生成工程において生成された疑似構造の一例を示す断面図である。図９において、２００は接地配線層となる第１の配線層、２０１は第２の配線層、２０２は第１の層間絶縁膜、２０３は第２の層間絶縁膜、２０４はパッシベーション膜、２０４ａはパッシベーション膜２０４に生じたボイドを示している。また、図９において、太い実線により囲まれている部分は配線容量シミュレーションの対象となる一の解析領域を示している。図９に示すように、一の解析領域に隣接する部分である他の解析領域は一の解析領域を折り返した形状と同等であるため、一の解析領域が表現された疑似構造を他の解析領域に流用できるので、疑似構造の生成に要する時間を短縮することができる。
【０１１６】
尚、疑似構造生成工程において、製造条件及び製造モデル等をデータベースから抽出して用いたが、これに代えて、製造条件及び製造モデル等を逐次作成して用いてもよい。
【０１１７】
また、疑似構造生成工程において、プロセスの種類を指定することにより製造条件又は製造工程順序を決めたが、これに代えて、疑似構造生成工程で生成される疑似構造が所定の疑似構造に等しくなるように、製造条件又は製造工程順序を決めてもよい。
【０１１８】
次に、ステップＳＢ２において、配線容量計算手段により行なわれる配線容量計算工程について説明する。すなわち、配線容量計算工程においては、疑似構造生成工程で生成された疑似構造に基づき、配線容量シミュレーションを用いて配線容量計算を行なった後、該配線容量計算の結果に基づき配線容量成分の計算を行なう。
【０１１９】
第２の実施形態によると、疑似構造生成工程において、半導体装置の製造工程を所定の製造条件下において再現できる製造モデルに、所定の製造条件を入力して半導体装置の製造工程を再現すると共に該製造工程を再現した結果を用いて疑似構造を生成するため、製造工程に対応して変化する半導体装置の構造が正確に表現された疑似構造を生成できるので、容量計算の精度を向上させることができる。また、半導体装置の試作又は実測を行なうことなく疑似構造を生成できるので、容量計算を簡単に行なうことができる。
【０１２０】
尚、第２の実施形態において、計算対象となる配線容量成分毎に疑似構造を逐次作成したが、これに代えて、全ての配線層が配置された疑似構造を予め製造モデルを用いて生成しておくと共に、該疑似構造を部分的に変更して、計算対象となる配線容量成分毎に用いてもよいし、又は配線部における特徴的な構造が表現された複数の疑似構造を予め製造モデルを用いて生成しておくと共に、該複数の疑似構造を幾何学的に組み合わせて、計算対象となる配線容量成分毎に用いてもよい。このようにすると、疑似構造の生成に要する時間を短縮することができる。
【０１２１】
また、第２の実施形態において、製造モデルを用いて生成された疑似構造に基づき配線容量の計算を行なったが、これに代えて、製造モデルを用いて生成された疑似構造に基づき配線抵抗の計算を行なっても同等の効果、すなわち抵抗計算の精度が向上するという効果が得られる。
【０１２２】
（第３の実施形態）
以下、本発明の第３の実施形態に係る容量計算装置及び容量計算方法について、トランジスタ素子に生じる空乏層の容量の計算を例として、図面を参照しながら説明する。
【０１２３】
図１０は第３の実施形態に係る容量計算方法のフロー図である。
【０１２４】
まず、ステップＳＣ１において、原型データ生成手段により行なわれる原型データ生成工程について説明する。すなわち、原型データ生成工程においては、容量計算の対象となる半導体装置の構造が表現された疑似構造の原型データを生成する。
【０１２５】
図１１は、空乏層を含むトランジスタ素子の一例を示す断面図である。図１１において、３００は半導体基板、３００ａは半導体基板の表面、３０１はソース・ドレイン領域、３０２はゲート絶縁膜、３０３はゲート電極、３０４は空乏層を示している。また、図１１において、太い実線はチャネル領域とソース領域（又はドレイン領域）とのジャンクションを示しており、白い丸印は電子を示しており、黒い丸印は正孔を示している。ジャンクションの形若しくは位置又は空乏層３０４の曲がり方若しくは厚さは、半導体基板３００又はソース・ドレイン領域３０１の電気的特性、例えば不純物物質又は不純物濃度等によって変化する。
【０１２６】
原型データ生成工程において、具体的には、半導体基板３００とソース・ドレイン領域３０１との間に挟まれた空乏層３０４の容量を近似的に求めたいので、空乏層３０４の原型データとしては、例えばジャンクションを中心線とする長方形を選択する。
【０１２７】
また、原型データ生成工程において、疑似構造の原型データを生成すると共に、容量計算の対象（本実施形態では半導体基板３００とソース・ドレイン領域３０１との間に挟まれた空乏層３０４）、及び容量計算の具体的条件（本実施形態では半導体基板３００とソース・ドレイン領域３０１とに印加する電圧、及び容量の単位等）等を入力しておく。尚、前記の入力は後の容量計算工程において行なってもよい。
【０１２８】
次に、ステップＳＣ２において、形状モデル作成手段により行なわれる形状モデル作成工程について説明する。すなわち、形状モデル作成工程においては、半導体装置における一の構成要素の形状の、半導体装置における他の構成要素の形状又は電気的特性に対する依存関係が表現された数式である形状モデル、例えば空乏層の形状の、ジャンクションの基板表面からの深さ（以下、ジャンクション位置と称する）及び空乏層の厚さに対する依存関係が表現された形状モデルを作成する。尚、空乏層の厚さは、半導体基板内部における電荷総量（キャリアである電子及び正孔の数の差）の分布等から求められる。
【０１２９】
以下、基板下向きにｙ座標をとると共にｙ座標の原点を基板表面にとった場合の空乏層３０４の形状モデルの一例を示す。
【０１３０】
空乏層下端ｙ座標 ＝ ジャンクション位置 ＋ 空乏層の厚さ／２
空乏層上端ｙ座標 ＝ ジャンクション位置 − 空乏層の厚さ／２
尚、形状モデル作成工程で作成された形状モデルは、図１０に示すようにデータベースＤＣ１に記憶される。これにより、形状モデル作成工程で作成された形状モデルを再利用することが可能となる。
【０１３１】
次に、ステップＳＣ３において、計算条件値作成手段により行なわれる計算条件値作成工程について説明する。すなわち、計算条件値作成工程において、半導体装置における他の構成要素の形状又は電気的特性、例えば、ジャンクション位置等が数値計算可能なデータとして表現された計算条件値を作成する。
【０１３２】
次に、ステップＳＣ４において、疑似構造生成手段により行なわれる疑似構造生成工程について説明する。すなわち、疑似構造生成工程において、形状モデル作成工程で作成された形状モデルに計算条件値作成工程で作成された計算条件値を入力することにより、半導体装置における一の構成要素の形状、例えば空乏層の形状を求めた後、該一の構成要素の形状を用いて疑似構造を生成する。
【０１３３】
図１２は、疑似構造生成工程で生成された疑似構造の一例を示す断面図である。図１２において、３１０は半導体基板、３１０ａは半導体基板の表面、３１１はソース・ドレイン領域、３１２はゲート絶縁膜、３１３はゲート電極、３１４は空乏層を示している。また、図１２において、太い実線はチャネル領域とソース領域（又はドレイン領域）とのジャンクションを示し、ａはジャンクション位置を示し、ｂは空乏層の厚さを示している。
【０１３４】
次に、ステップＳＣ５において、容量計算手段により行なわれる容量計算工程について説明する。すなわち、容量計算工程においては、疑似構造生成工程で生成された疑似構造に基づき、半導体装置の所定部分、例えば空乏層の容量を計算する。
【０１３５】
第３の実施形態によると、形状モデル作成工程において、一の構成要素の形状の、他の構成要素の形状又は電気的特性に対する依存関係が表現された形状モデルを作成すると共に、計算条件値作成工程において、他の構成要素の形状又は電気的特性が数値計算可能なデータとして表現された計算条件値を作成した後、疑似構造生成工程において、形状モデル作成工程で作成された形状モデルに計算条件値作成工程で作成された計算条件値を入力して一の構成要素の形状を求めると共に該一の構成要素の形状を用いて疑似構造を生成するため、一の構成要素の形状が正確に表現された疑似構造を生成できるので、容量計算の精度を向上させることができる。また、計算条件値の変更により色々な疑似構造を簡単に生成できるので、容量計算を簡単化することができる。
【０１３６】
尚、第３の実施形態において、空乏層の形状の、ジャンクション位置及び空乏層の厚さに対する依存関係が表現された形状モデルを作成したが、これに代えて、例えば空乏層の形状の、基板物質、不純物物質及び不純物導入量に対する依存関係が表現された形状モデル等を作成してもよい。基板物質と不純物物質と不純物導入量とが決まると、不純物濃度分布が経験的に求められるため、空乏層付近の構造を決めることができる。すなわち、空乏層の形状の、基板物質、不純物物質及び不純物導入量に対する依存関係が表現された形状モデルに、半導体装置の製造時における不純物導入量等の制御可能な値を入力することにより、空乏層の形状が求められる。
【０１３７】
以下に、基板物質と不純物物質と不純物導入量とから不純物濃度分布を求めるための数式の一例と、該不純物濃度分布からジャンクション位置又は空乏層の厚さを求めるための数式の一例とを示す。尚、不純物濃度分布から求めたジャンクション位置と空乏層の厚さとから空乏層の形状を求めるための数式は前記の空乏層３０４の形状モデルの一例と同一である。
【０１３８】
基板表面からある深さでの不純物濃度 ＝
ｆ（基板物質、不純物物質、不純物導入量、深さ）
但し、ｆは不純物濃度を計算するための不純物分布関数である。
【０１３９】
ジャンクション位置 ＝
ｇ（一導電型不純物物質、一導電型不純物導入量、他導電型不純物物質、 他導電型不純物導入量）
但し、ｇはｆによって計算される一導電型不純物濃度と他導電型不純物濃度とが同じになる位置を求めるための計算処理である。
【０１４０】
空乏層の厚さ ＝
ｈ（不純物物質、………、表面濃度、………、係数、………）
但し、ｈは不純物物質の組み合わせ、各不純物物質の濃度、電子と正孔との再結合の割合等から空乏層の厚さを求めるための計算処理である。
【０１４１】
（第３の実施形態の変形例）
以下、本発明の第３の実施形態の変形例に係る容量計算装置及び容量計算方法について、図面を参照しながら説明する。
【０１４２】
図１３は第３の実施形態の変形例に係る容量計算方法のフロー図である。
【０１４３】
第３の実施形態の変形例に係る容量計算装置及び容量計算方法が第３の実施形態と異なるのは、ステップＳＤ２において、誘電率モデル作成手段により誘電率モデル作成工程が行なわれることである。すなわち、誘電率モデル作成工程においては、半導体装置における一の構成要素の誘電率の、半導体装置における他の構成要素の形状又は電気的特性に対する依存関係が表現された数式である誘電率モデル、例えば空乏層の誘電率の、半導体基板の電荷総量（キャリアである電子及び正孔の数の差）に対する依存関係が表現された誘電率モデルを作成する。
【０１４４】
図１４は、空乏層を含むトランジスタ素子の構造が表現された疑似構造の一例を示す断面図である。図１４において、３２０は半導体基板、３２０ａは半導体基板の表面、３２１はソース・ドレイン領域、３２２はゲート絶縁膜、３２３はゲート電極、３２４は空乏層を示している。また、図１４において、太い実線はチャネル領域とソース領域（又はドレイン領域）とのジャンクションを示している。
【０１４５】
図１５は、空乏層を定義する方法の一例を示す図である。図１５において、太い実線は、一の不純物物質を一の不純物導入量で半導体基板に注入した場合の半導体基板内部における電荷総量の一の分布を示しており、一点鎖線は、他の不純物物質を他の不純物導入量で半導体基板に注入した場合の半導体基板内部における電荷総量の他の分布を示しており、破線は空乏層と規定される電荷総量の上限値を示している。
【０１４６】
図１５に示す一の分布の場合、一の分布が空乏層と規定される電荷総量の上限値を下回る範囲が空乏層と規定されて、図１５に示すｃが空乏層の厚さとなる。
【０１４７】
しかし、図１５に示す他の分布の場合、電荷総量の上限値から空乏層の厚さを求めることができないため、例えば空乏層の形状の、ジャンクション位置及び空乏層の厚さに対する依存関係が表現された形状モデルを用いて疑似構造を生成することはできない。
【０１４８】
一方、第３の実施形態の変形例によると、例えばジャンクション位置及び空乏層の厚さをそれぞれ一定の値に固定して、空乏層の誘電率の電荷総量に対する依存関係が表現された誘電率モデルを用いて疑似構造を生成するため、図１５に示す他の分布の場合にも疑似構造を生成することができる。
【０１４９】
（第４の実施形態）
以下、本発明の第４の実施形態に係る容量計算装置及び容量計算方法について、図面を参照しながら説明する。
【０１５０】
図１６は第４の実施形態に係る容量計算方法のフロー図である。
【０１５１】
まず、ステップＳＥ１において、製造工程指定手段により行なわれる製造工程指定工程について説明する。すなわち、製造工程指定工程において、半導体装置の製造工程の種類及び実施順序を指定する。
【０１５２】
次に、ステップＳＥ２において、製造モデル作成手段により行なわれる製造モデル作成工程について説明する。すなわち、製造モデル作成工程において、製造工程指定工程で指定された製造工程を所定の製造条件下において再現できる数式である製造モデル、例えば基板表面からの不純物の移動距離又は不純物濃度等の、所定の製造条件（拡散温度又は拡散時間等）に対する依存関係が表現された製造モデルを作成する。
【０１５３】
尚、製造モデル作成工程で作成された製造モデルは、データベースＤＥ１に記憶される。これにより、製造モデル作成工程で作成された製造モデルを再利用することが可能となる。
【０１５４】
次に、ステップＳＥ３において、計算条件値作成手段により行なわれる計算条件値作成工程について説明する。すなわち、計算条件値作成工程においては、所定の製造条件が数値計算可能なデータとして表現された計算条件値を作成する。
【０１５５】
次に、ステップＳＥ４において、疑似構造生成手段により行なわれる疑似構造生成工程について説明する。すなわち、疑似構造生成工程において、製造工程指定工程で指定された製造工程の実施順序に従って、製造モデル作成工程で作成された製造モデルに計算条件値作成工程で作成された計算条件値を入力することにより、半導体装置の製造工程を再現した後、該製造工程を再現した結果を用いて疑似構造を生成する。
【０１５６】
次に、ステップＳＥ５において、容量計算手段により行なわれる容量計算工程について説明する。すなわち、容量計算工程においては、疑似構造生成工程で生成された疑似構造に基づき、半導体装置の所定部分の容量を計算する。
【０１５７】
第４の実施形態によると、製造モデル作成工程において、半導体装置の製造工程を所定の製造条件下において再現できる数式である製造モデルを作成すると共に、計算条件値作成工程において、所定の製造条件が数値計算可能なデータとして表現された計算条件値を作成した後、疑似構造生成工程において、製造モデル作成工程で作成された製造モデルに計算条件値作成工程で作成された計算条件値を入力して半導体装置の製造工程を再現すると共に該製造工程を再現した結果を用いて疑似構造を生成するため、製造工程に対応して変化する半導体装置の構造が正確に表現された疑似構造を生成できるので、容量計算の精度を向上させることができる。また、計算条件値の変更により色々な疑似構造を簡単に生成できるので、容量計算を簡単化することができる。
【０１５８】
（第５の実施形態）
以下、本発明の第５の実施形態に係る容量計算装置及び容量計算方法について、細い溝型素子分離絶縁膜（以下、ＳＴＩと称する）の容量の計算を例として、図面を参照しながら説明する。
【０１５９】
図１７は第５の実施形態に係る容量計算方法のフロー図である。
【０１６０】
まず、ステップＳＦ１において、原型データ生成手段により行なわれる原型データ生成工程について説明する。すなわち、原型データ生成工程においては、容量計算の対象となる半導体装置の構造が表現された疑似構造の原型データを生成する。
【０１６１】
図１８は、ＳＴＩの一例を示す断面図である。図１８において、５００は半導体基板、５０１はソース・ドレイン領域、５０２はゲート絶縁膜、５０３はゲート電極、５０４はＳＴＩ、ｄはＳＴＩの幅、ｅはＳＴＩの高さを示している。
【０１６２】
原型データ生成工程において、具体的には、２つのトランジスタ領域の間に挟まれたＳＴＩ５０４の容量を近似的に求めたいので、ＳＴＩ５０４の原型データとしては、例えば２つのトランジスタ領域の間に挟まれた四角形を選択する。このようにすると、ＳＴＩの形状はＳＴＩの幅ｄ及びＳＴＩの高さｅにより表現することができる。但し、実際のＳＴＩの形状は、製造工程における拡散温度又は拡散時間等の製造条件のばらつきによって変化する。
【０１６３】
図１９は、ＳＴＩの幅のばらつきの一例を示す図である。図１９において、ＳＴＩの幅のばらつきの分布を太い実線及び棒グラフにより示しており、ＳＴＩの幅の平均値を破線で示している。
【０１６４】
次に、ステップＳＦ２において、製造モデル作成手段により行なわれる製造モデル作成工程について説明する。すなわち、製造モデル作成工程においては、半導体装置における一の構成要素の形状又は誘電率の、半導体装置の製造工程における所定の製造条件に対する依存関係が表現された数式である製造モデル、例えばＳＴＩの形状、つまりＳＴＩの幅又はＳＴＩの高さの、所定の製造条件（酸化時間又はエッチングレート等）に対する依存関係が表現された数式である製造モデルを作成する。尚、製造モデルは、原型データ生成工程で生成された疑似構造の原型データ、及び半導体装置における一の構成要素の形状又は誘電率の規格値に基づき作成される。
【０１６５】
次に、ステップＳＦ３において、ばらつきモデル作成手段により行なわれるばらつきモデル作成工程について説明する。すなわち、ばらつきモデル作成工程においては、所定の製造条件に基づき、該所定の製造条件の複数のばらつき値を算出する数式であるばらつきモデルを作成する。ばらつきモデルとしては、例えば製造条件のばらつきを近似する分布関数モデルと該分布関数モデルの係数との組み合わせを用いることができる。
【０１６６】
尚、製造モデル作成工程で作成された製造モデル、及びばらつきモデル作成工程で作成されたばらつきモデルはデータベースＤＦ１に記憶される。これにより、製造モデル作成工程で作成された製造モデル、及びばらつきモデル作成工程で作成されたばらつきモデルを再利用することが可能となる。
【０１６７】
次に、ステップＳＦ４において、計算条件値作成手段により行なわれる計算条件値作成工程について説明する。すなわち、計算条件値作成工程においては、所定の製造条件が数値計算可能なデータとして表現された計算条件値を作成する。
【０１６８】
次に、ステップＳＦ５において、平均疑似構造生成手段により行なわれる平均疑似構造生成工程について説明する。すなわち、平均疑似構造生成工程においては、製造モデル作成工程で作成された製造モデルに計算条件値作成工程で作成された計算条件値を入力することにより、半導体装置の一の構成要素の形状又は誘電率、例えばＳＴＩの形状を求めた後、該一の構成要素の形状又は誘電率を用いて半導体装置の平均的構造が表現された平均疑似構造を生成する。
【０１６９】
次に、ステップＳＦ６において、ばらつき疑似構造生成手段により行なわれるばらつき疑似構造生成工程について説明する。すなわち、ばらつき疑似構造生成工程においては、ばらつきモデル作成工程で作成されたばらつきモデルに計算条件値作成工程で作成された計算条件値を入力することにより、所定の製造条件の複数のばらつき値を算出した後、該所定の製造条件の複数のばらつき値を製造モデル作成工程で作成された製造モデルに順次入力して得られる結果のそれぞれを用いて、半導体装置の構造のばらつきが表現された複数のばらつき疑似構造を生成する。
【０１７０】
次に、ステップＳＦ７において、容量計算手段により行なわれる容量計算工程について説明する。すなわち、容量計算工程においては、平均疑似構造生成工程で生成された平均疑似構造に基づき、半導体装置の所定部分の容量の平均値、例えばＳＴＩの容量の平均値を計算すると共に、ばらつき疑似構造生成工程で生成された複数のばらつき疑似構造のそれぞれに基づき、半導体装置の所定部分の容量の複数のばらつき値、例えばＳＴＩの容量の複数のばらつき値を計算する。
【０１７１】
第５の実施形態によると、製造モデル作成工程において、一の構成要素の形状又は誘電率の、所定の製造条件に対する依存関係が表現された製造モデルを作成すると共に、計算条件値作成工程において、所定の製造条件が数値計算可能なデータとして表現された計算条件値を作成した後、平均疑似構造生成工程において、製造モデルに計算条件値を入力して一の構成要素の形状又は誘電率を求めると共に該一の構成要素の形状又は誘電率を用いて平均疑似構造を生成するため、一の構成要素の形状又は誘電率が正確に表現された平均疑似構造を生成できるので、半導体装置の所定部分の容量の平均値を正確に計算することができる。
【０１７２】
また、第５の実施形態によると、ばらつきモデル作成工程において、半導体装置の所定の製造条件に基づき該所定の製造条件の複数のばらつき値を算出するばらつきモデルを作成した後、ばらつき疑似構造生成工程において、ばらつきモデルに計算条件値を入力して所定の製造条件の複数のばらつき値を算出すると共に、該所定の製造条件の複数のばらつき値を製造モデルに順次入力して得られる結果のそれぞれを用いて、半導体装置の構造のばらつきが表現された複数のばらつき疑似構造を生成するため、所定の製造条件のばらつき値に対応する半導体装置の構造のばらつきが正確に表現された複数のばらつき疑似構造を生成できるので、半導体装置の所定部分の容量のばらつきを正確に計算することができる。
【０１７３】
（第６の実施形態）
以下、本発明の第６の実施形態に係る容量計算装置及び容量計算方法について、図面を参照しながら説明する。
【０１７４】
図２０は第６の実施形態に係る容量計算方法のフロー図である。
【０１７５】
まず、ステップＳＧ１において、製造工程指定手段により行なわれる製造工程指定工程について説明する。すなわち、製造工程指定工程においては、半導体装置の製造工程の種類及び実施順序を指定する。
【０１７６】
次に、ステップＳＧ２において、製造モデル作成手段により行なわれる製造モデル作成工程について説明する。すなわち、製造モデル作成工程においては、製造工程指定工程で指定された製造工程を所定の製造条件下において再現できる数式である製造モデル、例えば基板表面からの不純物の移動距離又は不純物濃度等の、所定の製造条件（酸化時間又はエッチングレート等）に対する依存関係が表現された製造モデルを作成する。
【０１７７】
次に、ステップＳＧ３において、ばらつきモデル作成手段により行なわれるばらつきモデル作成工程について説明する。すなわち、ばらつきモデル作成工程においては、所定の製造条件に基づき、該所定の製造条件の複数のばらつき値を算出する数式であるばらつきモデルを作成する。ばらつきモデルとしては、例えば製造条件のばらつきを近似する分布関数モデルと該分布関数モデルの係数との組み合わせを用いることができる。
【０１７８】
尚、製造モデル作成工程で作成された製造モデル、及びばらつきモデル作成工程で作成されたばらつきモデルはデータベースＤＧ１に記憶される。これにより、製造モデル作成工程で作成された製造モデル、及びばらつきモデル作成工程で作成されたばらつきモデルを再利用することが可能となる。
【０１７９】
次に、ステップＳＧ４において、計算条件値作成手段により行なわれる計算条件値作成工程について説明する。すなわち、計算条件値作成工程においては、所定の製造条件が数値計算可能なデータとして表現された計算条件値を作成する。
【０１８０】
次に、ステップＳＧ５において、平均疑似構造生成手段により行なわれる平均疑似構造生成工程について説明する。すなわち、平均疑似構造生成工程においては、製造モデル作成工程で作成された製造モデルに計算条件値作成工程で作成された計算条件値を入力することにより、半導体装置の製造工程を再現した後、該製造工程を再現した結果を用いて半導体装置の平均的構造が表現された平均疑似構造を生成する。
【０１８１】
次に、ステップＳＧ６において、ばらつき疑似構造生成手段により行なわれるばらつき疑似構造生成工程について説明する。すなわち、ばらつき疑似構造生成工程においては、ばらつきモデル作成工程で作成されたばらつきモデルに計算条件値作成工程で作成された計算条件値を入力することにより、所定の製造条件の複数のばらつき値を算出した後、該所定の製造条件の複数のばらつき値を製造モデル作成工程で作成された製造モデルに順次入力して得られる結果のそれぞれを用いて、半導体装置の構造のばらつきが表現された複数のばらつき疑似構造を生成する。
【０１８２】
次に、ステップＳＧ７において、容量計算手段により行なわれる容量計算工程について説明する。すなわち、容量計算工程においては、平均疑似構造生成工程で生成された平均疑似構造に基づき、半導体装置の所定部分の容量の平均値を計算すると共に、ばらつき疑似構造生成工程で生成された複数のばらつき疑似構造のそれぞれに基づき、半導体装置の所定部分の容量の複数のばらつき値を計算する。
【０１８３】
第６の実施形態によると、製造モデル作成工程において、半導体装置の製造工程を所定の製造条件下において再現できる製造モデルを作成すると共に、計算条件値作成工程において、所定の製造条件が数値計算可能なデータとして表現された計算条件値を作成した後、平均疑似構造生成工程において、製造モデルに計算条件値を入力して半導体装置の製造工程を再現すると共に該製造工程を再現した結果を用いて平均疑似構造を生成するため、製造工程に対応して変化する半導体装置の構造が正確に表現された平均疑似構造を生成できるので、半導体装置の所定部分の容量の平均値を正確に計算することができる。
【０１８４】
また、第６の実施形態によると、ばらつきモデル作成工程において、半導体装置の所定の製造条件に基づき該所定の製造条件の複数のばらつき値を算出するばらつきモデルを作成した後、ばらつき疑似構造生成工程において、ばらつきモデルに計算条件値を入力して所定の製造条件の複数のばらつき値を算出すると共に、該所定の製造条件の複数のばらつき値を製造モデルに順次入力して得られる結果のそれぞれを用いて、半導体装置の構造のばらつきが表現された複数のばらつき疑似構造を生成するため、所定の製造条件のばらつき値に対応する半導体装置の構造のばらつきが正確に表現された複数のばらつき疑似構造を生成できるので、半導体装置の所定部分の容量のばらつきを正確に計算することができる。
【０１８５】
（第７の実施形態）
以下、本発明の第７の実施形態に係る容量計算装置及び容量計算方法について、トランジスタ素子に生じる空乏層の容量の計算を例として、図面を参照しながら説明する。
【０１８６】
図２１は第７の実施形態に係る容量計算方法のフロー図である。
【０１８７】
まず、ステップＳＨ１において、使用状態指定手段により行なわれる使用状態指定工程について説明する。すなわち、使用状態指定工程において、半導体装置を使用する際の使用状態、例えばトランジスタの各電極に電圧を与えると共に半導体基板を接地するというような使用状態を指定する。
【０１８８】
図２２は、電圧を印加していない状態における空乏層を含むトランジスタ素子の一例を示す断面図である。図２２において、７００は半導体基板、７０１はソース・ドレイン領域、７０２はゲート絶縁膜、７０３はゲート電極、７０４はソース・ドレイン電極、７０５は空乏層を示している。また、図２２において、太い実線はチャネル領域とソース領域（又はドレイン領域）とのジャンクションを示しており、白い丸印は電子を示しており、黒い丸印は正孔を示している。
【０１８９】
図２３は、図２２に示すトランジスタ素子に電圧を印加したときの、空乏層の位置及び幅、又はジャンクションの位置の変化の様子を示す図である。
【０１９０】
図２３に示すように、トランジスタ素子に電圧を印加すると、空乏層及びジャンクションの位置が深くなると共に空乏層の幅が拡がる。
【０１９１】
次に、ステップＳＨ２において、使用モデル作成手段により行なわれる使用モデル作成工程について説明する。すなわち、使用モデル作成工程においては、使用状態指定工程で指定された使用状態を所定の使用条件下において再現できる数式である使用モデル、例えば空乏層の形状又はジャンクション位置等の、所定の使用条件（トランジスタの各電極に印加される電圧の高さ等）に対する依存関係が表現された使用モデル、つまり不純物移動度の電界強度に対する依存関係が表現された使用モデルを作成する。
【０１９２】
尚、使用モデル作成工程で作成された使用モデルは、データベースＤＨ１に記憶される。これにより、使用モデル作成工程で作成された使用モデルを再利用することが可能となる。
【０１９３】
次に、ステップＳＨ３において、計算条件値作成手段により行なわれる計算条件値作成工程について説明する。すなわち、計算条件値作成工程においては、所定の使用条件が数値計算可能なデータとして表現された計算条件値を作成する。
【０１９４】
次に、ステップＳＨ４において、疑似構造生成手段により行なわれる疑似構造生成工程について説明する。すなわち、疑似構造生成工程においては、使用モデル作成工程で作成された使用モデルに計算条件値作成工程で作成された計算条件値を入力することにより、半導体装置の使用状態を再現した後、該使用状態を再現した結果を用いて疑似構造を生成する。
【０１９５】
次に、ステップＳＨ５において、容量計算手段により行なわれる容量計算工程について説明する。すなわち、容量計算工程においては、疑似構造生成工程で生成された疑似構造に基づき、半導体装置の所定部分の容量を計算する。
【０１９６】
第７の実施形態によると、使用モデル作成工程において、半導体装置の使用状態を所定の使用条件下において再現できる使用モデルを作成すると共に、計算条件値作成工程において、所定の使用条件が数値計算可能なデータとして表現された計算条件値を作成した後、疑似構造生成工程において、使用モデル作成工程で作成された使用モデルに計算条件値作成工程で作成された計算条件値を入力して半導体装置の使用状態を再現すると共に、該使用状態を再現した結果を用いて疑似構造を生成するため、使用状態に対応して変化する半導体装置の構造が正確に表現された疑似構造を生成できるので、容量計算の精度を向上させることができる。また、計算条件値の変更により色々な疑似構造を簡単に生成できるので、容量計算を簡単化することができる。
【０１９７】
（第８の実施形態）
以下、本発明の第８の実施形態に係る容量計算装置及び容量計算方法について、図面を参照しながら説明する。
【０１９８】
尚、本実施形態に係る容量計算装置は、第１〜７の実施形態において作成された形状モデル、誘電率モデル、製造モデル、又は使用モデルを用いて、半導体装置の所定部分の容量を計算する手段を備えていると共に、予め作成された形状モデル、誘電率モデル、製造モデル、又は使用モデルが十分に蓄積されたデータベースを備えているものとする。
【０１９９】
図２４は第８の実施形態に係る容量計算方法のフロー図である。
【０２００】
まず、ステップＳＩ１において、計算条件値群作成手段により行なわれる計算条件値群作成工程について説明する。すなわち、計算条件値群作成工程においては、形状モデル若しくは誘電率モデルを用いる場合、半導体装置における所定の構成要素の形状又は電気的特性が、製造モデルを用いる場合、所定の製造条件が、使用モデルを用いる場合、所定の使用条件が、それぞれ数値計算可能なデータとして表現された計算条件値を作成する。
【０２０１】
尚、計算条件値群作成工程においては、複数の計算条件値を計算条件値群として順次入力する。
【０２０２】
次に、ステップＳＩ２において、疑似構造生成手段により行なわれる疑似構造生成工程について説明する。すなわち、疑似構造生成工程においては、形状モデル若しくは誘電率モデルを用いる場合、データベースＤＩ１から抽出された形状モデル若しくは誘電率モデルに、製造モデルを用いる場合、データベースＤＩ２から抽出された製造モデルに、使用モデルを用いる場合、データベースＤＩ３から抽出された使用モデルに、計算条件値群作成工程で作成された複数の計算条件値を順次入力して得られる結果のそれぞれを用いて複数の疑似構造を生成する。
【０２０３】
次に、ステップＳＩ３において、容量計算手段により行なわれる容量計算工程について説明する。すなわち、容量計算工程においては、疑似構造生成工程で生成された複数の疑似構造のそれぞれに基づき、半導体装置の所定部分の複数の容量を計算する。
【０２０４】
次に、ステップＳＩ４において、容量値関数作成手段により行なわれる容量値関数作成工程について説明する。すなわち、容量値関数作成工程においては、例えば最小二乗法等の近似方法を用いることにより、計算条件値群作成工程で作成された複数の計算条件値と、容量計算工程で計算された複数の容量の値との相関関係が表現された関数である容量値関数を作成する。
【０２０５】
尚、容量値関数作成工程で作成された容量値関数は、データベースＤＩ４に記憶される。これにより、容量値関数作成工程で作成された容量値関数を再利用することが可能となる。
【０２０６】
次に、ステップＳＩ５において、計算条件値作成手段により行なわれる計算条件値作成工程について説明する。すなわち、計算条件値作成工程においては、半導体装置における所定の構成要素の形状若しくは電気的特性、所定の製造条件、又は所定の使用条件が数値計算可能なデータとして表現された計算条件値を作成する。
【０２０７】
次に、ステップＳＩ６において、簡易容量計算手段により行なわれる簡易容量計算工程について説明する。すなわち、簡易容量計算工程においては、容量値関数作成工程で作成された容量値関数に計算条件値作成工程で作成された計算条件値を入力することにより、半導体装置の所定部分の容量を計算する。
【０２０８】
第８の実施形態によると、容量値関数作成工程において、計算条件値群作成工程で作成された複数の計算条件値と、容量計算工程で計算された半導体装置の所定部分の複数の容量の値との相関関係が表現された容量値関数を作成した後、簡易容量計算工程において、容量値関数作成工程で作成された容量値関数を用いて、半導体装置の所定部分の容量を計算するため、疑似構造を生成することなく容量値関数を用いて容量計算を行なうことができるので、容量計算を簡単化することができる。尚、通常、容量値関数作成工程と簡易容量計算工程とが連続的に行なわれることはなく、簡易容量計算工程においては、予め作成され、データベース等に蓄積されている容量値関数が用いられる。
【０２０９】
また、第８の実施形態によると、形状モデル、誘電率モデル、製造モデル、又は使用モデルを用いて容量計算を行なった結果に基づき容量値関数を作成しているため、該容量値関数を用いて容量計算を行なうことにより、半導体装置の製造工程から使用段階にかけての容量のばらつきの予測等を簡単に行なうことができる。
【０２１０】
（第９の実施形態）
以下、本発明の第９の実施形態に係る容量計算装置及び容量計算方法について、図面を参照しながら説明する。
【０２１１】
尚、本実施形態に係る容量計算装置は、第８の実施形態と同様に、第１〜７の実施形態において作成された形状モデル、誘電率モデル、製造モデル、又は使用モデルを用いて、半導体装置の所定部分の容量を計算する手段を備えていると共に、予め作成された形状モデル、誘電率モデル、製造モデル、又は使用モデルが十分に蓄積されたデータベースを備えているものとする。
【０２１２】
図２５は第９の実施形態に係る容量計算方法のフロー図である。
【０２１３】
まず、ステップＳＪ１において、目標容量値入力手段により行なわれる目標容量値入力工程について説明する。すなわち、目標容量値入力工程においては、後の容量計算工程で計算される容量の値である計算容量値の目標値となる目標容量値、及び計算容量値と目標容量値との間の許容差を入力する。ここで、許容差としては、例えば目標容量値と所定の係数とが積算された値等を用いる。
【０２１４】
次に、ステップＳＪ２において、計算条件値設定手段により行なわれる計算条件値設定工程について説明する。すなわち、計算条件値群作成工程においては、形状モデル若しくは誘電率モデルを用いる場合、半導体装置における所定の構成要素の形状又は電気的特性が、製造モデルを用いる場合、所定の製造条件が、使用モデルを用いる場合、所定の使用条件が、それぞれ数値計算可能なデータとして表現された計算条件値を作成する。このとき、計算容量値が目標容量値に等しくなるように計算条件値が決定される。
【０２１５】
尚、計算条件値作成工程においては、計算容量値と目標容量値との間の差である容量値差が、目標容量値入力工程で入力された許容差よりも小さくなるまで、計算条件値が繰り返し変更されると共に、最初の計算条件値作成工程おいては、計算条件値の初期値として所定値が用いられる。
【０２１６】
次に、ステップＳＪ３において、疑似構造生成手段により行なわれる疑似構造生成工程について説明する。すなわち、疑似構造生成工程においては、形状モデル若しくは誘電率モデルを用いる場合、データベースＤＪ１から抽出された形状モデル若しくは誘電率モデルに、製造モデルを用いる場合、データベースＤＪ２から抽出された製造モデルに、使用モデルを用いる場合、データベースＤＪ３から抽出された使用モデルに、計算条件値作成工程で作成された計算条件値を入力して得られる結果を用いて疑似構造を生成する。
【０２１７】
次に、ステップＳＪ４において、容量計算手段により行なわれる容量計算工程について説明する。すなわち、容量計算工程においては、疑似構造生成工程で生成された疑似構造に基づき、半導体装置の所定部分の容量を計算する。
【０２１８】
次に、ステップＳＪ５において、容量値差計算手段により行なわれる容量値差計算工程について説明する。すなわち、容量値差計算工程においては、容量計算工程で計算された容量の値である計算容量値と、目標容量値入力工程で入力された目標容量値との差の絶対値である容量値差を計算する。
【０２１９】
次に、ステップＳＪ６において、容量値差判定手段により行なわれる容量値差判定工程について説明する。すなわち、容量値差判定工程においては、容量値差計算工程で計算された容量値差が、目標容量値入力工程で入力された許容差よりも小さいか否かの判断をする。容量値差が許容差よりも小さければ、ステップＳＪ７に進み、容量値差が許容差よりも小さくなければ、ステップＳＪ２に戻る。
【０２２０】
次に、ステップＳＪ７において、疑似構造出力手段により行なわれる疑似構造出力工程について説明する。すなわち、疑似構造出力工程においては、容量値差計算工程で計算された容量値差が、目標容量値入力工程で入力された許容差よりも小さい場合における、すなわち計算容量値が目標容量値に略等しい場合における、該計算容量値の算出に用いられた疑似構造を出力する。このとき、該疑似構造に加えて、該疑似構造の生成に用いられた計算条件値、例えば製造条件等を出力してもよい。
【０２２１】
第９の実施形態によると、容量計算工程において計算された半導体装置の所定部分の容量の値である計算容量値が、目標容量値入力工程において入力された目標容量値に略等しくなるまで、計算条件値作成工程、疑似構造生成工程、及び容量計算工程を、計算条件値作成工程において計算条件値を変更しながら繰り返し行なうため、計算容量値が目標容量値に略等しくなった場合において、該計算容量値の算出に用いられた疑似構造、又は該疑似構造の生成に用いられた計算条件値を出力することにより、半導体装置の所定部分の容量の値が目標容量値に略等しくなるときの半導体装置の構造又は製造条件等を知ることができる。
【０２２２】
【発明の効果】
第１の容量計算装置によると、絶縁層の形状が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２２３】
第２の容量計算装置によると、半導体装置における一の構成要素の形状が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２２４】
第３の容量計算装置によると、半導体装置における一の構成要素の誘電率が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２２５】
第４の容量計算装置によると、使用状態に対応して変化する半導体装置の構造が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２２６】
第５の容量計算装置によると、半導体装置における一の構成要素の形状又は誘電率が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２２７】
第６の容量計算装置によると、製造工程に対応して変化する半導体装置の構造が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２２８】
第２〜第６の容量計算装置において、計算条件値作成手段が作成した複数の計算条件値と、容量計算手段が計算した半導体装置の所定部分の複数の容量の値との相関関係が表現された容量値関数を作成する容量値関数作成手段と、容量値関数作成手段が作成した容量値関数を用いて、半導体装置の所定部分の容量を計算する簡易容量計算手段とを備えていると、疑似構造を生成することなく容量値関数を用いて容量計算を行なうことができるため、容量計算を簡単化することができる。
【０２２９】
第２〜第６の容量計算装置において、計算条件値作成手段が、容量計算手段が計算した半導体装置の所定部分の容量の値が所定値に略等しくなるなるまで、計算条件値を繰り返し変更すると、半導体装置の所定部分の容量の値が所定値に略等しくなった場合において、該容量の値の算出に用いられた疑似構造、又は該疑似構造の生成に用いられた計算条件値を出力することにより、半導体装置の所定部分の容量の値が所定値に略等しくなるときの半導体装置の構造又は製造条件等を知ることができる。
【０２３０】
第５又は第６の容量計算装置において、所定の製造条件に基づき、該所定の製造条件の複数のばらつき値を算出するばらつきモデルを作成するばらつきモデル作成手段を備えており、疑似構造生成手段が、ばらつきモデルに計算条件値を入力して所定の製造条件の複数のばらつき値を算出すると共に、該所定の製造条件の複数のばらつき値を製造モデルに順次入力して得られる結果のそれぞれを用いて、半導体装置の構造のばらつきが表現された複数のばらつき疑似構造を生成すると、所定の製造条件のばらつき値に対応する半導体装置の構造のばらつきが正確に表現された複数のばらつき疑似構造を生成できるため、半導体装置の所定部分の容量のばらつきを正確に計算することができる。
【０２３１】
第６の容量計算装置において、計算条件値作成手段が、疑似構造生成手段が生成する疑似構造が所定の疑似構造に等しくなるように、所定の製造条件を決定すると、所定の構造を有する半導体装置について容量計算を行なうことができる。
【０２３２】
第１の容量計算方法によると、絶縁層の形状が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２３３】
第２の容量計算方法によると、半導体装置における一の構成要素の形状が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２３４】
第３の容量計算方法によると、半導体装置における一の構成要素の誘電率が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２３５】
第４の容量計算方法によると、使用状態に対応して変化する半導体装置の構造が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２３６】
第５の容量計算方法によると、半導体装置における一の構成要素の形状又は誘電率が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２３７】
第６の容量計算方法によると、製造工程に対応して変化する半導体装置の構造が正確に表現された疑似構造を生成できるため、容量計算の精度を向上させることができると共に、計算条件値の変更により色々な疑似構造を簡単に生成できるため、容量計算を簡単化することができる。
【０２３８】
第２〜第６の容量計算方法において、計算条件値作成工程において作成された複数の計算条件値と、容量計算工程において計算された半導体装置の所定部分の複数の容量の値との相関関係が表現された容量値関数を作成する容量値関数作成工程と、容量値関数作成工程において作成された容量値関数を用いて、半導体装置の所定部分の容量を計算する簡易容量計算工程とを備えていると、疑似構造を生成することなく容量値関数を用いて容量計算を行なうことができるため、容量計算を簡単化することができる。尚、実際の運用上、容量値関数作成工程と簡易容量計算工程とが連続的に行なわれることはなく、簡易容量計算工程においては、予め作成され、データベース等に蓄積されている容量値関数が用いられる。
【０２３９】
第２〜第６の容量計算方法において、計算条件値作成工程、疑似構造生成工程、及び容量計算工程を、容量計算工程において計算された半導体装置の所定部分の容量の値が所定値に略等しくなるまで、計算条件値作成工程において計算条件値を変更しながら繰り返し行なう繰り返し工程を備えていると、半導体装置の所定部分の容量の値が所定値に略等しくなった場合において、該容量の値の算出に用いられた疑似構造、又は該疑似構造の生成に用いられた計算条件値を出力することにより、半導体装置の所定部分の容量の値が所定値に略等しくなるときの半導体装置の構造又は製造条件等を知ることができる。
【０２４０】
第５又は第６の容量計算方法において、所定の製造条件に基づき、該所定の製造条件の複数のばらつき値を算出するばらつきモデルを作成するばらつきモデル作成工程を備えており、疑似構造生成工程が、ばらつきモデルに計算条件値を入力して所定の製造条件の複数のばらつき値を算出した後、該所定の製造条件の複数のばらつき値を製造モデルに順次入力して得られる結果のそれぞれを用いて、半導体装置の構造のばらつきが表現された複数のばらつき疑似構造を生成すると、所定の製造条件のばらつき値に対応する半導体装置の構造のばらつきが正確に表現された複数のばらつき疑似構造を生成できるため、半導体装置の所定部分の容量のばらつきを正確に計算することができる。
【０２４１】
第６の容量計算方法において、計算条件値作成工程が、疑似構造生成工程において生成された疑似構造が所定の疑似構造に等しくなるように、所定の製造条件を決定する工程を含むと、所定の構造を有する半導体装置について容量計算を行なうことができる。
【図面の簡単な説明】
【図１】第１の実施形態に係る容量計算方法のフロー図である。
【図２】前記の容量計算方法における形状モデル作成工程の各処理を説明する図である。
【図３】前記の容量計算方法において、ボイドを含む配線部の構造が表現された疑似構造の一例を示す断面図である。
【図４】前記の容量計算方法において、ボイドの形状を実測したデータをプロットした図である。
【図５】前記の容量計算方法において、ボイドの形状の配線間隔に対する依存関係が表現された形状モデルを示す図である。
【図６】前記の容量計算方法における疑似構造生成工程の各処理を説明する図である。
【図７】前記の容量計算方法における疑似構造生成工程において生成された疑似構造の一例を示す断面図である。
【図８】第２の実施形態に係る容量計算方法のフロー図である。
【図９】前記の容量計算方法における疑似構造生成工程において生成された疑似構造の一例を示す断面図である。
【図１０】第３の実施形態に係る容量計算方法のフロー図である。
【図１１】前記の容量計算方法において、空乏層を含むトランジスタ素子の一例を示す断面図である。
【図１２】前記の容量計算方法における疑似構造生成工程において生成された疑似構造の一例を示す断面図である。
【図１３】第３の実施形態の変形例に係る容量計算方法のフロー図である。
【図１４】前記の容量計算方法において、空乏層を含むトランジスタ素子の構造が表現された疑似構造の一例を示す断面図である。
【図１５】前記の容量計算方法において、空乏層を定義する方法の一例を示す図である。
【図１６】第４の実施形態に係る容量計算方法のフロー図である。
【図１７】第５の実施形態に係る容量計算方法のフロー図である。
【図１８】前記の容量計算方法において、ＳＴＩの一例を示す断面図である。
【図１９】前記の容量計算方法において、ＳＴＩの幅のばらつきの一例を示す図である。
【図２０】第６の実施形態に係る容量計算方法のフロー図である。
【図２１】第７の実施形態に係る容量計算方法のフロー図である。
【図２２】前記の容量計算方法において、電圧を印加していない状態における空乏層を含むトランジスタ素子の一例を示す断面図である。
【図２３】前記の容量計算方法において、トランジスタ素子に電圧を印加したときの、空乏層の位置及び幅、又はジャンクションの位置の変化の様子を示す図である。
【図２４】第８の実施形態に係る容量計算方法のフロー図である。
【図２５】第９の実施形態に係る容量計算方法のフロー図である。
【図２６】従来の容量計算方法において、配線構造の一例を示す立体図である。
【図２７】従来の容量計算方法において、配線容量シミュレーションに用いられる疑似構造の一例を示す断面図である。
【図２８】従来の容量計算方法において、ＭＯＳトランジスタの一例を示す断面図である。
【図２９】従来の容量計算方法において、２つのトランジスタ素子を分離するＳＴＩの一例を示す断面図である。
【図３０】従来の容量計算方法において、配線構造の一例を示す断面図である。
【符号の説明】
１００ 第１の配線層
１０１ 第２の配線層
１０２ 第１の層間絶縁膜
１０２ａ 第１の層間絶縁膜のテーパ部
１０３ 第２の層間絶縁膜
１０４ パッシベーション膜
１０４ａ ボイド
１１０ 第１の配線層
１１１ 第２の配線層
１１２ 第１の層間絶縁膜
１１３ 第２の層間絶縁膜
１１４ パッシベーション膜
１１４ａ ボイド
２００ 第１の配線層
２０１ 第２の配線層
２０２ 第１の層間絶縁膜
２０３ 第２の層間絶縁膜
２０４ パッシベーション膜
２０４ａ ボイド
３００ 半導体基板
３００ａ 半導体基板の表面
３０１ ソース・ドレイン領域
３０２ ゲート絶縁膜
３０３ ゲート電極
３０４ 空乏層
３１０ 半導体基板
３１０ａ 半導体基板の表面
３１１ ソース・ドレイン領域
３１２ ゲート絶縁膜
３１３ ゲート電極
３１４ 空乏層
３２０ 半導体基板
３２０ａ 半導体基板の表面
３２１ ソース・ドレイン領域
３２２ ゲート絶縁膜
３２３ ゲート電極
３２４ 空乏層
５００ 半導体基板
５０１ ソース・ドレイン領域
５０２ ゲート絶縁膜
５０３ ゲート電極
５０４ ＳＴＩ
７００ 半導体基板
７０１ ソース・ドレイン領域
７０２ ゲート絶縁膜
７０３ ゲート電極
７０４ ソース・ドレイン電極
７０５ 空乏層
ａ ジャンクション位置
ｂ 空乏層の厚さ
ｃ 空乏層の厚さ
ｄ ＳＴＩの幅
ｅ ＳＴＩの高さ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a capacity calculation apparatus and a capacity calculation method for calculating the capacity of a component of a semiconductor device.
[0002]
[Prior art]
In the manufacture of a semiconductor device, the capacitance of a wiring portion formed by laminating a wiring layer and an insulating layer, a depletion layer generated in a transistor element, or a trench type element isolation insulating film has a great influence on the operating characteristics or quality of the semiconductor device. It is.
[0003]
Hereinafter, a method for calculating the wiring capacity, which is the capacity of the wiring part, will be described first. In the following description, the wiring layer is formed of a conductive thin film and refers to a structure in which a current flows by a voltage applied from the outside, and the insulating layer is formed of a dielectric film having a capacity. This means a structure part that electrically insulates the wiring layers, that is, an interlayer insulating film.
[0004]
Along with the rapid miniaturization of the manufacturing process of semiconductor devices in recent years, in the wiring layer forming process, the wiring width and the wiring spacing which is the spacing between adjacent wiring layers are miniaturized and the wiring layers are required to be multilayered. . As a result, the wiring capacitance and wiring resistance increase, and the transmission of electrical signals in the semiconductor integrated circuit is delayed. Therefore, it is necessary to design the circuit in consideration of the wiring capacitance and wiring resistance. However, in circuit design, it is indispensable to accurately predict the wiring capacitance and wiring resistance generated in the wiring portion, while it is difficult to predict the wiring capacitance and wiring resistance based on experience or measurement. For this reason, computer simulation is widely used to predict wiring capacitance or wiring resistance. Here, simulation refers to performing a numerical solution in order to solve a theoretical formula by giving physical condition values, and a simulator is a computer software in which the simulation method is summarized as a series of procedures on a computer. It shall be said.
[0005]
In circuit design, in particular, wiring capacity prediction, it is necessary to consider the dependency of the wiring capacity on the wiring interval, the wiring width, or the laminated structure of the wiring layers. However, it is required to predict the wiring capacity for the structure of the wiring portion, that is, the wiring structure by changing the wiring interval, the wiring width, or the laminated structure of the wiring layer in various ways. As the number of wiring structures to be predicted increases, the number of calculation steps required for a simulation for predicting wiring capacity (hereinafter referred to as wiring capacity simulation) has become enormous.
[0006]
Therefore, a current general wiring capacity simulator for performing wiring capacity simulation has a database function for creating a database of wiring capacity values calculated by wiring capacity simulation.
[0007]
In the wiring capacity simulation, the capacity calculation is performed based on a pseudo structure in which the actual wiring structure is expressed as data that can be numerically calculated. The pseudo structure is composed of prototype data and shape determination values. The prototype data is a figure that approximates each component of the actual wiring structure, for example, a shape type that is a simple figure type such as a square or a triangle, and an actual type. It is data consisting of the relative positional relationship between each component of the wiring structure, and the shape determination value is the length or angle of the side in the figure that approximates each component of the actual wiring structure specified by the shape type, etc. And data consisting of relative distances between the components of the actual wiring structure.
[0008]
In the wiring capacity simulator, a plurality of pseudo structures are automatically generated, and a wiring capacity simulation is automatically performed based on each of the generated pseudo structures. The capacity value can be stored in the database as a series of data. Thereby, for example, the dependency of the wiring capacitance on the wiring interval or the wiring width can be examined.
[0009]
By the way, when forming the wiring portion, a uniform interlayer insulating film is formed between a plurality of wiring layers having a laminated structure to insulate the wiring layers and planarize the surface of the interlayer insulating film. A method of forming an upper wiring layer is generally used. For this reason, in the wiring capacitance simulator, a pseudo structure is generated based on the premise that the interlayer insulating film formed between the wiring layers is homogeneous and the surface of the interlayer insulating film is flat.
[0010]
FIG. 26 is a diagram illustrating an example of a wiring structure. In the wiring capacity simulation, an electric potential such as an electric field vector generated in the wiring structure is calculated, then the electric potential is decomposed in each direction, and each component of the decomposed electric potential is calculated as a wiring capacity component. In FIG. 26, C1, C2, and C3 respectively indicate side coupling capacitance, fringe capacitance, and overlap capacitance, which are one of the wiring capacitance components.
[0011]
FIG. 27 is a two-dimensional sectional view showing an example of a conventional pseudo structure used for wiring capacity simulation. In FIG. 27, 10 denotes a wiring layer made of a conductive thin film, and 11 denotes an interlayer insulating film made of a dielectric thin film. In FIG. 27, a portion surrounded by a thick solid line indicates an analysis region to be subjected to one wiring capacity simulation. As shown in FIG. 27, the shape of the wiring layer 10 and the interlayer insulating film 11 is a rectangle composed of sides perpendicular or parallel to the thick solid line indicating the analysis region. A pseudo structure in which the structure of the semiconductor device is expressed by a combination of simple figures is called a basic planar structure.
[0012]
Hereinafter, a method for calculating the capacitance of the depletion layer generated in the vicinity of the gate electrode of the MOS transistor will be described.
[0013]
FIG. 28 is a cross-sectional view showing an example of a MOS transistor. In FIG. 28, 20 is a semiconductor substrate, 21 is a source / drain region, 22 is a gate insulating film, 23 is a gate electrode, and 24 is a depletion layer. In FIG. 28, a thick solid line indicates a junction between a channel region and a source region (or drain region), a white circle indicates an electron, and a black circle indicates a hole.
[0014]
Since the concentration of electrons or holes (hereinafter collectively referred to as carriers) in the depletion layer, that is, the conductivity of the depletion layer is extremely low, a capacity is generated in the depletion layer.
[0015]
The capacity calculation of the depletion layer has been conventionally performed according to the procedure described below.
[0016]
(1) After representing the structure of the transistor element to be subjected to capacitance calculation one by one as shape data that can be numerically calculated, the shape data is stored in a computer.
[0017]
(2) Information such as the impurity concentration of the semiconductor substrate is added to the shape data. This impurity concentration defines a region having one conductivity type and a region having another conductivity type in the semiconductor substrate.
[0018]
(3) By calculating the amount of migration of impurities when a voltage is applied to the junction surface between the region having one conductivity type and the region having another conductivity type, that is, both sides of the junction, the depletion layer formed near the junction is calculated. After obtaining the shape, the capacity of the depletion layer is calculated using the shape of the depletion layer.
[0019]
Hereinafter, a method for calculating the capacitance of the thin trench element isolation insulating film (hereinafter referred to as STI) will be described. With the recent miniaturization of semiconductor devices, the capacity of STI is becoming ignorable.
[0020]
FIG. 29 is a cross-sectional view showing an example of an STI that separates two transistor elements. In FIG. 29, 30 is a semiconductor substrate, 31 is a source / drain region, 32 is a gate insulating film, 33 is a gate electrode, and 34 is STI.
[0021]
In the conventional STI capacity calculation, the capacity calculation similar to that of the depletion layer is performed for each STI structure to be subjected to the capacity calculation, or the capacity is estimated by hand calculation. .
[0022]
[Problems to be solved by the invention]
However, in the conventional capacitance calculation method for calculating the capacitance of the wiring portion or the like based on the pseudo structure, that is, the basic planar structure, with the miniaturization of the semiconductor device, the actual semiconductor device structure and the basic planar structure in which the structure is expressed. There is a problem that the accuracy of capacity calculation becomes insufficient due to an error between
[0023]
The error between the actual semiconductor device structure and the basic planar structure will be described below with reference to the drawings.
[0024]
FIG. 30 is a cross-sectional view schematically showing an example of an actual wiring portion. In FIG. 30, 40 is a first wiring layer as a lower layer, 41 is a second wiring layer as an upper layer, 42 is a first interlayer insulating film, 42a is a tapered portion of the first interlayer insulating film 42, 43 is The second interlayer insulating film 44 is a passivation film for protecting the second wiring layer 41, and 44 a is a void generated in the passivation film 44. Different types of interlayer insulating films, that is, the first interlayer insulating film 42 and the second interlayer insulating film 43 are laminated between the first wiring layer 40 and the second wiring layer 41. This is to improve the chemical stability on the surface of the wiring layer while preventing the dielectric constant of the entire film from increasing.
[0025]
As shown in FIG. 30, the surface of the second interlayer insulating film 43 is planarized, while the surface of the first interlayer insulating film 42 is not planarized. Specifically, anisotropic etching using a sputtering method is performed on the first interlayer insulating film 42 in order to remove voids generated when the first interlayer insulating film 42 is deposited. A part of the first interlayer insulating film 42 having the tapered portion 42a is formed on the wiring layer 40, and the second interlayer is formed over the entire surface of the first interlayer insulating film 42 including the tapered portion 42a. An interlayer insulating film 43 is deposited. At this time, the tapered portion 42a of the first interlayer insulating film 42 cannot be expressed using the basic planar structure. Further, the shape of the tapered portion 42 a of the first interlayer insulating film 42 changes with the wiring width of the first wiring layer 40.
[0026]
By the way, when an insulating film is formed by using a vapor deposition method or the like, a hollow structure or void may be formed in the insulating film depending on the vapor deposition shape of the insulating film material. On the other hand, the insulating property is deposited on the uppermost wiring layer. Voids generated in the thin film, that is, the passivation film are not usually removed. Specifically, as shown in FIG. 30, the void 44a generated in the passivation film 44 that protects the second wiring layer 41 is not removed. At this time, the void 44a cannot be expressed using the basic planar structure. Further, since the void 44 a is generated due to the protruding shape of the second wiring layer 41 in the passivation film 44, the shape of the void 44 a changes with the wiring interval of the second wiring layer 41.
[0027]
As described above, with the miniaturization of the semiconductor device, voids and the like generated in the taper portion of the interlayer insulating film or the passivation film cannot be ignored. On the other hand, in the conventional capacitance calculation method, the taper portion or passivation of the interlayer insulating film is not possible. Since the capacitance of the wiring portion and the like is calculated based on the basic planar structure that cannot express voids and the like generated in the film, there is a problem that the accuracy of the capacitance calculation becomes insufficient.
[0028]
In addition, for example, when calculating the capacitance such as a depletion layer or STI generated in a transistor element, each component of the semiconductor device that is the target of the capacitance calculation is expressed as shape data that can be numerically calculated. Since the capacity of the constituent elements of the semiconductor device is calculated using the shape data, there is a problem that the capacity calculation becomes complicated.
[0029]
In view of the above, an object of the present invention is to improve the accuracy of capacity calculation and simplify the capacity calculation.
[0030]
[Means for Solving the Problems]
In order to achieve the above object, a first capacitance calculation apparatus according to the present invention has a structure of a semiconductor device having a wiring portion in which a wiring layer made of a conductive film and an insulating layer made of a dielectric film are laminated. Based on a pseudo structure expressed as numerically computable data, a shape model that is a mathematical expression that expresses the dependency of the shape of the insulating layer on the shape of the wiring layer, assuming a capacitance calculation device that calculates the capacitance of the wiring part A shape model creating means for creating a calculation condition value creating at least a calculation condition value expressed as data capable of numerical calculation of the shape of the wiring layer, and a calculation condition value for the shape model created by the shape model creating means By inputting the calculation condition value created by the creating means, the shape of the insulating layer is obtained, and the pseudo structure generating means for generating the pseudo structure using the shape of the insulating layer, and the pseudo structure generating Based on the pseudo-structure stage it is generated, and a capacity calculating means for calculating the capacitance of the wiring portion.
[0031]
According to the first capacity calculation device, the shape model creating means creates a shape model in which the dependency of the shape of the insulating layer on the shape of the wiring layer is expressed, and the calculation condition value creating means includes the wiring layer Create a calculation condition value expressed as data whose shape can be numerically calculated, and the pseudo structure generation means inputs the calculation condition value created by the calculation condition value creation means to the shape model created by the shape model creation means In addition to determining the shape of the insulating layer and generating a pseudo structure using the shape of the insulating layer, it is possible to generate a pseudo structure that accurately represents the shape of the insulating layer, and various pseudo structures by changing the calculation condition values Can be generated easily.
[0032]
A second capacity calculation apparatus according to the present invention is a capacity calculation apparatus that calculates a capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device including a plurality of components is expressed as numerically calculable data. And a shape model creating means for creating a shape model that is a mathematical expression expressing the dependence of the shape of one component in the semiconductor device on the shape or electrical characteristics of another component in the semiconductor device, and at least Calculation condition value creation means for creating calculation condition values expressed as data that can numerically calculate the shape or electrical characteristics of other components, and calculation condition value creation means for the shape model created by the shape model creation means By inputting the calculated calculation condition value, the shape of one component is obtained, and the pseudo structure is generated using the shape of the one component. A generation unit, based on the pseudo-structure Pseudo structure generating means has generated, and a capacity calculating means for calculating the volume of the predetermined portion of the semiconductor device.
[0033]
According to the second capacity calculation device, the shape model creation means creates a shape model in which the dependency of the shape of one component on the shape or electrical characteristics of another component is expressed, and the calculation conditions The value creating means creates a calculation condition value expressed as data in which the shape or electrical characteristics of other components can be numerically calculated, and the pseudo structure creating means adds the shape model created by the shape model creating means to the shape model. Since the calculation condition value created by the calculation condition value creation means is input to obtain the shape of one component and the pseudo structure is generated using the shape of the one component, the shape of the one component is accurately The expressed pseudo structure can be generated, and various pseudo structures can be easily generated by changing the calculation condition value.
[0034]
A third capacity calculation apparatus according to the present invention is a capacity calculation apparatus that calculates a capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device including a plurality of components is expressed as numerically calculable data. And a dielectric constant model creating means for creating a dielectric constant model that is a mathematical expression expressing the dependence of the dielectric constant of one component in a semiconductor device on the shape or electrical characteristics of another component in the semiconductor device Calculation condition value creating means for creating a calculation condition value expressed as data capable of numerical calculation of at least the shape or electrical characteristics of other components, and a calculation condition in the dielectric constant model created by the dielectric constant model creating means By inputting the calculation condition value created by the value creating means, the dielectric constant of one component is obtained, and the pseudo structure is created using the dielectric constant of the one component. And a pseudo structure generation means for forming, based on the pseudo-structure Pseudo structure generating means has generated, and a capacity calculating means for calculating the volume of the predetermined portion of the semiconductor device.
[0035]
According to the third capacity calculation apparatus, the dielectric constant model creating means creates a dielectric constant model in which the dependence of the dielectric constant of one component on the shape or electrical characteristics of another component is expressed, and The calculation condition value creating means creates the calculation condition value expressed as data capable of numerically calculating the shape or electrical characteristics of other components, and the pseudo structure generating means is created by the dielectric constant model creating means. The calculation condition value created by the calculation condition value creating means is input to the obtained dielectric constant model to obtain the dielectric constant of one component, and the pseudo structure is generated using the dielectric constant of the one component. A pseudo structure in which the dielectric constants of the constituent elements are accurately expressed can be generated, and various pseudo structures can be easily generated by changing the calculation condition value.
[0036]
A fourth capacity calculation apparatus according to the present invention is a capacity calculation apparatus that calculates a capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device including a plurality of components is expressed as numerically calculable data. And a usage model creation means for creating a usage model that is a mathematical formula that can reproduce the usage state of a semiconductor device under a predetermined usage condition, and a calculation condition value that represents at least the predetermined usage condition as data that can be numerically calculated The calculation condition value creating means for creating the use condition and the calculation condition value created by the calculation condition value creating means are input to the use model created by the use model creating means to reproduce the use state of the semiconductor device and the use state Based on the pseudo structure generated by the pseudo structure generating means and the pseudo structure generating means for generating the pseudo structure using the result of reproducing And a capacity calculating means for calculating the volume of the part.
[0037]
According to the fourth capacity calculation apparatus, the use model creating means creates a use model that is a mathematical expression that can reproduce the use state of the semiconductor device under a predetermined use condition, and the calculation condition value creating means has a predetermined use. The calculation condition value expressed as data that can be numerically calculated is created, and the pseudo structure generation means inputs the calculation condition value created by the calculation condition value creation means to the use model created by the use model creation means. Since the pseudo structure is generated using the result of reproducing the use state of the semiconductor device and the result of reproducing the use state, the pseudo structure in which the structure of the semiconductor device changing according to the use state is accurately expressed can be generated. At the same time, various pseudo structures can be easily generated by changing the calculation condition value.
[0038]
A fifth capacity calculation apparatus according to the present invention is a capacity calculation apparatus that calculates a capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device including a plurality of components is expressed as numerically calculable data. And a manufacturing model creating means for creating a manufacturing model which is a mathematical expression expressing a dependency of a shape or dielectric constant of one component in a semiconductor device on a predetermined manufacturing condition in a manufacturing process of the semiconductor device, at least, Enter the calculation condition value created by the calculation condition value creation means into the production model created by the production model creation means and the calculation condition value creation means for creating the calculation condition values expressed as data that can be numerically calculated for the predetermined production conditions Thus, the shape or dielectric constant of one component is obtained, and the pseudo structure is generated using the shape or dielectric constant of the one component. A structure generation unit, based on the pseudo-structure Pseudo structure generating means has generated, and a capacity calculating means for calculating the volume of the predetermined portion of the semiconductor device.
[0039]
According to the fifth capacity calculating apparatus, the manufacturing model creating means creates a manufacturing model in which the dependency of the shape or dielectric constant of one component on a predetermined manufacturing condition is expressed, and the calculation condition value creating means However, a calculation condition value is generated in which a predetermined manufacturing condition is expressed as data that can be numerically calculated, and the pseudo structure generation means calculates the calculation model created by the calculation condition value creation means on the manufacturing model created by the manufacturing model creation means. By inputting the condition value to determine the shape or dielectric constant of one component and to generate a pseudo structure using the shape or dielectric constant of the one component, the shape or dielectric constant of one component is accurately The expressed pseudo structure can be generated, and various pseudo structures can be easily generated by changing the calculation condition value.
[0040]
A sixth capacity calculation apparatus according to the present invention is a capacity calculation apparatus that calculates the capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device composed of a plurality of components is expressed as numerically calculable data. Based on the above, a manufacturing model creating means for creating a manufacturing model that is a mathematical formula that can reproduce the manufacturing process of a semiconductor device under a predetermined manufacturing condition, and a calculation condition value that represents at least the predetermined manufacturing condition as data that can be numerically calculated The manufacturing condition of the semiconductor device is reproduced by inputting the calculation condition value created by the calculation condition value creating means into the manufacturing model created by the manufacturing model creating means and the calculation condition value creating means for creating the manufacturing process. Based on the pseudo structure generated by the pseudo structure generating means and the pseudo structure generating means for generating the pseudo structure using the result of reproducing And a capacity calculating means for calculating the volume of the part.
[0041]
According to the sixth capacity calculating apparatus, the manufacturing model creating means creates a manufacturing model capable of reproducing the manufacturing process of the semiconductor device under a predetermined manufacturing condition, and the calculation condition value creating means has a numerical value for the predetermined manufacturing condition. Calculation condition values expressed as computable data are created, and further, the pseudo structure generation means inputs the calculation condition values created by the calculation condition value creation means to the manufacturing model created by the manufacturing model creation means, and the semiconductor device Since the pseudo structure is generated using the result of reproducing the manufacturing process and the result of reproducing the manufacturing process, a pseudo structure in which the structure of the semiconductor device that changes in accordance with the manufacturing process is accurately expressed can be generated and calculated. Various pseudo structures can be easily generated by changing the condition value.
[0042]
In the second to sixth capacity calculation apparatuses, the calculation condition value creating means creates a plurality of calculation condition values, and the pseudo structure generating means is based on each of the plurality of calculation condition values created by the calculation condition value creating means. The capacitance calculation means calculates a plurality of capacitances of a predetermined portion of the semiconductor device based on each of the plurality of pseudo structures generated by the pseudo structure generation means, and calculates a plurality of capacitances created by the calculation condition value creation means Capacitance value function creation means for creating a capacitance value function that is a function expressing the correlation between the calculation condition value and the values of a plurality of capacitances of a predetermined portion of the semiconductor device calculated by the capacitance calculation means, and creation of the capacitance value function It is preferable that the apparatus further includes simple capacity calculating means for calculating the capacity of a predetermined portion of the semiconductor device using the capacity value function created by the means.
[0043]
In the second to sixth capacity calculation devices, the calculation condition value creating means repeatedly changes the calculation condition value until the capacitance value of the predetermined portion of the semiconductor device calculated by the capacitance calculation means becomes substantially equal to the predetermined value. Is preferred.
[0044]
The fifth or sixth capacity calculation apparatus further includes a variation model creating means for creating a variation model that is a mathematical formula for calculating a plurality of variation values of the predetermined manufacturing condition based on the predetermined manufacturing condition. The structure generation means calculates a plurality of variation values under a predetermined manufacturing condition by inputting the calculation condition value created by the calculation condition value creation means into the variation model created by the variation model creation means, and at the same time manufactures the predetermined manufacturing condition. Using each of the results obtained by sequentially inputting a plurality of variation values of conditions into the manufacturing model created by the manufacturing model creation means, a plurality of variation pseudo-structures expressing the variation in the structure of the semiconductor device are generated, and the capacitance The calculation means is based on each of the plurality of variation pseudo-structures generated by the pseudo-structure generation means and determines the capacitance of the predetermined portion of the semiconductor device. It is preferable to calculate the variation of the number.
[0045]
In the sixth capacity calculation apparatus, it is preferable that the calculation condition value creating means determines the predetermined manufacturing condition so that the pseudo structure generated by the pseudo structure generating means is equal to the predetermined pseudo structure.
[0046]
In the first capacitance calculation method according to the present invention, the structure of a semiconductor device having a wiring portion in which a wiring layer made of a conductive film and an insulating layer made of a dielectric film are stacked is expressed as data capable of numerical calculation. Based on the pseudo structure, assuming a capacitance calculation method for calculating the capacitance of the wiring portion, a shape model creation step for creating a shape model that is a mathematical expression expressing the dependency of the shape of the insulating layer on the shape of the wiring layer; A calculation condition value creation process that creates a calculation condition value that represents at least the shape of the wiring layer as numerically calculable data, and a calculation created in the calculation condition value creation process in the shape model created in the shape model creation process After obtaining the shape of the insulating layer by inputting the condition value, the pseudo structure generation process that generates the pseudo structure using the shape of the insulating layer, and the pseudo structure generation process Based on the pseudo-structure, and a capacity calculating step of calculating the capacity of the wiring portion.
[0047]
According to the first capacity calculation method, in the shape model creation step, a shape model expressing the dependency of the shape of the insulating layer on the shape of the wiring layer is created, and in the calculation condition value creation step, the shape of the wiring layer After creating the calculation condition value expressed as data that can be numerically calculated, in the pseudo structure generation process, enter the calculation condition value created in the calculation condition value creation process into the shape model created in the shape model creation process In addition to determining the shape of the insulating layer and generating a pseudo structure using the shape of the insulating layer, it is possible to generate a pseudo structure that accurately represents the shape of the insulating layer, and various pseudo structures by changing the calculation condition values Can be generated easily.
[0048]
A second capacity calculation method according to the present invention is a capacity calculation method for calculating a capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device composed of a plurality of components is expressed as numerically calculable data. And a shape model creation step of creating a shape model that is a mathematical expression expressing the dependency of the shape of one component in the semiconductor device on the shape or electrical characteristics of the other component in the semiconductor device, and In the calculation condition value creation process, a calculation condition value creation process for creating calculation condition values in which the shape or electrical characteristics of other components are expressed as data that can be numerically calculated, and the shape model created in the shape model creation process After obtaining the shape of one component by inputting the created calculation condition value, a pseudo structure is generated using the shape of the one component And a pseudo structure generation step that, based on the pseudo-structure generated in the pseudo-structure generation step, and a capacity calculating step of calculating the capacity of a predetermined portion of the semiconductor device.
[0049]
According to the second capacity calculation method, in the shape model creation step, a shape model is created in which the dependency of the shape of one component on the shape of another component or the electrical characteristics is expressed. In the creation process, after creating the calculation condition value expressed as data that can be numerically calculated the shape or electrical characteristics of other components, in the pseudo structure generation process, calculate the shape model created in the shape model creation process Since the calculation condition value created in the condition value creation process is input to determine the shape of one component and the pseudo structure is generated using the shape of the one component, the shape of one component is accurately The expressed pseudo structure can be generated, and various pseudo structures can be easily generated by changing the calculation condition value.
[0050]
A third capacity calculation method according to the present invention is a capacity calculation method for calculating a capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device composed of a plurality of components is expressed as numerically calculable data. And a dielectric constant model creation step of creating a dielectric constant model that is a mathematical expression expressing the dependence of the dielectric constant of one component in a semiconductor device on the shape or electrical characteristics of another component in the semiconductor device And a calculation condition value creation process for creating a calculation condition value in which at least the shape or electrical characteristics of other components are expressed as data that can be numerically calculated, and a dielectric constant model created in the dielectric constant model creation process After calculating the dielectric constant of one component by inputting the calculation condition value created in the condition value creation step, the dielectric constant of the one component is used. And a pseudo structure generation step of generating a pseudo-structure, based on the pseudo-structure generated in the pseudo-structure generation step, and a capacity calculating step of calculating the capacity of a predetermined portion of the semiconductor device.
[0051]
According to the third capacity calculation method, in the dielectric constant model creation step, a dielectric constant model in which the dependence of the dielectric constant of one component on the shape or electrical characteristics of another component is expressed, In the calculation condition value creation process, after creating the calculation condition value expressed as data that can be numerically calculated the shape or electrical characteristics of other components, it was created in the dielectric structure model creation process in the pseudo structure generation process In order to obtain the dielectric constant of one component by inputting the calculation condition value created in the calculation condition value creation step into the dielectric constant model and to generate a pseudo structure using the dielectric constant of the one component, A pseudo structure in which the dielectric constants of the constituent elements are accurately expressed can be generated, and various pseudo structures can be easily generated by changing the calculation condition value.
[0052]
A fourth capacity calculation method according to the present invention is a capacity calculation method for calculating the capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device composed of a plurality of components is expressed as numerically calculable data. And a usage model creation process that creates a usage model that is a mathematical formula that can reproduce the usage state of a semiconductor device under a predetermined usage condition, and a calculation condition value that represents at least the predetermined usage condition as data that can be numerically calculated The calculation condition value creation process for creating the semiconductor device and the use condition created in the use model creation process by inputting the calculation condition value created in the calculation condition value creation process to reproduce the usage state of the semiconductor device A pseudo-structure generation process that generates a pseudo-structure using the result of reproducing the state, and a pseudo-structure generated in the pseudo-structure generation process And a capacity calculating step of calculating the capacity of a predetermined portion of the semiconductor device.
[0053]
According to the fourth capacity calculation method, in the use model creation step, a use model that is a mathematical expression that can reproduce the use state of the semiconductor device under a predetermined use condition is created, and in the calculation condition value creation step, a predetermined use condition is created. After creating the calculation condition value expressed as data that can be numerically calculated, enter the calculation condition value created in the calculation condition value creation process into the use model created in the use model creation process in the pseudo structure generation process. Since the pseudo structure is generated using the result of reproducing the use state of the semiconductor device and the result of reproducing the use state, the pseudo structure in which the structure of the semiconductor device changing according to the use state is accurately expressed can be generated. At the same time, various pseudo structures can be easily generated by changing the calculation condition value.
[0054]
A fifth capacity calculation method according to the present invention is a capacity calculation method for calculating a capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device composed of a plurality of components is expressed as numerically calculable data. And a manufacturing model creating step for creating a manufacturing model that is a mathematical expression expressing a dependency of a shape or dielectric constant of one component in the semiconductor device on a predetermined manufacturing condition in the manufacturing process of the semiconductor device, and at least Calculation condition value creation process for creating a calculation condition value expressed as data that can be numerically calculated for a given manufacturing condition, and a calculation condition value created in the calculation condition value creation process for the production model created in the production model creation process After obtaining the shape or dielectric constant of one component by inputting, the pseudo structure using the shape or dielectric constant of the one component And a pseudo structure generation step of generating is based on the pseudo-structure generated in the pseudo-structure generation step, and a capacity calculation method for calculating the capacity of a predetermined portion of the semiconductor device.
[0055]
According to the fifth capacity calculation method, in the manufacturing model creation step, a manufacturing model in which the dependency of the shape or dielectric constant of one component on the predetermined manufacturing conditions is created, and in the calculation condition value creation step After creating a calculation condition value in which the predetermined manufacturing condition is expressed as numerically calculable data, the calculation created in the calculation condition value creation process in the manufacturing model created in the production model creation process in the pseudo structure generation process By inputting the condition value to determine the shape or dielectric constant of one component and to generate a pseudo structure using the shape or dielectric constant of the one component, the shape or dielectric constant of one component is accurately The expressed pseudo structure can be generated, and various pseudo structures can be easily generated by changing the calculation condition value.
[0056]
A sixth capacity calculation method according to the present invention is a capacity calculation method for calculating a capacity of a predetermined portion of a semiconductor device based on a pseudo structure in which the structure of a semiconductor device composed of a plurality of components is expressed as numerically calculable data. Based on the above, a manufacturing model creation process for creating a manufacturing model that is a mathematical formula that can reproduce a semiconductor device manufacturing process under a predetermined manufacturing condition, and at least a predetermined manufacturing condition expressed as data that can be numerically calculated After reproducing the manufacturing process of the semiconductor device by inputting the calculation condition value created in the calculation condition value creating process to the manufacturing model created in the manufacturing model creating process, the calculation condition value creating means for creating A pseudo-structure generation process that generates a pseudo-structure using a result of reproducing a manufacturing process, and a pseudo-structure generated in the pseudo-structure generation process Can, and a capacity calculating step of calculating the capacity of a predetermined portion of the semiconductor device.
[0057]
According to the sixth capacity calculation method, in the manufacturing model creation process, a manufacturing model that can reproduce the semiconductor device manufacturing process under a predetermined manufacturing condition is created, and in the calculation condition value creation process, the predetermined manufacturing condition is numerically calculated. After creating the calculation condition value expressed as possible data, in the pseudo structure generation process, input the calculation condition value created in the calculation condition value creation process to the manufacturing model created in the manufacturing model creation process, and the semiconductor device Since the pseudo structure is generated using the result of reproducing the manufacturing process and the result of reproducing the manufacturing process, a pseudo structure in which the structure of the semiconductor device that changes in accordance with the manufacturing process is accurately expressed can be generated and calculated. Various pseudo structures can be easily generated by changing the condition value.
[0058]
In the second to sixth capacity calculation methods, the calculation condition value creation step includes a step of creating a plurality of calculation condition values, and the pseudo structure generation step includes a plurality of calculation condition values created in the calculation condition value creation step. A step of generating a plurality of pseudo-structures based on the respective steps, and the capacity calculating step includes a step of calculating a plurality of capacities of a predetermined portion of the semiconductor device based on each of the plurality of pseudo-structures generated in the pseudo-structure generating step. A function expressing a correlation between a plurality of calculation condition values created in the calculation condition value creating step and a plurality of capacitance values of a predetermined portion of the semiconductor device calculated in the capacity calculation step after the capacity calculation step The capacitance value function creating step for creating a capacitance value function, and the capacitance value function created in the capacitance value function creating step are used to easily calculate the capacitance of a predetermined portion of the semiconductor device. Preferably further includes a capacity calculation step.
[0059]
In the second to sixth capacitance calculation methods, the calculation condition value creation step, the pseudo structure generation step, and the capacitance calculation step are performed in such a manner that the capacitance value of the predetermined portion of the semiconductor device calculated in the capacitance calculation step is substantially equal to the predetermined value. Until then, it is preferable to further include an iterative process that is repeated while changing the calculation condition value in the calculation condition value creating process.
[0060]
In the fifth or sixth capacity calculation method, before the pseudo structure generation process, based on a predetermined manufacturing condition, a variation model is created that is a mathematical expression that calculates a plurality of variation values of the predetermined manufacturing condition. The pseudo structure generation step includes a plurality of variations of a predetermined manufacturing condition by inputting the calculation condition value created in the calculation condition value creation step into the variation model created in the variation model creation step. After calculating the value, the variation of the structure of the semiconductor device is expressed using each of the results obtained by sequentially inputting a plurality of variation values of the predetermined manufacturing condition into the manufacturing model created in the manufacturing model creating step. The capacity calculation step includes generating a plurality of variation pseudo-structures generated in the pseudo-structure generation step. Based on each of the concrete, it is preferred to include a step of calculating a plurality of variation values in the capacitor of a predetermined portion of the semiconductor device.
[0061]
In the sixth capacity calculation method, it is preferable that the calculation condition value creating step includes a step of determining a predetermined manufacturing condition so that the pseudo structure generated in the pseudo structure generation step is equal to the predetermined pseudo structure.
[0062]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a capacity calculation device and a capacity calculation method according to a first embodiment of the present invention will be described with reference to the drawings.
[0063]
FIG. 1 is a flowchart of a capacity calculation method according to the first embodiment.
[0064]
First, the shape measurement process performed by the shape measurement means in step SA1 will be described. That is, in the shape measurement step, the shape of the wiring part in the actually manufactured semiconductor device is actually measured. Specifically, for example, using a photograph of a wiring part created by SEM (scanning electron microscope) cross-sectional photography, the thickness or width of a conductive thin film that becomes a wiring layer, or a void or interlayer insulation generated in a passivation film After measuring dimensions such as the shape of the taper portion of the film, the dimensions are divided by the magnification of the photograph to obtain the shape of the wiring portion.
[0065]
In the present embodiment, the shape of the wiring portion is actually measured in the shape measuring step. Instead, the desired shape of the wiring portion is obtained from a database in which data relating to the shape of the wiring portion measured in advance is sufficiently accumulated. You may extract and use the data regarding.
[0066]
Next, the shape model creation process performed by the shape model creation means in step SA2 will be described. That is, in the shape model creation step, a shape model that is a mathematical expression expressing the dependency of the shape of the insulating layer on the shape of the wiring layer is created based on the data related to the shape of the wiring portion actually measured in the shape measurement step. . The shape model is created based on the shape type that is the prototype data of the pseudo structure, and the shape of the insulating layer can be calculated by inputting the shape of the wiring layer.
[0067]
Hereinafter, with respect to the method of creating the shape model in step SA2, referring to the flow diagram shown in FIG. 2 as an example of the shape model in which the dependency of the shape of the void generated in the passivation film (see FIG. 30) on the wiring interval is expressed. While explaining.
[0068]
In step SA21, prototype data of a pseudo structure in which the structure of the semiconductor device to be subjected to capacity calculation is expressed is generated. For example, since it is difficult to create a shape model using the shape of the void 44a shown in FIG. 30 as it is, a rectangle that exists in the middle between adjacent wiring layers is selected as the prototype data of the void 44a.
[0069]
FIG. 3 is a cross-sectional view of the pseudo structure in which the structure of the wiring portion including the void 44a shown in FIG. 30 is expressed. In FIG. 3, 100 is a first wiring layer as a lower layer, 101 is a second wiring layer as an upper layer, 102 is a first interlayer insulating film, 102a is a tapered portion of the first interlayer insulating film 102, 103 is The second interlayer insulating film 104 is a passivation film for protecting the second wiring layer 101, and 104a is a void generated in the passivation film. As the prototype data of the tapered portion 42a in the first interlayer insulating film 42 shown in FIG. 30, a triangle or trapezoid existing on the first wiring layer 100 is selected as shown in FIG.
[0070]
In step SA22, data relating to the shape of the wiring portion actually measured in the shape measuring step is plotted. For example, in order to investigate the dependency of the void shape on the wiring interval, as shown in FIG. 4, the horizontal axis represents the wiring interval and the vertical axis represents the width of the void or the height of the void. Plot data on the shape of the created void.
[0071]
In step SA23, based on the result plotted in step SA22, for example, a shape model in which the dependency of the void shape on the wiring interval is expressed is created.
[0072]
FIG. 5 is a graph showing a shape model in which the void width or void height is expressed as a linear function of the wiring interval based on the void shape plot results shown in FIG. In FIG. 5, the solid line is a graph showing a shape model in which the void width is expressed as a linear function of the wiring interval, and the alternate long and short dash line is the shape model in which the height of the void is expressed as a linear function of the wiring interval. This is shown in the graph.
[0073]
Even when a wiring interval other than the actual measurement data is input to the shape model shown in FIG. 5, a substantially accurate void width or height can be obtained within the practical range. In FIG. 5, since the void width or the void height becomes constant when the value of the wiring interval exceeds a predetermined value (s1 in FIG. 5), the wiring interval is divided into two sections with s1 as a boundary. Different shape models are created in each section.
[0074]
In the following, an example of the shape model shown in FIG. 5 is shown where the wiring interval is x, the width of the void is y1, and the height of the void is y2.
[0075]

The shape model created in the shape model creation step is stored in the database DA1 as shown in FIG. Thereby, the shape model created in the shape model creation step can be reused.
[0076]
In addition, in the shape model creation process, the shape model was created by plotting data related to the shape of the wiring portion actually measured in the shape measurement step, but instead, this relates to the shape of the wiring portion actually measured in the shape measurement step. For example, a shape model may be created for the data by using a statistical method such as a least square method.
[0077]
In addition, in the shape model creation process, a shape model in which the dependency of the void shape on the wiring interval is expressed is created. However, the shape model is not limited to this, and the wiring width of the shape of the taper portion of the interlayer insulating film is not limited thereto. A shape model or the like in which the dependency relationship with respect to is expressed can also be created.
[0078]
In addition, in the shape model creation process, a rectangle is used as the shape type of the original data for creating the shape model. However, the shape type is not limited to this, but other shape types such as polygons, circles, or a combination of these shapes Etc. can be used.
[0079]
Next, the pseudo structure generation process performed by the pseudo structure generation means in step SA3 will be described. That is, in the pseudo structure generation step, the shape of the insulating layer, for example, the shape of the void generated in the passivation film is obtained by inputting the shape of the wiring layer, for example, the wiring interval, into the shape model created in the shape model creating step. Then, a pseudo structure is generated using the shape of the insulating layer.
[0080]
Hereinafter, a method for generating a pseudo structure in the pseudo structure generation step is illustrated in FIG. 6 as an example in which a plurality of pseudo structures are generated in order to calculate a plurality of wiring capacitance components in a wiring portion having a plurality of wiring layers. This will be described with reference to a flow diagram. Here, the plurality of wiring layers in the wiring section are physically separated by an interlayer insulating film in order to avoid electrical contact with each other and to distinguish purposes such as between elements, between cells, or between blocks. It shall be separated in the vertical direction.
[0081]
In step SA31, the number of wiring layers, the thickness of the wiring layers, the dielectric constant of the interlayer insulating film, and the like are input.
[0082]
In step SA32, templates necessary for the calculation of the wiring capacitance component are sequentially selected from the database DA2 in which a large number of templates in which the pseudo structure generation procedure is abstractly described are stored.
[0083]
[Table 1] shows an example of a template.
[0084]
[Table 1]

[0085]
In [Table 1], m in the wiring layer mn indicates that it is a wiring layer, and n indicates the distinction between the wiring layers. For example, m1 is determined as a lowermost wiring layer excluding the ground wiring layer m0, and m3 is determined as a wiring layer two layers above m1.
[0086]
In step SA33, the wiring layers included in the template selected in step SA32 are sequentially selected.
[0087]
In step SA34, the wiring interval described in the template shown in Table 1 is input to the shape model created in the shape model creation step, for example, the shape model expressing the dependency of the void shape shown in FIG. After calculating the void shape, the void shape, the wiring layer thickness input in step SA31, the dielectric constant of the interlayer insulating film, etc. are added to the template, which is necessary for calculating the wiring capacitance component. A shape numerical table that is a combination of the shape determination values of the pseudo structure is generated and stored in the database DA3.
[0088]
[Table 2] shows an example of the shape numerical value table.
[0089]
[Table 2]

[0090]
In step SA35, it is determined whether or not the processing has been completed for all the wiring layers included in the template selected in step SA32. If the process has been completed, the process proceeds to step SA36, and if the process has not been completed, the process returns to step SA33.
[0091]
In step SA36, it is determined whether or not the processing has been completed for all templates corresponding to the wiring capacitance component to be calculated. If the process has been completed, the process proceeds to step SA37. If the process has not been completed, the process returns to step SA32.
[0092]
In step SA37, shape numerical tables necessary for calculating the wiring capacitance component are sequentially selected from the database DA3, and then pseudo structures are sequentially generated based on the shape numerical tables.
[0093]
FIG. 7 is a cross-sectional view showing an example of a pseudo structure generated based on a combination of one shape determination value surrounded by a thick solid line in the shape numerical value table shown in [Table 2]. In FIG. 7, 110 is a first wiring layer serving as a ground wiring layer, 111 is a second wiring layer, 112 is a first interlayer insulating film, 113 is a second interlayer insulating film, 114 is a passivation film, and 114a is Voids generated in the passivation film 114 are shown. In FIG. 7, a portion surrounded by a thick solid line indicates one analysis region to be subjected to wiring capacity simulation. As shown in FIG. 7, the other analysis region adjacent to the one analysis region is equivalent to a shape obtained by folding the one analysis region, so that the pseudo structure in which the one analysis region is expressed is analyzed by another analysis. Since it can be used for a region, the time required to generate a pseudo structure can be shortened.
[0094]
Next, the wiring capacity calculation process performed by the wiring capacity calculation means in step SA4 will be described. That is, in the wiring capacity calculation process, after performing the wiring capacity calculation using the wiring capacity simulation based on the pseudo structure generated in the pseudo structure generation process, the wiring capacity component is calculated based on the result of the wiring capacity calculation. Do.
[0095]
According to the first embodiment, in the shape model creation step, the shape model in which the dependency of the shape of the insulating layer on the shape of the wiring layer is expressed based on the data related to the shape of the wiring portion actually measured in the shape measurement step. After the creation, in the pseudo structure generation step, to obtain the shape of the insulating layer by inputting the shape of the wiring layer to the shape model created in the shape model creation step, and to generate the pseudo structure using the shape of the insulating layer Since the pseudo structure in which the shape of the insulating layer is accurately expressed can be generated, the accuracy of the capacitance calculation of the wiring portion can be improved.
[0096]
Although the two-dimensional pseudo structure is used in the first embodiment, the same effect can be obtained by using a three-dimensional pseudo structure instead.
[0097]
(Second Embodiment)
Hereinafter, a capacity calculation apparatus and a capacity calculation method according to a second embodiment of the present invention will be described with reference to the drawings.
[0098]
FIG. 8 is a flowchart of the capacity calculation method according to the second embodiment.
[0099]
First, the pseudo structure generation process performed by the pseudo structure generation means in step SB1 will be described. That is, in the pseudo structure generation process, a predetermined manufacturing condition (sputtering rate) of a thin film growth rate in a thin film forming process using a sputtering method, for example, a manufacturing model that is a mathematical formula that can reproduce a semiconductor device manufacturing process under a predetermined manufacturing condition. Using the results of reproducing the manufacturing process after reproducing the manufacturing process of the semiconductor device by inputting predetermined manufacturing conditions into the manufacturing model expressing the dependency on temperature, sputtering time, growth material, etc.) Generate a pseudo structure.
[0100]
In the present embodiment, it is assumed that a manufacturing model, manufacturing conditions, and the like that are created in advance and stored in a database are used.
[0101]
Hereinafter, with respect to a method of generating a pseudo structure in the pseudo structure generation step, an example in which a plurality of pseudo structures necessary for calculating a plurality of wiring capacitance components in a wiring section having a plurality of wiring layers is generated is illustrated in FIG. This will be described with reference to the flowchart shown in FIG.
[0102]
In step SB11, templates necessary for calculation of the wiring capacitance component are sequentially selected from the database DB1 in which a large number of templates in which the pseudo structure generation procedure is abstractly described are stored.
[0103]
[Table 3] shows an example of a template.
[0104]
[Table 3]

[0105]
In step SB12, the wiring layers included in the template selected in step SB11 are sequentially selected.
[0106]
In step SB13, a shape numerical value table to which a combination of shape determination values obtained by reproduction of the manufacturing process in the subsequent step SB18 is added is generated based on the template, and the shape numerical value table is stored in the database DB2.
[0107]
[Table 4] shows an example of the shape numerical value table.
[0108]
[Table 4]

[0109]
In step SB14, it is determined whether or not the processing has been completed for all the wiring layers included in the template selected in step SB11. If the process has ended, the process proceeds to step SB15. If the process has not ended, the process returns to step SB12.
[0110]
In step SB15, it is determined whether or not the processing has been completed for all templates corresponding to the wiring capacitance component to be calculated. If the process has been completed, the process proceeds to step SB16. If the process has not been completed, the process returns to step SB11.
[0111]
In step SB16, the type of a series of steps (hereinafter referred to as processes) for manufacturing the semiconductor device is designated.
[0112]
In step SB17, the type of manufacturing model that reproduces each manufacturing process included in the process specified in step SB16 is specified.
[0113]
In step SB18, the manufacturing process order and manufacturing conditions of the process specified in step SB16 are extracted from the database DB3 in which process data including the manufacturing process order and manufacturing conditions of the process are accumulated. After extracting the manufacturing model specified in step SB17 and the parameters of the manufacturing model from the database DB4 in which model data consisting of parameters is accumulated, the manufacturing extracted into the extracted manufacturing model in accordance with the extracted manufacturing process sequence Enter the conditions. Thereby, the manufacturing process is sequentially reproduced, and for example, the shape or dielectric constant of a plurality of components constituting the semiconductor device is obtained. Next, based on the result of reproducing the manufacturing process, after creating a combination of the shape determination values of the pseudo structure, the combination of the shape determination values is added to the shape numerical table stored in the database DB2, and the shape numerical table To complete.
[0114]
In step SB19, after a shape numerical table necessary for calculating the wiring capacitance component is sequentially selected from the database DB2, pseudo structures are sequentially generated based on the shape numerical table.
[0115]
FIG. 9 is a cross-sectional view showing an example of the pseudo structure generated in the pseudo structure generation process. In FIG. 9, reference numeral 200 denotes a first wiring layer serving as a ground wiring layer, 201 denotes a second wiring layer, 202 denotes a first interlayer insulating film, 203 denotes a second interlayer insulating film, 204 denotes a passivation film, and 204a denotes The voids generated in the passivation film 204 are shown. In FIG. 9, a portion surrounded by a thick solid line indicates one analysis region to be subjected to wiring capacity simulation. As shown in FIG. 9, the other analysis region adjacent to the one analysis region is equivalent to a shape obtained by folding the one analysis region, so that the pseudo structure in which the one analysis region is expressed is analyzed by another analysis. Since it can be used for a region, the time required to generate a pseudo structure can be shortened.
[0116]
In the pseudo structure generation step, the manufacturing conditions, the manufacturing model, and the like are extracted from the database and used. Instead, the manufacturing conditions, the manufacturing model, and the like may be sequentially generated and used.
[0117]
In addition, in the pseudo structure generation process, the manufacturing conditions or the manufacturing process order are determined by specifying the type of process. Instead, the pseudo structure generated in the pseudo structure generation process is equal to a predetermined pseudo structure. As such, the manufacturing conditions or the manufacturing process sequence may be determined.
[0118]
Next, the wiring capacity calculation process performed by the wiring capacity calculation means in step SB2 will be described. That is, in the wiring capacity calculation process, after performing the wiring capacity calculation using the wiring capacity simulation based on the pseudo structure generated in the pseudo structure generation process, the wiring capacity component is calculated based on the result of the wiring capacity calculation. Do.
[0119]
According to the second embodiment, in the pseudo structure generation process, the manufacturing process of the semiconductor device is reproduced by inputting the predetermined manufacturing conditions to the manufacturing model that can reproduce the manufacturing process of the semiconductor device under the predetermined manufacturing conditions. Since the pseudo structure is generated using the result of reproducing the manufacturing process, the pseudo structure in which the structure of the semiconductor device that changes in accordance with the manufacturing process is accurately expressed can be generated. it can. In addition, since the pseudo structure can be generated without trial manufacture or actual measurement of the semiconductor device, the capacity calculation can be easily performed.
[0120]
In the second embodiment, a pseudo structure is sequentially created for each wiring capacitance component to be calculated. Instead, a pseudo structure in which all wiring layers are arranged is generated in advance using a manufacturing model. In addition, the pseudo structure may be partially changed and used for each wiring capacitance component to be calculated, or a plurality of pseudo structures in which characteristic structures in the wiring portion are expressed in advance are manufactured models. The plurality of pseudo structures may be geometrically combined and used for each wiring capacitance component to be calculated. In this way, the time required for generating the pseudo structure can be shortened.
[0121]
In the second embodiment, the wiring capacitance is calculated based on the pseudo structure generated using the manufacturing model. Instead, the wiring resistance is calculated based on the pseudo structure generated using the manufacturing model. Even if the calculation is performed, the same effect, that is, the effect that the accuracy of the resistance calculation is improved can be obtained.
[0122]
(Third embodiment)
Hereinafter, a capacitance calculation apparatus and a capacitance calculation method according to a third embodiment of the present invention will be described with reference to the drawings, taking as an example the calculation of the capacitance of a depletion layer generated in a transistor element.
[0123]
FIG. 10 is a flowchart of the capacity calculation method according to the third embodiment.
[0124]
First, the prototype data generation process performed by the prototype data generation means in step SC1 will be described. That is, in the prototype data generation step, pseudo-structure prototype data representing the structure of the semiconductor device that is the target of capacitance calculation is generated.
[0125]
FIG. 11 is a cross-sectional view illustrating an example of a transistor element including a depletion layer. In FIG. 11, 300 is a semiconductor substrate, 300a is the surface of the semiconductor substrate, 301 is a source / drain region, 302 is a gate insulating film, 303 is a gate electrode, and 304 is a depletion layer. In FIG. 11, a thick solid line indicates a junction between a channel region and a source region (or drain region), a white circle indicates an electron, and a black circle indicates a hole. The shape or position of the junction or the bending or thickness of the depletion layer 304 varies depending on the electrical characteristics of the semiconductor substrate 300 or the source / drain region 301, such as an impurity substance or impurity concentration.
[0126]
In the prototype data generation step, specifically, since it is desired to approximate the capacitance of the depletion layer 304 sandwiched between the semiconductor substrate 300 and the source / drain region 301, the prototype data of the depletion layer 304 is, for example, Select a rectangle centered on the junction.
[0127]
Further, in the prototype data generation process, prototype data having a pseudo structure is generated, a capacitance calculation target (in this embodiment, a depletion layer 304 sandwiched between the semiconductor substrate 300 and the source / drain region 301), and a capacitance Specific calculation conditions (in this embodiment, a voltage applied to the semiconductor substrate 300 and the source / drain region 301, a unit of capacitance, and the like) are input. The input may be performed in a later capacity calculation step.
[0128]
Next, the shape model creation process performed by the shape model creation means in step SC2 will be described. That is, in the shape model creation step, a shape model that is a mathematical expression expressing the dependency of the shape of one component in the semiconductor device on the shape or electrical characteristics of another component in the semiconductor device, for example, a depletion layer A shape model is created in which the dependency of the shape on the depth of the junction from the substrate surface (hereinafter referred to as the junction position) and the thickness of the depletion layer is expressed. Note that the thickness of the depletion layer is obtained from the distribution of the total amount of charges (difference in the number of electrons and holes as carriers) in the semiconductor substrate.
[0129]
Hereinafter, an example of a shape model of the depletion layer 304 when the y coordinate is taken downward and the origin of the y coordinate is taken on the substrate surface is shown.
[0130]
Depletion layer bottom y coordinate = Junction position + Depletion layer thickness / 2
Depletion layer top y-coordinate = Junction position-Depletion layer thickness / 2
The shape model created in the shape model creation step is stored in the database DC1 as shown in FIG. Thereby, the shape model created in the shape model creation step can be reused.
[0131]
Next, the calculation condition value creating process performed by the calculation condition value creating means in step SC3 will be described. That is, in the calculation condition value creation step, a calculation condition value is created in which the shape or electrical characteristics of other components in the semiconductor device, for example, the junction position or the like is expressed as data that can be numerically calculated.
[0132]
Next, the pseudo structure generation process performed by the pseudo structure generation means in step SC4 will be described. That is, in the pseudo structure generation step, by inputting the calculation condition value created in the calculation condition value creation step into the shape model created in the shape model creation step, the shape of one component in the semiconductor device, for example, a depletion layer Then, a pseudo structure is generated using the shape of the one component.
[0133]
FIG. 12 is a cross-sectional view illustrating an example of the pseudo structure generated in the pseudo structure generation process. In FIG. 12, 310 is a semiconductor substrate, 310a is the surface of the semiconductor substrate, 311 is a source / drain region, 312 is a gate insulating film, 313 is a gate electrode, and 314 is a depletion layer. In FIG. 12, a thick solid line indicates the junction between the channel region and the source region (or drain region), a indicates the junction position, and b indicates the thickness of the depletion layer.
[0134]
Next, the capacity calculation process performed by the capacity calculation means in step SC5 will be described. That is, in the capacitance calculation step, the capacitance of a predetermined portion of the semiconductor device, for example, a depletion layer is calculated based on the pseudo structure generated in the pseudo structure generation step.
[0135]
According to the third embodiment, in the shape model creation step, a shape model in which the dependency of the shape of one component on the shape of another component or the electrical characteristics is created, and the calculation condition value is created In the process, after creating the calculation condition value expressed as data that can be numerically calculated the shape or electrical characteristics of other components, in the pseudo-structure generation process, the calculation condition for the shape model created in the shape model creation process The calculation condition value created in the value creation process is input to determine the shape of one component, and the pseudo structure is generated using the shape of the one component, so that the shape of one component is accurately expressed. Therefore, the accuracy of capacity calculation can be improved. In addition, since various pseudo structures can be easily generated by changing the calculation condition value, the capacity calculation can be simplified.
[0136]
In the third embodiment, a shape model in which the dependency of the shape of the depletion layer on the junction position and the thickness of the depletion layer is created, but instead, for example, a substrate having a shape of the depletion layer is formed. You may create the shape model etc. in which the dependence relation with respect to a substance, an impurity substance, and an impurity introduction amount was expressed. When the substrate material, the impurity material, and the impurity introduction amount are determined, the impurity concentration distribution is determined empirically, so that the structure near the depletion layer can be determined. That is, by inputting a controllable value such as the amount of impurities introduced during the manufacture of a semiconductor device into the shape model that expresses the dependency of the shape of the depletion layer on the substrate material, the impurity material, and the amount of impurities introduced, The shape of the layer is required.
[0137]
Hereinafter, an example of an equation for obtaining the impurity concentration distribution from the substrate material, the impurity material, and the amount of introduced impurity, and an example of an equation for obtaining the junction position or the thickness of the depletion layer from the impurity concentration distribution are shown. The mathematical formula for obtaining the shape of the depletion layer from the junction position obtained from the impurity concentration distribution and the thickness of the depletion layer is the same as an example of the shape model of the depletion layer 304 described above.
[0138]
Impurity concentration at a certain depth from the substrate surface =
f (Substrate material, impurity material, impurity introduction amount, depth)
Here, f is an impurity distribution function for calculating the impurity concentration.
[0139]
Junction position =
g (one conductivity type impurity substance, one conductivity type impurity introduction amount, other conductivity type impurity substance, other conductivity type impurity introduction amount)
However, g is a calculation process for obtaining a position where the one conductivity type impurity concentration calculated by f and the other conductivity type impurity concentration are the same.
[0140]
Depletion layer thickness =
h (impurity substance, ..., surface concentration, ..., coefficient, ...)
However, h is a calculation process for obtaining the thickness of the depletion layer from the combination of impurity substances, the concentration of each impurity substance, the recombination ratio of electrons and holes, and the like.
[0141]
(Modification of the third embodiment)
Hereinafter, a capacity calculation device and a capacity calculation method according to a modification of the third embodiment of the present invention will be described with reference to the drawings.
[0142]
FIG. 13 is a flowchart of a capacity calculation method according to a modification of the third embodiment.
[0143]
The capacity calculation device and the capacity calculation method according to the modification of the third embodiment are different from those of the third embodiment in that a dielectric constant model creating step is performed by a dielectric constant model creating means in step SD2. That is, in the dielectric constant model creation step, a dielectric constant model that is a mathematical expression expressing the dependency of the dielectric constant of one component in the semiconductor device on the shape or electrical characteristics of the other component in the semiconductor device, for example, A dielectric constant model expressing the dependence of the dielectric constant of the depletion layer on the total charge of the semiconductor substrate (difference in the number of electrons and holes as carriers) is created.
[0144]
FIG. 14 is a cross-sectional view showing an example of a pseudo structure in which the structure of a transistor element including a depletion layer is expressed. In FIG. 14, 320 is a semiconductor substrate, 320a is the surface of the semiconductor substrate, 321 is a source / drain region, 322 is a gate insulating film, 323 is a gate electrode, and 324 is a depletion layer. In FIG. 14, a thick solid line indicates a junction between the channel region and the source region (or drain region).
[0145]
FIG. 15 is a diagram illustrating an example of a method for defining a depletion layer. In FIG. 15, a thick solid line indicates one distribution of the total amount of charges in the semiconductor substrate when one impurity substance is injected into the semiconductor substrate with one impurity introduction amount, and a one-dot chain line indicates another impurity substance. The other distribution of the total amount of charges inside the semiconductor substrate when implanted into the semiconductor substrate with another impurity introduction amount is shown, and the broken line indicates the upper limit value of the total amount of charges defined as a depletion layer.
[0146]
In the case of the one distribution shown in FIG. 15, a range where the one distribution is less than the upper limit value of the total amount of charge defined as the depletion layer is defined as the depletion layer, and c shown in FIG. 15 is the thickness of the depletion layer.
[0147]
However, in the case of the other distribution shown in FIG. 15, since the thickness of the depletion layer cannot be obtained from the upper limit value of the total charge amount, for example, the dependency of the shape of the depletion layer on the junction position and the thickness of the depletion layer is expressed. It is not possible to generate a pseudo structure using the formed shape model.
[0148]
On the other hand, according to the modification of the third embodiment, for example, the dielectric constant model in which the junction position and the thickness of the depletion layer are fixed to a constant value and the dependence of the dielectric constant of the depletion layer on the total charge is expressed. Since the pseudo structure is generated using the pseudo structure, the pseudo structure can be generated even in the case of another distribution shown in FIG.
[0149]
(Fourth embodiment)
Hereinafter, a capacity calculation apparatus and a capacity calculation method according to a fourth embodiment of the present invention will be described with reference to the drawings.
[0150]
FIG. 16 is a flowchart of the capacity calculation method according to the fourth embodiment.
[0151]
First, the manufacturing process designating process performed by the manufacturing process designating means in step SE1 will be described. That is, in the manufacturing process designating step, the type of semiconductor device manufacturing process and the execution order are designated.
[0152]
Next, the manufacturing model creation process performed by the manufacturing model creation means in step SE2 will be described. That is, in the manufacturing model creation process, a manufacturing model that is a mathematical formula that can reproduce the manufacturing process specified in the manufacturing process specifying process under a predetermined manufacturing condition, for example, a predetermined distance such as an impurity moving distance or impurity concentration from the substrate surface. A manufacturing model is created in which a dependency relationship with manufacturing conditions (diffusion temperature or diffusion time) is expressed.
[0153]
The production model created in the production model creation process is stored in the database DE1. This makes it possible to reuse the manufacturing model created in the manufacturing model creation process.
[0154]
Next, the calculation condition value creating process performed by the calculation condition value creating means in step SE3 will be described. That is, in the calculation condition value creation step, a calculation condition value is created in which predetermined manufacturing conditions are expressed as data that can be numerically calculated.
[0155]
Next, the pseudo structure generation process performed by the pseudo structure generation means in step SE4 will be described. In other words, in the pseudo structure generation process, the calculation condition value created in the calculation condition value creation process is input to the production model created in the production model creation process according to the execution order of the production process designated in the production process designation process. Thus, after reproducing the manufacturing process of the semiconductor device, a pseudo structure is generated using the result of reproducing the manufacturing process.
[0156]
Next, the capacity calculation process performed by the capacity calculation means in step SE5 will be described. That is, in the capacitance calculation step, the capacitance of a predetermined portion of the semiconductor device is calculated based on the pseudo structure generated in the pseudo structure generation step.
[0157]
According to the fourth embodiment, in the manufacturing model creating process, a manufacturing model that is a mathematical formula that can reproduce the manufacturing process of the semiconductor device under a predetermined manufacturing condition is created, and in the calculation condition value creating process, the predetermined manufacturing condition is After creating the calculation condition value expressed as data that can be numerically calculated, in the pseudo structure generation process, enter the calculation condition value created in the calculation condition value creation process into the production model created in the production model creation process. Since the pseudo structure is generated by reproducing the manufacturing process of the semiconductor device and using the result of reproducing the manufacturing process, it is possible to generate the pseudo structure in which the structure of the semiconductor device changing in accordance with the manufacturing process is accurately expressed. The accuracy of capacity calculation can be improved. In addition, since various pseudo structures can be easily generated by changing the calculation condition value, the capacity calculation can be simplified.
[0158]
(Fifth embodiment)
Hereinafter, a capacitance calculation apparatus and a capacitance calculation method according to a fifth embodiment of the present invention will be described with reference to the drawings, taking as an example the calculation of the capacitance of a thin trench element isolation insulating film (hereinafter referred to as STI). .
[0159]
FIG. 17 is a flowchart of the capacity calculation method according to the fifth embodiment.
[0160]
First, the prototype data generation process performed by the prototype data generation means in step SF1 will be described. That is, in the prototype data generation step, pseudo-structure prototype data representing the structure of the semiconductor device that is the target of capacitance calculation is generated.
[0161]
FIG. 18 is a cross-sectional view showing an example of an STI. In FIG. 18, 500 is a semiconductor substrate, 501 is a source / drain region, 502 is a gate insulating film, 503 is a gate electrode, 504 is STI, d is the width of STI, and e is the height of STI.
[0162]
In the prototype data generation process, specifically, since it is desired to approximately obtain the capacitance of the STI 504 sandwiched between the two transistor regions, the prototype data of the STI 504 is, for example, sandwiched between the two transistor regions. Select a rectangle. In this way, the shape of the STI can be expressed by the width d of the STI and the height e of the STI. However, the actual shape of the STI changes due to variations in manufacturing conditions such as diffusion temperature or diffusion time in the manufacturing process.
[0163]
FIG. 19 is a diagram illustrating an example of variations in the STI width. In FIG. 19, the distribution of STI width variation is indicated by a thick solid line and a bar graph, and the average value of the STI width is indicated by a broken line.
[0164]
Next, the manufacturing model creation process performed by the manufacturing model creation means in step SF2 will be described. That is, in the manufacturing model creation process, a manufacturing model, for example, the shape of the STI, is a mathematical expression expressing the dependency of the shape or dielectric constant of one component in the semiconductor device on the predetermined manufacturing conditions in the manufacturing process of the semiconductor device. That is, a manufacturing model is created that is a mathematical expression expressing the dependency of the STI width or STI height on predetermined manufacturing conditions (such as oxidation time or etching rate). Note that the manufacturing model is created based on the pseudo structure prototype data generated in the prototype data generation process and the standard value of the shape or dielectric constant of one component in the semiconductor device.
[0165]
Next, the variation model creating process performed by the variation model creating means in step SF3 will be described. That is, in the variation model creation step, a variation model that is a mathematical formula for calculating a plurality of variation values of the predetermined manufacturing condition is generated based on the predetermined manufacturing condition. As the variation model, for example, a combination of a distribution function model that approximates variation in manufacturing conditions and a coefficient of the distribution function model can be used.
[0166]
The manufacturing model created in the manufacturing model creation process and the variation model created in the variation model creation process are stored in the database DF1. This makes it possible to reuse the manufacturing model created in the manufacturing model creation process and the variation model created in the variation model creation process.
[0167]
Next, the calculation condition value creating step performed by the calculation condition value creating means in step SF4 will be described. That is, in the calculation condition value creation step, a calculation condition value is created in which predetermined manufacturing conditions are expressed as data that can be numerically calculated.
[0168]
Next, the average pseudo structure generation process performed by the average pseudo structure generation means in step SF5 will be described. That is, in the average pseudo structure generation step, the calculation condition value created in the calculation condition value creation step is input to the production model created in the production model creation step, so that the shape or dielectric of one component of the semiconductor device is obtained. After determining the ratio, for example, the shape of the STI, an average pseudo structure in which the average structure of the semiconductor device is expressed using the shape or dielectric constant of the one component is generated.
[0169]
Next, the variation pseudo structure generation process performed by the variation pseudo structure generation means in step SF6 will be described. That is, in the variation pseudo-structure generation process, the calculation condition values created in the calculation condition value creation step are input to the variation model created in the variation model creation step, thereby calculating a plurality of variation values for a predetermined manufacturing condition. Then, using each of the results obtained by sequentially inputting a plurality of variation values of the predetermined manufacturing condition into the manufacturing model created in the manufacturing model creating step, a plurality of variations expressing the structure variation of the semiconductor device are expressed. A variation pseudo-structure is generated.
[0170]
Next, the capacity calculation process performed by the capacity calculation means in step SF7 will be described. That is, in the capacity calculation step, based on the average pseudo structure generated in the average pseudo structure generation step, the average value of the capacitance of a predetermined portion of the semiconductor device, for example, the average value of the STI capacity, is calculated, and the variation pseudo structure is generated. Based on each of the plurality of variation pseudo-structures generated in the process, a plurality of variation values of the capacitance of a predetermined portion of the semiconductor device, for example, a plurality of variation values of the STI capacitance are calculated.
[0171]
According to the fifth embodiment, in the manufacturing model creating step, the manufacturing model in which the dependency of the shape or dielectric constant of one component on the predetermined manufacturing conditions is created, and in the calculation condition value creating step, After creating a calculation condition value in which the predetermined manufacturing condition is expressed as data that can be numerically calculated, the calculation condition value is input to the manufacturing model and the shape or dielectric constant of one component is obtained in the average pseudo-structure generation process In addition, since the average pseudo structure is generated using the shape or dielectric constant of the one component, the average pseudo structure in which the shape or dielectric constant of the one component is accurately expressed can be generated. The average value of the capacity can be calculated accurately.
[0172]
Further, according to the fifth embodiment, in the variation model creating step, after creating a variation model for calculating a plurality of variation values of the predetermined manufacturing condition based on the predetermined manufacturing condition of the semiconductor device, the variation pseudo-structure generating step , The calculation condition value is input to the variation model to calculate a plurality of variation values of the predetermined manufacturing condition, and each of the results obtained by sequentially inputting the plurality of variation values of the predetermined manufacturing condition to the manufacturing model is obtained. In order to generate a plurality of variation pseudo-structures in which the variation in the structure of the semiconductor device is expressed, a plurality of variation pseudo-structures in which the variation in the structure of the semiconductor device corresponding to the variation value of a predetermined manufacturing condition is accurately expressed Therefore, the variation in the capacitance of a predetermined portion of the semiconductor device can be accurately calculated.
[0173]
(Sixth embodiment)
Hereinafter, a capacity calculation device and a capacity calculation method according to a sixth embodiment of the present invention will be described with reference to the drawings.
[0174]
FIG. 20 is a flowchart of the capacity calculation method according to the sixth embodiment.
[0175]
First, the manufacturing process designating process performed by the manufacturing process designating means in step SG1 will be described. That is, in the manufacturing process designating step, the type of semiconductor device manufacturing process and the execution order are designated.
[0176]
Next, the manufacturing model creation process performed by the manufacturing model creation means in step SG2 will be described. That is, in the manufacturing model creation process, a manufacturing model that is a mathematical formula that can reproduce the manufacturing process specified in the manufacturing process specifying process under predetermined manufacturing conditions, for example, a predetermined distance such as the distance of impurity migration or impurity concentration from the substrate surface. A manufacturing model is created in which the dependency on the manufacturing conditions (oxidation time or etching rate) is expressed.
[0177]
Next, the variation model creating process performed by the variation model creating means in step SG3 will be described. That is, in the variation model creation step, a variation model that is a mathematical formula for calculating a plurality of variation values of the predetermined manufacturing condition is generated based on the predetermined manufacturing condition. As the variation model, for example, a combination of a distribution function model that approximates variation in manufacturing conditions and a coefficient of the distribution function model can be used.
[0178]
The manufacturing model created in the manufacturing model creation process and the variation model created in the variation model creation process are stored in the database DG1. This makes it possible to reuse the manufacturing model created in the manufacturing model creation process and the variation model created in the variation model creation process.
[0179]
Next, the calculation condition value creating process performed by the calculation condition value creating means in step SG4 will be described. That is, in the calculation condition value creation step, a calculation condition value is created in which predetermined manufacturing conditions are expressed as data that can be numerically calculated.
[0180]
Next, the average pseudo structure generation process performed by the average pseudo structure generation means in step SG5 will be described. That is, in the average pseudo-structure generation process, by inputting the calculation condition value created in the calculation condition value creation process to the production model created in the production model creation process, An average pseudo structure in which the average structure of the semiconductor device is expressed is generated using the result of reproducing the manufacturing process.
[0181]
Next, the variation pseudo structure generation process performed by the variation pseudo structure generation means in step SG6 will be described. That is, in the variation pseudo-structure generation process, the calculation condition values created in the calculation condition value creation step are input to the variation model created in the variation model creation step, thereby calculating a plurality of variation values for a predetermined manufacturing condition. Then, using each of the results obtained by sequentially inputting a plurality of variation values of the predetermined manufacturing condition into the manufacturing model created in the manufacturing model creating step, a plurality of variations expressing the structure variation of the semiconductor device are expressed. A variation pseudo-structure is generated.
[0182]
Next, the capacity calculation process performed by the capacity calculation means in step SG7 will be described. That is, in the capacity calculation step, the average value of the capacitance of a predetermined portion of the semiconductor device is calculated based on the average pseudo structure generated in the average pseudo structure generation step, and a plurality of variations generated in the variation pseudo structure generation step. Based on each of the pseudo structures, a plurality of variation values of the capacitance of a predetermined portion of the semiconductor device are calculated.
[0183]
According to the sixth embodiment, in the manufacturing model creating process, a manufacturing model capable of reproducing the semiconductor device manufacturing process under a predetermined manufacturing condition is created, and the predetermined manufacturing condition can be numerically calculated in the calculation condition value creating process. After creating the calculation condition value expressed as simple data, in the average pseudo-structure generation process, the calculation condition value is input to the manufacturing model to reproduce the semiconductor device manufacturing process and use the result of reproducing the manufacturing process. Since the average pseudo-structure is generated, an average pseudo-structure that accurately represents the structure of the semiconductor device that changes in accordance with the manufacturing process can be generated. Therefore, the average value of the capacitance of a predetermined portion of the semiconductor device can be accurately calculated. Can do.
[0184]
According to the sixth embodiment, in the variation model creating step, after creating a variation model for calculating a plurality of variation values of the predetermined manufacturing condition based on the predetermined manufacturing condition of the semiconductor device, the variation pseudo-structure generating step , The calculation condition value is input to the variation model to calculate a plurality of variation values of the predetermined manufacturing condition, and each of the results obtained by sequentially inputting the plurality of variation values of the predetermined manufacturing condition to the manufacturing model is obtained. In order to generate a plurality of variation pseudo-structures in which the variation in the structure of the semiconductor device is expressed, a plurality of variation pseudo-structures in which the variation in the structure of the semiconductor device corresponding to the variation value of a predetermined manufacturing condition is accurately expressed Therefore, the variation in the capacitance of a predetermined portion of the semiconductor device can be accurately calculated.
[0185]
(Seventh embodiment)
Hereinafter, a capacitance calculation apparatus and a capacitance calculation method according to a seventh embodiment of the present invention will be described with reference to the drawings, taking as an example the calculation of the capacitance of a depletion layer generated in a transistor element.
[0186]
FIG. 21 is a flowchart of the capacity calculation method according to the seventh embodiment.
[0187]
First, the use state designation step performed by the use state designation unit in step SH1 will be described. That is, in the use state designation step, a use state when using the semiconductor device, for example, a use state in which a voltage is applied to each electrode of the transistor and the semiconductor substrate is grounded is designated.
[0188]
FIG. 22 is a cross-sectional view showing an example of a transistor element including a depletion layer in a state where no voltage is applied. In FIG. 22, reference numeral 700 denotes a semiconductor substrate, 701 denotes a source / drain region, 702 denotes a gate insulating film, 703 denotes a gate electrode, 704 denotes a source / drain electrode, and 705 denotes a depletion layer. In FIG. 22, a thick solid line indicates a junction between a channel region and a source region (or drain region), a white circle indicates an electron, and a black circle indicates a hole.
[0189]
FIG. 23 is a diagram showing a change in the position and width of the depletion layer or the position of the junction when a voltage is applied to the transistor element shown in FIG.
[0190]
As shown in FIG. 23, when a voltage is applied to the transistor element, the positions of the depletion layer and the junction are deepened and the width of the depletion layer is expanded.
[0191]
Next, the usage model creation process performed by the usage model creation means in step SH2 will be described. That is, in the usage model creation step, a usage model that is a mathematical expression that can reproduce the usage state specified in the usage state specification step under a predetermined usage condition, for example, a predetermined usage condition (such as a depletion layer shape or a junction position). A usage model in which the dependence on the voltage applied to each electrode of the transistor is expressed, that is, a usage model in which the dependence of the impurity mobility on the electric field strength is expressed.
[0192]
The usage model created in the usage model creation process is stored in the database DH1. As a result, the usage model created in the usage model creation step can be reused.
[0193]
Next, the calculation condition value creating step performed by the calculation condition value creating means in step SH3 will be described. That is, in the calculation condition value creation step, a calculation condition value is created in which a predetermined use condition is expressed as data that can be numerically calculated.
[0194]
Next, the pseudo structure generation process performed by the pseudo structure generation means in step SH4 will be described. That is, in the pseudo-structure generation process, by inputting the calculation condition value created in the calculation condition value creation process to the use model created in the use model creation process, the usage state of the semiconductor device is reproduced, and then the use A pseudo structure is generated using the result of reproducing the state.
[0195]
Next, the capacity calculation process performed by the capacity calculation means in step SH5 will be described. That is, in the capacitance calculation step, the capacitance of a predetermined portion of the semiconductor device is calculated based on the pseudo structure generated in the pseudo structure generation step.
[0196]
According to the seventh embodiment, in the usage model creation step, a usage model that can reproduce the usage state of the semiconductor device under a predetermined usage condition is created, and in the calculation condition value creation step, the predetermined usage condition can be numerically calculated. After creating the calculation condition value expressed as simple data, in the pseudo structure generation process, enter the calculation condition value created in the calculation condition value creation process into the use model created in the use model creation process, and Since the pseudo structure is generated using the result of reproducing the use state and the result of reproducing the use state, a pseudo structure that accurately represents the structure of the semiconductor device that changes in accordance with the use state can be generated. Calculation accuracy can be improved. In addition, since various pseudo structures can be easily generated by changing the calculation condition value, the capacity calculation can be simplified.
[0197]
(Eighth embodiment)
The capacity calculation apparatus and capacity calculation method according to the eighth embodiment of the present invention will be described below with reference to the drawings.
[0198]
Note that the capacity calculation apparatus according to the present embodiment calculates the capacity of a predetermined portion of the semiconductor device using the shape model, dielectric constant model, manufacturing model, or usage model created in the first to seventh embodiments. And a database in which a shape model, a dielectric constant model, a manufacturing model, or a usage model created in advance are sufficiently accumulated.
[0199]
FIG. 24 is a flowchart of the capacity calculation method according to the eighth embodiment.
[0200]
First, the calculation condition value group creation step performed by the calculation condition value group creation means in step SI1 will be described. That is, in the calculation condition value group creation step, when a shape model or a dielectric constant model is used, when a shape or an electrical characteristic of a predetermined component in a semiconductor device is used, when a manufacturing model is used, a predetermined manufacturing condition is a usage model. Is used, a calculation condition value is created in which predetermined use conditions are expressed as data that can be numerically calculated.
[0201]
In the calculation condition value group creation step, a plurality of calculation condition values are sequentially input as calculation condition value groups.
[0202]
Next, the pseudo structure generation process performed by the pseudo structure generation means in step SI2 will be described. That is, in the pseudo structure generation process, when a shape model or a dielectric constant model is used, a shape model or a dielectric constant model extracted from the database DI1 is used. When a manufacturing model is used, it is used for a manufacturing model extracted from the database DI2. In the case of using a model, a plurality of pseudo structures are generated using each of the results obtained by sequentially inputting a plurality of calculation condition values created in the calculation condition value group creation step into the use model extracted from the database DI3. .
[0203]
Next, the capacity calculation process performed by the capacity calculation means in step SI3 will be described. That is, in the capacitance calculation step, a plurality of capacitances of a predetermined portion of the semiconductor device are calculated based on each of the plurality of pseudo structures generated in the pseudo structure generation step.
[0204]
Next, the capacitance value function creating process performed by the capacitance value function creating means in step SI4 will be described. That is, in the capacity value function creation step, for example, by using an approximation method such as a least square method, a plurality of calculation condition values created in the calculation condition value group creation step and a plurality of capacities calculated in the capacity calculation step A capacitance value function that is a function expressing the correlation with the value of is generated.
[0205]
The capacity value function created in the capacity value function creating process is stored in the database DI4. As a result, the capacitance value function created in the capacitance value function creation step can be reused.
[0206]
Next, the calculation condition value creating process performed by the calculation condition value creating means in step SI5 will be described. That is, in the calculation condition value creation step, a calculation condition value is created in which the shape or electrical characteristics of a predetermined component in the semiconductor device, a predetermined manufacturing condition, or a predetermined use condition is expressed as data that can be numerically calculated. .
[0207]
Next, the simple capacity calculation process performed by the simple capacity calculation means in step SI6 will be described. That is, in the simple capacity calculation step, the capacitance of a predetermined part of the semiconductor device is calculated by inputting the calculation condition value created in the calculation condition value creation step into the capacitance value function created in the capacitance value function creation step. .
[0208]
According to the eighth embodiment, in the capacitance value function creating step, a plurality of calculation condition values created in the calculation condition value group creating step, and a plurality of capacitance values of a predetermined portion of the semiconductor device calculated in the capacitance calculating step In order to calculate the capacitance of a predetermined portion of the semiconductor device using the capacitance value function created in the capacitance value function creation step in the simple capacitance calculation step, after creating the capacitance value function expressing the correlation with Since the capacity calculation can be performed using the capacity value function without generating the pseudo structure, the capacity calculation can be simplified. Normally, the capacity value function creating process and the simple capacity calculating process are not performed continuously. In the simple capacity calculating process, a capacity value function created in advance and stored in a database or the like is used.
[0209]
Further, according to the eighth embodiment, since the capacitance value function is created based on the result of the capacitance calculation using the shape model, the dielectric constant model, the manufacturing model, or the usage model, the capacitance value function is used. By performing the capacity calculation, it is possible to easily predict the variation in the capacity from the manufacturing process to the use stage of the semiconductor device.
[0210]
(Ninth embodiment)
The capacity calculation apparatus and capacity calculation method according to the ninth embodiment of the present invention will be described below with reference to the drawings.
[0211]
In addition, the capacity calculation apparatus according to the present embodiment uses the shape model, the dielectric constant model, the manufacturing model, or the usage model created in the first to seventh embodiments, as in the eighth embodiment. It is assumed that a unit for calculating a capacity of a predetermined part of the apparatus is provided, and a database in which a shape model, a dielectric constant model, a manufacturing model, or a usage model created in advance is sufficiently accumulated is provided.
[0212]
FIG. 25 is a flowchart of the capacity calculation method according to the ninth embodiment.
[0213]
First, the target capacity value input process performed by the target capacity value input means in step SJ1 will be described. That is, in the target capacity value input step, the target capacity value that is the target value of the calculated capacity value, which is the capacity value calculated in the subsequent capacity calculation process, and the tolerance between the calculated capacity value and the target capacity value. Enter. Here, as the tolerance, for example, a value obtained by integrating a target capacity value and a predetermined coefficient is used.
[0214]
Next, the calculation condition value setting process performed by the calculation condition value setting means in step SJ2 will be described. That is, in the calculation condition value group creation step, when a shape model or a dielectric constant model is used, when a shape or an electrical characteristic of a predetermined component in a semiconductor device is used, when a manufacturing model is used, a predetermined manufacturing condition is a usage model. Is used, a calculation condition value is created in which predetermined use conditions are expressed as data that can be numerically calculated. At this time, the calculation condition value is determined so that the calculated capacity value becomes equal to the target capacity value.
[0215]
In the calculation condition value creating step, the calculation condition value is calculated until the capacitance value difference, which is the difference between the calculated capacity value and the target capacity value, is smaller than the tolerance input in the target capacity value input step. While being repeatedly changed, a predetermined value is used as an initial value of the calculation condition value in the first calculation condition value creating step.
[0216]
Next, the pseudo structure generation process performed by the pseudo structure generation means in step SJ3 will be described. That is, in the pseudo structure generation process, when using a shape model or a dielectric constant model, when using a manufacturing model for a shape model or a dielectric constant model extracted from the database DJ1, it is used for a manufacturing model extracted from the database DJ2. In the case of using a model, a pseudo structure is generated using a result obtained by inputting the calculation condition value created in the calculation condition value creation step into the use model extracted from the database DJ3.
[0217]
Next, the capacity calculation process performed by the capacity calculation means in step SJ4 will be described. That is, in the capacitance calculation step, the capacitance of a predetermined portion of the semiconductor device is calculated based on the pseudo structure generated in the pseudo structure generation step.
[0218]
Next, the capacitance value difference calculation process performed by the capacitance value difference calculation means in step SJ5 will be described. That is, in the capacitance value difference calculation step, a capacitance value difference that is an absolute value of a difference between the calculated capacitance value calculated in the capacitance calculation step and the target capacitance value input in the target capacitance value input step. Calculate
[0219]
Next, the capacitance value difference determining step performed by the capacitance value difference determining means in step SJ6 will be described. That is, in the capacitance value difference determination step, it is determined whether or not the capacitance value difference calculated in the capacitance value difference calculation step is smaller than the tolerance input in the target capacitance value input step. If the capacitance value difference is smaller than the tolerance, the process proceeds to step SJ7, and if the capacitance value difference is not smaller than the tolerance, the process returns to step SJ2.
[0220]
Next, the pseudo structure output process performed by the pseudo structure output means in step SJ7 will be described. That is, in the pseudo structure output step, the capacitance value difference calculated in the capacitance value difference calculation step is smaller than the tolerance input in the target capacitance value input step, that is, the calculated capacitance value is substantially equal to the target capacitance value. The pseudo structure used for calculation of the calculated capacity value in the case of being equal is output. At this time, in addition to the pseudo structure, calculation condition values used for generating the pseudo structure, such as manufacturing conditions, may be output.
[0221]
According to the ninth embodiment, calculation is performed until the calculated capacitance value, which is the capacitance value of the predetermined portion of the semiconductor device calculated in the capacitance calculation step, becomes substantially equal to the target capacitance value input in the target capacitance value input step. Since the condition value creation process, the pseudo structure generation process, and the capacity calculation process are repeated while changing the calculation condition value in the calculation condition value creation process, the calculation is performed when the calculated capacity value is substantially equal to the target capacity value. A semiconductor in which the capacitance value of a predetermined portion of the semiconductor device becomes substantially equal to the target capacitance value by outputting the pseudo structure used for calculating the capacitance value or the calculation condition value used for generating the pseudo structure. It is possible to know the structure or manufacturing conditions of the apparatus.
[0222]
【The invention's effect】
According to the first capacity calculation device, a pseudo structure in which the shape of the insulating layer is accurately expressed can be generated, so that the accuracy of capacity calculation can be improved and various pseudo structures can be easily changed by changing the calculation condition value. Therefore, the capacity calculation can be simplified.
[0223]
According to the second capacity calculation device, a pseudo structure in which the shape of one component in the semiconductor device is accurately expressed can be generated, so that the accuracy of capacity calculation can be improved and various values can be obtained by changing calculation condition values. Since a simple pseudo structure can be easily generated, capacity calculation can be simplified.
[0224]
According to the third capacity calculation device, since a pseudo structure in which the dielectric constant of one component in the semiconductor device is accurately expressed can be generated, the accuracy of the capacity calculation can be improved and the calculation condition value can be changed. Since various pseudo structures can be easily generated, capacity calculation can be simplified.
[0225]
According to the fourth capacity calculation apparatus, since the pseudo structure in which the structure of the semiconductor device that changes in accordance with the use state can be accurately generated can be generated, the accuracy of the capacity calculation can be improved, and the calculation condition value of Since various pseudo structures can be easily generated by the change, the capacity calculation can be simplified.
[0226]
According to the fifth capacity calculation device, since a pseudo structure in which the shape or dielectric constant of one component in the semiconductor device is accurately expressed can be generated, the accuracy of capacity calculation can be improved, and the calculation condition value of Since various pseudo structures can be easily generated by the change, the capacity calculation can be simplified.
[0227]
According to the sixth capacity calculation apparatus, since the pseudo structure in which the structure of the semiconductor device that changes in accordance with the manufacturing process is accurately expressed can be generated, the accuracy of capacity calculation can be improved, and the calculation condition value of Since various pseudo structures can be easily generated by the change, the capacity calculation can be simplified.
[0228]
In the second to sixth capacitance calculation devices, the correlation between the plurality of calculation condition values created by the calculation condition value creation unit and the values of the plurality of capacitances of a predetermined portion of the semiconductor device calculated by the capacitance calculation unit is expressed. A capacitance value function creating means for creating a capacitance value function, and a simple capacitance calculating means for calculating a capacitance of a predetermined portion of the semiconductor device using the capacitance value function created by the capacitance value function creating means, Since the capacity calculation can be performed using the capacity value function without generating the pseudo structure, the capacity calculation can be simplified.
[0229]
In the second to sixth capacity calculation devices, when the calculation condition value creating means repeatedly changes the calculation condition value until the capacitance value of the predetermined portion of the semiconductor device calculated by the capacitance calculation means becomes substantially equal to the predetermined value. When the capacitance value of a predetermined portion of the semiconductor device becomes substantially equal to the predetermined value, the pseudo structure used to calculate the capacitance value or the calculation condition value used to generate the pseudo structure is output. Thus, the structure or manufacturing conditions of the semiconductor device when the capacitance value of the predetermined portion of the semiconductor device becomes substantially equal to the predetermined value can be known.
[0230]
The fifth or sixth capacity calculation apparatus includes a variation model creating unit that creates a variation model for calculating a plurality of variation values of the predetermined manufacturing condition based on the predetermined manufacturing condition, and the pseudo structure generating unit includes The calculation condition value is input to the variation model to calculate a plurality of variation values of the predetermined manufacturing condition, and each of the results obtained by sequentially inputting the plurality of variation values of the predetermined manufacturing condition to the manufacturing model is used. When a plurality of variation pseudo-structures that express the variation in the structure of the semiconductor device are generated, a plurality of variation pseudo-structures that accurately represent the variation in the structure of the semiconductor device corresponding to the variation value of a predetermined manufacturing condition are generated. Therefore, it is possible to accurately calculate the variation in capacitance of a predetermined portion of the semiconductor device.
[0231]
In the sixth capacity calculating apparatus, when the calculation condition value creating means determines the predetermined manufacturing condition so that the pseudo structure generated by the pseudo structure generating means is equal to the predetermined pseudo structure, the semiconductor device having the predetermined structure A capacity calculation can be performed for.
[0232]
According to the first capacitance calculation method, a pseudo structure in which the shape of the insulating layer is accurately expressed can be generated, so that the accuracy of the capacitance calculation can be improved and various pseudo structures can be easily changed by changing the calculation condition value. Therefore, the capacity calculation can be simplified.
[0233]
According to the second capacity calculation method, since a pseudo structure in which the shape of one component in the semiconductor device is accurately expressed can be generated, the accuracy of capacity calculation can be improved and various values can be obtained by changing calculation condition values. Since a simple pseudo structure can be easily generated, capacity calculation can be simplified.
[0234]
According to the third capacitance calculation method, a pseudo structure in which the dielectric constant of one component in the semiconductor device is accurately expressed can be generated, so that the accuracy of the capacitance calculation can be improved and the calculation condition value can be changed. Since various pseudo structures can be easily generated, capacity calculation can be simplified.
[0235]
According to the fourth capacity calculation method, it is possible to generate a pseudo structure in which the structure of the semiconductor device that changes in accordance with the usage state is accurately expressed, so that the accuracy of capacity calculation can be improved and the calculation condition value of Since various pseudo structures can be easily generated by the change, the capacity calculation can be simplified.
[0236]
According to the fifth capacitance calculation method, since a pseudo structure in which the shape or dielectric constant of one component in the semiconductor device is accurately expressed can be generated, the accuracy of capacitance calculation can be improved, and the calculation condition value of Since various pseudo structures can be easily generated by the change, the capacity calculation can be simplified.
[0237]
According to the sixth capacity calculation method, it is possible to generate a pseudo structure in which the structure of the semiconductor device that changes in accordance with the manufacturing process is accurately expressed, so that the accuracy of capacity calculation can be improved and the calculation condition value of Since various pseudo structures can be easily generated by the change, the capacity calculation can be simplified.
[0238]
In the second to sixth capacitance calculation methods, there is a correlation between a plurality of calculation condition values created in the calculation condition value creation step and a plurality of capacitance values of a predetermined portion of the semiconductor device calculated in the capacitance calculation step. A capacitance value function creating step for creating the expressed capacitance value function, and a simple capacitance calculating step for calculating the capacitance of a predetermined portion of the semiconductor device using the capacitance value function created in the capacitance value function creating step. In this case, the capacity calculation can be performed using the capacity value function without generating a pseudo structure, so that the capacity calculation can be simplified. In actual operation, the capacity value function creating process and the simple capacity calculating process are not performed continuously. In the simple capacity calculating process, the capacity value function created in advance and stored in the database or the like is not used. Used.
[0239]
In the second to sixth capacitance calculation methods, the calculation condition value creation step, the pseudo structure generation step, and the capacitance calculation step are performed in such a manner that the capacitance value of the predetermined portion of the semiconductor device calculated in the capacitance calculation step is substantially equal to the predetermined value. In the calculation condition value creating process, when the calculation condition value is repeatedly included in the repetition process, the capacitance value of the predetermined portion of the semiconductor device is substantially equal to the predetermined value. Structure of semiconductor device when capacitance value of predetermined part of semiconductor device becomes substantially equal to predetermined value by outputting pseudo structure used for calculation of calculation or calculation condition value used for generation of pseudo structure Or manufacturing conditions etc. can be known.
[0240]
The fifth or sixth capacity calculation method includes a variation model creating step for creating a variation model for calculating a plurality of variation values of the predetermined manufacturing condition based on the predetermined manufacturing condition. Then, after calculating a plurality of variation values of a predetermined manufacturing condition by inputting calculation condition values to the variation model, each of the results obtained by sequentially inputting the plurality of variation values of the predetermined manufacturing condition to the manufacturing model is used. When a plurality of variation pseudo-structures that express the variation in the structure of the semiconductor device are generated, a plurality of variation pseudo-structures that accurately represent the variation in the structure of the semiconductor device corresponding to the variation value of a predetermined manufacturing condition are generated. Therefore, it is possible to accurately calculate the variation in capacitance of a predetermined portion of the semiconductor device.
[0241]
In the sixth capacity calculation method, when the calculation condition value creating step includes a step of determining a predetermined manufacturing condition so that the pseudo structure generated in the pseudo structure generation step is equal to the predetermined pseudo structure, Capacitance calculation can be performed for a semiconductor device having a structure.
[Brief description of the drawings]
FIG. 1 is a flowchart of a capacity calculation method according to a first embodiment.
FIG. 2 is a diagram illustrating each process of a shape model creation step in the capacity calculation method.
FIG. 3 is a cross-sectional view showing an example of a pseudo structure in which a structure of a wiring portion including a void is expressed in the capacitance calculation method.
FIG. 4 is a plot of data obtained by actually measuring the shape of voids in the capacity calculation method.
FIG. 5 is a diagram illustrating a shape model in which a dependency of a void shape on a wiring interval is expressed in the capacitance calculation method.
FIG. 6 is a diagram illustrating each process of a pseudo structure generation step in the capacity calculation method.
FIG. 7 is a cross-sectional view showing an example of a pseudo structure generated in a pseudo structure generation step in the capacity calculation method.
FIG. 8 is a flowchart of a capacity calculation method according to a second embodiment.
FIG. 9 is a cross-sectional view showing an example of a pseudo structure generated in a pseudo structure generation step in the capacity calculation method.
FIG. 10 is a flowchart of a capacity calculation method according to a third embodiment.
FIG. 11 is a cross-sectional view illustrating an example of a transistor element including a depletion layer in the capacitance calculation method.
FIG. 12 is a cross-sectional view showing an example of a pseudo structure generated in a pseudo structure generation step in the capacity calculation method.
FIG. 13 is a flowchart of a capacity calculation method according to a modification of the third embodiment.
FIG. 14 is a cross-sectional view showing an example of a pseudo structure in which the structure of a transistor element including a depletion layer is expressed in the capacitance calculation method.
FIG. 15 is a diagram showing an example of a method for defining a depletion layer in the capacitance calculation method.
FIG. 16 is a flowchart of a capacity calculation method according to the fourth embodiment.
FIG. 17 is a flowchart of a capacity calculation method according to a fifth embodiment.
FIG. 18 is a cross-sectional view showing an example of an STI in the capacity calculation method.
FIG. 19 is a diagram illustrating an example of variations in STI width in the capacity calculation method.
FIG. 20 is a flowchart of a capacity calculation method according to the sixth embodiment.
FIG. 21 is a flowchart of a capacity calculation method according to a seventh embodiment.
FIG. 22 is a cross-sectional view showing an example of a transistor element including a depletion layer in a state where no voltage is applied in the capacitance calculation method.
FIG. 23 is a diagram showing changes in the position and width of a depletion layer or the position of a junction when a voltage is applied to a transistor element in the capacitance calculation method.
FIG. 24 is a flowchart of a capacity calculation method according to an eighth embodiment.
FIG. 25 is a flowchart of the capacity calculation method according to the ninth embodiment.
FIG. 26 is a three-dimensional view showing an example of a wiring structure in a conventional capacity calculation method.
FIG. 27 is a cross-sectional view showing an example of a pseudo structure used for wiring capacity simulation in a conventional capacity calculation method.
FIG. 28 is a cross-sectional view showing an example of a MOS transistor in a conventional capacitance calculation method.
FIG. 29 is a cross-sectional view showing an example of an STI for separating two transistor elements in a conventional capacitance calculation method.
FIG. 30 is a cross-sectional view showing an example of a wiring structure in a conventional capacitance calculation method.
[Explanation of symbols]
100 first wiring layer
101 Second wiring layer
102 1st interlayer insulation film
102a Tapered portion of first interlayer insulating film
103 2nd interlayer insulation film
104 Passivation film
104a void
110 First wiring layer
111 Second wiring layer
112 First interlayer insulating film
113 Second interlayer insulating film
114 Passivation film
114a void
200 First wiring layer
201 Second wiring layer
202 first interlayer insulating film
203 Second interlayer insulating film
204 Passivation film
204a void
300 Semiconductor substrate
300a Surface of semiconductor substrate
301 Source / drain region
302 Gate insulating film
303 Gate electrode
304 Depletion layer
310 Semiconductor substrate
310a Semiconductor substrate surface
311 Source / drain region
312 Gate insulation film
313 Gate electrode
314 Depletion layer
320 Semiconductor substrate
320a Semiconductor substrate surface
321 Source / drain region
322 Gate insulation film
323 Gate electrode
324 Depletion layer
500 Semiconductor substrate
501 Source / drain region
502 Gate insulating film
503 Gate electrode
504 STI
700 Semiconductor substrate
701 Source / drain region
702 Gate insulating film
703 Gate electrode
704 Source / drain electrodes
705 depletion layer
a Junction position
b Depth layer thickness
c Depth layer thickness
d STI width
e STI height

Claims (24)

Based on a pseudo structure in which the structure of a semiconductor device having a wiring portion formed by laminating a wiring layer made of a conductive film and an insulating layer made of a dielectric film is expressed as data capable of numerical calculation, the capacitance of the wiring portion is A capacity calculation device for calculating,
A shape model creating means for creating a shape model that is a mathematical expression expressing the dependency of the shape of the insulating layer on the shape of the wiring layer;
A calculation condition value creating means for creating a calculation condition value expressed as data capable of numerical calculation of at least the shape of the wiring layer;
By inputting the calculation condition value created by the calculation condition value creating means into the shape model created by the shape model creating means, the shape of the insulating layer is obtained, and the pseudo structure is obtained using the shape of the insulating layer. Pseudo structure generating means for generating;
A capacity calculation apparatus comprising: capacity calculation means for calculating the capacitance of the wiring portion based on the pseudo structure generated by the pseudo structure generation means. A capacity calculation device that calculates the capacity of a predetermined part of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of the structure of a semiconductor device composed of a plurality of components,
A shape model creating means for creating a shape model that is a mathematical expression expressing the dependence of the shape of one component in the semiconductor device on the shape or electrical characteristics of another component in the semiconductor device;
A calculation condition value creating means for creating a calculation condition value expressed as data capable of numerical calculation of at least the shape or electrical characteristics of the other components;
By inputting the calculation condition value created by the calculation condition value creating means into the shape model created by the shape model creating means, the shape of the one component element is obtained and the shape of the one component element is used. Pseudo structure generating means for generating the pseudo structure;
A capacity calculation apparatus comprising: capacity calculation means for calculating a capacity of a predetermined portion of the semiconductor device based on the pseudo structure generated by the pseudo structure generation means. A capacity calculation device that calculates the capacity of a predetermined part of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of the structure of a semiconductor device composed of a plurality of components,
A dielectric constant model creating means for creating a dielectric constant model that is a mathematical expression expressing a dependence relationship of a dielectric constant of one component in the semiconductor device on a shape or an electrical characteristic of another component in the semiconductor device;
A calculation condition value creating means for creating a calculation condition value expressed as data capable of numerical calculation of at least the shape or electrical characteristics of the other components;
By inputting the calculation condition value created by the calculation condition value creating means into the dielectric constant model created by the dielectric constant model creating means, the dielectric constant of the one component is obtained, and the dielectric constant of the one component is obtained. Pseudo structure generating means for generating the pseudo structure using a rate;
A capacity calculation apparatus comprising: capacity calculation means for calculating a capacity of a predetermined portion of the semiconductor device based on the pseudo structure generated by the pseudo structure generation means. A capacity calculation device that calculates the capacity of a predetermined part of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of the structure of a semiconductor device composed of a plurality of components,
A use model creating means for creating a use model that is a mathematical formula capable of reproducing the use state of the semiconductor device under a predetermined use condition;
A calculation condition value creating means for creating a calculation condition value in which at least the predetermined use condition is expressed as data that can be numerically calculated;
By inputting the calculation condition value created by the calculation condition value creating means into the use model created by the use model creating means, the use state of the semiconductor device is reproduced and the result of reproducing the use state is used. Pseudo structure generating means for generating the pseudo structure;
A capacity calculation apparatus comprising: capacity calculation means for calculating a capacity of a predetermined portion of the semiconductor device based on the pseudo structure generated by the pseudo structure generation means. A capacity calculation device that calculates the capacity of a predetermined part of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of the structure of a semiconductor device composed of a plurality of components,
A manufacturing model creating means for creating a manufacturing model that is a mathematical expression expressing a dependency of a shape or dielectric constant of one component in the semiconductor device on a predetermined manufacturing condition in a manufacturing process of the semiconductor device;
A calculation condition value creating means for creating a calculation condition value expressed as data capable of numerical calculation of at least the predetermined manufacturing condition;
By inputting the calculation condition value created by the calculation condition value creation means into the production model created by the production model creation means, the shape or dielectric constant of the one component is obtained, and the shape of the one component Or pseudo structure generating means for generating the pseudo structure using a dielectric constant;
A capacity calculation apparatus comprising: capacity calculation means for calculating a capacity of a predetermined portion of the semiconductor device based on the pseudo structure generated by the pseudo structure generation means. The calculation condition value creating means creates a plurality of calculation condition values,
The pseudo structure generation means generates a plurality of the pseudo structures based on each of the plurality of calculation condition values created by the calculation condition value creation means,
The capacitance calculating means calculates a plurality of capacitances of a predetermined portion of the semiconductor device based on each of the plurality of pseudo structures generated by the pseudo structure generating means,
A capacitance value function which is a function expressing a correlation between a plurality of calculation condition values created by the calculation condition value creation unit and a plurality of capacitance values of a predetermined portion of the semiconductor device calculated by the capacitance calculation unit. A capacity value function creating means to create;
6. The apparatus according to claim 2 , further comprising simple capacitance calculation means for calculating a capacitance of a predetermined portion of the semiconductor device using the capacitance value function created by the capacitance value function creation means. The capacity calculation apparatus according to item 1. The calculation condition value creating means repeatedly changes the calculation condition value until the capacitance value of the predetermined portion of the semiconductor device calculated by the capacitance calculation means becomes substantially equal to a predetermined value . 6. The capacity calculation apparatus according to any one of 5 above. Based on the predetermined manufacturing condition, further comprising a variation model creating means for creating a variation model that is a mathematical formula for calculating a plurality of variation values of the predetermined manufacturing condition,
The pseudo structure generation unit calculates a plurality of variation values of the predetermined manufacturing condition by inputting the calculation condition value created by the calculation condition value creation unit into the variation model created by the variation model creation unit. A plurality of variations in which the variation of the structure of the semiconductor device is expressed using each of the results obtained by sequentially inputting a plurality of variation values of the predetermined manufacturing condition into the manufacturing model created by the manufacturing model creating means Generate a pseudo-structure,
The capacity calculation unit, based on each of a plurality of variations pseudo structure the pseudo structure generating means has generated, according to claim 5, wherein calculating a plurality of variation values in the capacitor of a predetermined portion of the semiconductor device Capacity calculator. A capacity calculation device that calculates the capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of the structure of a semiconductor device composed of a plurality of components,
Manufacturing model creating means for creating a manufacturing model that is a mathematical formula that can reproduce the manufacturing process of the semiconductor device under predetermined manufacturing conditions;
Calculation condition value creating means for creating a calculation condition value in which at least the predetermined manufacturing condition is expressed as numerically calculable data;
By inputting the calculation condition value created by the calculation condition value creating means into the production model created by the manufacturing model creating means, the manufacturing process of the semiconductor device is reproduced and the result of reproducing the manufacturing process is used. Pseudo structure generating means for generating the pseudo structure;
Based on the pseudo structure generated by the pseudo structure generating means, a predetermined portion of the semiconductor device is A capacity calculating means for calculating the capacity;
The calculation condition value creating means creates a plurality of calculation condition values,
The pseudo structure generation means generates a plurality of the pseudo structures based on each of the plurality of calculation condition values created by the calculation condition value creation means,
The capacitance calculating means calculates a plurality of capacitances of a predetermined portion of the semiconductor device based on each of the plurality of pseudo structures generated by the pseudo structure generating means,
A capacitance value function which is a function expressing a correlation between a plurality of calculation condition values created by the calculation condition value creation unit and a plurality of capacitance values of a predetermined portion of the semiconductor device calculated by the capacitance calculation unit. A capacity value function creating means to create;
A capacity calculating apparatus, further comprising: a simple capacity calculating means for calculating a capacity of a predetermined portion of the semiconductor device using the capacity value function created by the capacity value function creating means. A capacity calculation device that calculates the capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of the structure of a semiconductor device composed of a plurality of components,
Manufacturing model creating means for creating a manufacturing model that is a mathematical formula that can reproduce the manufacturing process of the semiconductor device under predetermined manufacturing conditions;
Calculation condition value creating means for creating a calculation condition value in which at least the predetermined manufacturing condition is expressed as numerically calculable data;
By inputting the calculation condition value created by the calculation condition value creating means into the production model created by the manufacturing model creating means, the manufacturing process of the semiconductor device is reproduced and the result of reproducing the manufacturing process is used. Pseudo structure generating means for generating the pseudo structure;
Based on the pseudo structure generated by the pseudo structure generating means, and capacity calculating means for calculating the capacity of a predetermined portion of the semiconductor device,
The calculation condition value creating means repeatedly changes the calculation condition value until the capacitance value of the predetermined portion of the semiconductor device calculated by the capacitance calculation means becomes substantially equal to a predetermined value. A capacity calculation device that calculates the capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of the structure of a semiconductor device composed of a plurality of components,
Manufacturing model creating means for creating a manufacturing model that is a mathematical formula that can reproduce the manufacturing process of the semiconductor device under predetermined manufacturing conditions;
Calculation condition value creating means for creating a calculation condition value in which at least the predetermined manufacturing condition is expressed as numerically calculable data;
By inputting the calculation condition value created by the calculation condition value creating means into the production model created by the manufacturing model creating means, the manufacturing process of the semiconductor device is reproduced and the result of reproducing the manufacturing process is used. Pseudo structure generating means for generating the pseudo structure;
Based on the pseudo structure generated by the pseudo structure generating means, and capacity calculating means for calculating the capacity of a predetermined portion of the semiconductor device,
Based on the predetermined manufacturing condition, further comprising a variation model creating means for creating a variation model that is a mathematical formula for calculating a plurality of variation values of the predetermined manufacturing condition,
The pseudo structure generation unit calculates a plurality of variation values of the predetermined manufacturing condition by inputting the calculation condition value created by the calculation condition value creation unit into the variation model created by the variation model creation unit. A plurality of variations in which the variation of the structure of the semiconductor device is expressed using each of the results obtained by sequentially inputting a plurality of variation values of the predetermined manufacturing condition into the manufacturing model created by the manufacturing model creating means Generate a pseudo-structure,
The capacity calculation unit calculates a plurality of variation values in the capacitance of a predetermined portion of the semiconductor device based on each of the plurality of variation pseudo-structures generated by the pseudo-structure generation unit. A capacity calculation device that calculates the capacity of a predetermined part of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of the structure of a semiconductor device composed of a plurality of components ,
Manufacturing model creating means for creating a manufacturing model that is a mathematical formula that can reproduce the manufacturing process of the semiconductor device under predetermined manufacturing conditions;
Calculation condition value creating means for creating a calculation condition value in which at least the predetermined manufacturing condition is expressed as numerically calculable data;
By inputting the calculation condition value created by the calculation condition value creating means into the production model created by the manufacturing model creating means, the manufacturing process of the semiconductor device is reproduced and the result of reproducing the manufacturing process is used. Pseudo structure generating means for generating the pseudo structure;
Based on the pseudo structure generated by the pseudo structure generating means, and capacity calculating means for calculating the capacity of a predetermined portion of the semiconductor device,
The calculation condition value creation means, said pseudo-structure the pseudo structure generation means generates so is equal to a predetermined the pseudo structure, the predetermined capacity computing device you characterized by determining the production conditions. Based on a pseudo structure in which the structure of a semiconductor device having a wiring portion formed by laminating a wiring layer made of a conductive film and an insulating layer made of a dielectric film is expressed as data capable of numerical calculation, the capacitance of the wiring portion is A capacity calculation method for calculating,
A shape model creating step for creating a shape model that is a mathematical expression expressing the dependency of the shape of the insulating layer on the shape of the wiring layer;
A calculation condition value creating step for creating a calculation condition value expressed as data capable of numerical calculation of at least the shape of the wiring layer;
After obtaining the shape of the insulating layer by inputting the calculation condition value created in the calculation condition value creating step into the shape model created in the shape model creating step, the pseudo model is obtained using the shape of the insulating layer. A pseudo-structure generation step for generating a structure;
And a capacitance calculation step of calculating a capacitance of the wiring portion based on the pseudo structure generated in the pseudo structure generation step. A capacity calculation method for calculating a capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of a structure of a semiconductor device composed of a plurality of components,
A shape model creating step of creating a shape model that is a mathematical expression expressing the dependency of the shape of one component in the semiconductor device on the shape or electrical characteristics of another component in the semiconductor device;
A calculation condition value creating step of creating a calculation condition value expressed as data capable of numerical calculation of at least the shape or electrical characteristics of the other components;
After obtaining the shape of the one component by inputting the calculation condition value created in the calculation condition value creating step into the shape model created in the shape model creating step, the shape of the one component A pseudo-structure generating step of generating the pseudo-structure using
And a capacitance calculation step of calculating a capacitance of a predetermined portion of the semiconductor device based on the pseudo structure generated in the pseudo structure generation step. A capacity calculation method for calculating a capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of a structure of a semiconductor device composed of a plurality of components,
A dielectric constant model creating step of creating a dielectric constant model that is a mathematical expression expressing a dependency relationship of a dielectric constant of one constituent element in the semiconductor device with respect to a shape or an electrical characteristic of another constituent element in the semiconductor device;
A calculation condition value creating step of creating a calculation condition value expressed as data capable of numerical calculation of at least the shape or electrical characteristics of the other components;
After obtaining the dielectric constant of the one component by inputting the calculation condition value created in the calculation condition value creation step into the dielectric constant model created in the dielectric constant model creation step, the one configuration A pseudo-structure generating step for generating the pseudo-structure using a dielectric constant of an element;
And a capacitance calculation step of calculating a capacitance of a predetermined portion of the semiconductor device based on the pseudo structure generated in the pseudo structure generation step. A capacity calculation method for calculating a capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of a structure of a semiconductor device composed of a plurality of components,
A use model creating step of creating a use model that is a mathematical formula capable of reproducing the use state of the semiconductor device under a predetermined use condition;
A calculation condition value creating step for creating a calculation condition value in which at least the predetermined use condition is expressed as data capable of numerical calculation;
By inputting the calculation condition value created in the calculation condition value creation step into the use model created in the use model creation step, the result of reproducing the use state is reproduced after reproducing the use state of the semiconductor device. A pseudo-structure generating step using the pseudo-structure to generate the pseudo-structure;
And a capacitance calculation step of calculating a capacitance of a predetermined portion of the semiconductor device based on the pseudo structure generated in the pseudo structure generation step. A capacity calculation method for calculating a capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of a structure of a semiconductor device composed of a plurality of components,
A manufacturing model creating step for creating a manufacturing model that is a mathematical expression expressing a dependency of a shape or dielectric constant of one component in the semiconductor device on a predetermined manufacturing condition in the manufacturing step of the semiconductor device;
A calculation condition value creating step of creating a calculation condition value expressed as data capable of numerical calculation of at least the predetermined manufacturing condition;
After obtaining the shape or dielectric constant of the one component by inputting the calculation condition value created in the calculation condition value creation step into the production model created in the production model creation step, the one configuration A pseudo-structure generating step of generating the pseudo-structure using an element shape or dielectric constant;
A capacitance calculation method comprising: a capacitance calculation method for calculating a capacitance of a predetermined portion of the semiconductor device based on the pseudo structure generated in the pseudo structure generation step. The calculation condition value creating step includes a step of creating a plurality of calculation condition values,
The pseudo structure generation step includes a step of generating a plurality of the pseudo structures based on each of a plurality of calculation condition values created in the calculation condition value creation step,
The capacitance calculation step includes a step of calculating a plurality of capacitances of a predetermined portion of the semiconductor device based on each of the plurality of pseudo structures generated in the pseudo structure generation step,
After the capacity calculation step,
A capacitance value that is a function expressing a correlation between a plurality of calculation condition values created in the calculation condition value creation step and a plurality of capacitance values of a predetermined portion of the semiconductor device calculated in the capacitance calculation step. Capacitance value function creation process for creating a function,
18. A simple capacitance calculation step of calculating a capacitance of a predetermined portion of the semiconductor device using the capacitance value function created in the capacitance value function creation step. 18 . The capacity calculation method according to claim 1. The calculation condition value creating step, the pseudo structure generation step, and the capacitance calculation step are performed until the capacitance value of a predetermined portion of the semiconductor device calculated in the capacitance calculation step is substantially equal to a predetermined value. The capacity calculation method according to any one of claims 14 to 17 , further comprising an iterative process that is repeatedly performed while changing a calculation condition value in the value creating process. Before the pseudo structure generating step, further comprising a variation model creating step of creating a variation model that is a mathematical formula for calculating a plurality of variation values of the predetermined manufacturing condition based on the predetermined manufacturing condition,
The pseudo structure generation step calculates a plurality of variation values of the predetermined manufacturing condition by inputting the calculation condition value created in the calculation condition value creation step into the variation model created in the variation model creation step. Then, using each of the results obtained by sequentially inputting a plurality of variation values of the predetermined manufacturing condition into the manufacturing model created in the manufacturing model creating step, the variation in the structure of the semiconductor device is expressed. Generating a plurality of variation pseudo-structures;
The capacity calculation step, claims based on said each of the plurality of variation pseudo structure generated in the pseudo-structure generation step, characterized in that it comprises a step of computing a plurality of variation values in the capacitor of a predetermined portion of the semiconductor device Item 18. A capacity calculation method according to Item 17 . A capacity calculation method for calculating a capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of a structure of a semiconductor device composed of a plurality of components,
A manufacturing model creating step for creating a manufacturing model which is a mathematical formula capable of reproducing the manufacturing process of the semiconductor device under predetermined manufacturing conditions;
Calculation condition value creating means for creating a calculation condition value in which at least the predetermined manufacturing condition is expressed as numerically calculable data;
By reproducing the manufacturing process of the semiconductor device by inputting the calculation condition value created in the calculation condition value creating process into the manufacturing model created in the manufacturing model creating process, the result of reproducing the manufacturing process is A pseudo-structure generating step of generating the pseudo-structure using:
A capacitance calculation step of calculating a capacitance of a predetermined portion of the semiconductor device based on the pseudo structure generated in the pseudo structure generation step;
The calculation condition value creating step includes a step of creating a plurality of calculation condition values,
The pseudo structure generation step includes a step of generating a plurality of the pseudo structures based on each of a plurality of calculation condition values created in the calculation condition value creation step,
The capacitance calculation step includes a step of calculating a plurality of capacitances of a predetermined portion of the semiconductor device based on each of the plurality of pseudo structures generated in the pseudo structure generation step,
After the capacity calculation step,
A capacitance value that is a function expressing a correlation between a plurality of calculation condition values created in the calculation condition value creation step and a plurality of capacitance values of a predetermined portion of the semiconductor device calculated in the capacitance calculation step. Capacitance value function creation process for creating a function,
A capacitance calculation method, further comprising: a simple capacitance calculation step of calculating a capacitance of a predetermined portion of the semiconductor device using the capacitance value function created in the capacitance value function creation step. A capacity calculation method for calculating a capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of a structure of a semiconductor device composed of a plurality of components,
A manufacturing model creating step for creating a manufacturing model which is a mathematical formula capable of reproducing the manufacturing process of the semiconductor device under predetermined manufacturing conditions;
Calculation condition value creating means for creating a calculation condition value in which at least the predetermined manufacturing condition is expressed as numerically calculable data;
By reproducing the manufacturing process of the semiconductor device by inputting the calculation condition value created in the calculation condition value creating process into the manufacturing model created in the manufacturing model creating process, the result of reproducing the manufacturing process is A pseudo-structure generating step of generating the pseudo-structure using:
A capacitance calculation step of calculating a capacitance of a predetermined portion of the semiconductor device based on the pseudo structure generated in the pseudo structure generation step;
The calculation condition value creation step, the pseudo structure generation step, and the capacitance calculation step are performed until the capacitance value of the predetermined portion of the semiconductor device calculated in the capacitance calculation step is substantially equal to a predetermined value. A capacity calculation method characterized by further comprising a repetition step of repeatedly performing the value generation step while changing the calculation condition value. A capacity calculation method for calculating a capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of a structure of a semiconductor device composed of a plurality of components,
A manufacturing model that is a mathematical formula that can reproduce the manufacturing process of the semiconductor device under predetermined manufacturing conditions. Manufacturing model creation process to create
Calculation condition value creating means for creating a calculation condition value in which at least the predetermined manufacturing condition is expressed as numerically calculable data;
By reproducing the manufacturing process of the semiconductor device by inputting the calculation condition value created in the calculation condition value creating process into the manufacturing model created in the manufacturing model creating process, the result of reproducing the manufacturing process is A pseudo-structure generating step of generating the pseudo-structure using:
A capacitance calculation step of calculating a capacitance of a predetermined portion of the semiconductor device based on the pseudo structure generated in the pseudo structure generation step;
Before the pseudo structure generating step, further comprising a variation model creating step of creating a variation model that is a mathematical formula for calculating a plurality of variation values of the predetermined manufacturing condition based on the predetermined manufacturing condition,
The pseudo structure generation step calculates a plurality of variation values of the predetermined manufacturing condition by inputting the calculation condition value created in the calculation condition value creation step into the variation model created in the variation model creation step. Then, using each of the results obtained by sequentially inputting a plurality of variation values of the predetermined manufacturing condition into the manufacturing model created in the manufacturing model creating step, the variation in the structure of the semiconductor device is expressed. Generating a plurality of variation pseudostructures;
The capacitance calculating step includes a step of calculating a plurality of variation values in a capacitance of a predetermined portion of the semiconductor device based on each of the plurality of variation pseudo-structures generated in the pseudo-structure generating step. Method of calculation. A capacity calculation method for calculating a capacity of a predetermined portion of the semiconductor device based on a pseudo structure expressed as data capable of numerical calculation of a structure of a semiconductor device composed of a plurality of components,
A manufacturing model creating step for creating a manufacturing model which is a mathematical formula capable of reproducing the manufacturing process of the semiconductor device under predetermined manufacturing conditions;
Calculation condition value creating means for creating a calculation condition value in which at least the predetermined manufacturing condition is expressed as numerically calculable data;
By reproducing the manufacturing process of the semiconductor device by inputting the calculation condition value created in the calculation condition value creating process into the manufacturing model created in the manufacturing model creating process, the result of reproducing the manufacturing process is A pseudo-structure generating step of generating the pseudo-structure using:
A capacitance calculating step of calculating a capacitance of a predetermined portion of the semiconductor device based on the pseudo structure generated in the pseudo structure generating step;
The calculation condition value creation process, the so said pseudo structure generated in the pseudo-structure generating step is equal to a predetermined the pseudo structure, you comprising the step of determining the predetermined production conditions ml Quantity calculation method .

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