JPH0581146A - Device with state holding function - Google Patents

Abstract

PURPOSE:To provide a means capable of recognizing an abnormal state by resetting when a termination processing of a CPU can not be performed, leaving a flag showing the abnormal state. CONSTITUTION:When a preliminary operation to pull out a main battery 9 in an operation state exists, the detection of the preliminary operation that the main battery 9 is pulled out is notified to a CPU 1 by a battery pull-out detection switch 10. When the CPU 1 does not terminate a clock stop, the CPU 1 is made an initial state by resetting the CPU 1 by a CPU reset control circuit 6 from the detection signal of a voltage detection circuit 8 and the fact that an abnormal operation exists in an abnormal storage circuit 12 is stored by the detection signal of the voltage detection circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery-operated portable terminal device having a state holding function.

[0002] In recent years, electronic devices are driven by batteries so that they can be carried, and their applications are rapidly expanding. It is necessary from a cost and handling standpoint to cut off the power supply as much as possible to extend the battery life when such a battery-powered device (handheld computer, laptop computer, palmtop computer, etc.) is not used. To be done.

Further, since the battery is often replaced, in this type of device, it is necessary to guarantee the data even if the battery is pulled out during the operation of the device. However, if the termination process cannot be performed for some reason, it is necessary to notify the operator that the memory data cannot be guaranteed due to the removal of the battery.

[0004]

2. Description of the Related Art Conventionally, many devices of this type have not been guaranteed to operate when the battery is removed during operation. Also,
The device that guarantees the removal of the battery during operation has been designed on the assumption that the voltage drop due to the removal of the battery can be detected and the termination process can be performed within a short time when the voltage can be held by the capacitor or the like. Here, the sub battery is a battery that can be recharged with a nickel-cadmium battery, is charged from the main battery, and supplies a voltage to the circuit when the main battery does not work.
Although the voltage is insufficient for the operation of the circuit, it is sufficient for maintaining the state of the circuit.

FIG. 4 is a block diagram of a conventional portable terminal device. In the figure, 1 is a processor for controlling (hereinafter CP
U), 2 is a storage device (RAM / ROM) for storing programs and data, 3 is a bus for transmitting / receiving data to / from the CPU 1, 4 is a clock generator for supplying an operation clock of the device, and 5 is control of clock oscillation An oscillation control unit 7 is a power supply control unit that stabilizes and outputs a voltage from the main battery 9 and the sub battery 11, and 9 is a main battery that supplies operating power of the device.
Is a battery pull-out detection switch that sends a signal when removing the holding metal fitting that is removed when pulling out the battery, 11 is a sub-battery that supplies the holding power of the device when the main battery 9 is pulled out, and 13 is for stopping the operation of the device This is a stop switch that the operator presses.

In the apparatus shown in the figure, when the stop switch 13 is pressed, the CPU 1 detects the pressing and instructs the oscillation controller 5 to stop the clock generation. The oscillation controller 5 causes the clock generator 4 to stop the clock generation. And, as it is, it becomes a standby state.

When the main battery 9 is pulled out during operation, the CPU 1 causes a non-maskable interrupt (NMI) from the battery pull-out detection switch 10 immediately before pulling out.
Received and entered the closing process.

When the termination process is completed normally, an instruction is given to the oscillation controller 5 to stop the clock. However, if the processing is not completed within a certain period of time due to some factor (such as an abnormal state occurring in software processing), the voltage of the sub-battery decreases, and the termination processing cannot be completed. In such a case, even if the main battery is reinserted, the internal state of the CPU is not maintained because the termination processing has not been completed, and the operation of the business resumption program at power-on becomes abnormal, and It often causes CPU runaway, and the cause of runaway is unknown.

[0009]

When the battery is pulled out during operation, the CPU often runs out of control.
At this time, there was a problem that the cause of runaway was unknown.

In view of the above points, the present invention provides a CP
It is an object of the present invention to provide means for grasping an abnormal state by resetting when U termination processing cannot be performed and leaving a flag indicating the abnormal state.

[0011]

The above-mentioned problems can be solved by a device having a state holding function constructed as follows. FIG. 1 is a principle diagram of the present invention.

When the stop switch 13 is detected to be turned on, a holding power is supplied to the entire circuit to hold the state, and the CPU has a state holding function to be in a standby state when the clock is stopped. In a device that maintains the state with the sub battery 11 even if it is removed, it detects that the voltage of the power supply 7 has dropped below a predetermined voltage and the battery pull-out detection switch 10 that detects the preliminary operation of pulling out the battery and sends a detection signal. A voltage detection circuit 8 for sending a signal to the CPU 1, a CPU reset control circuit 6 for supplying a reset signal to the CPU 1 by the signal, and an abnormality storage circuit 12 for storing that the battery voltage has dropped below a predetermined voltage by the signal. When there is a preliminary operation of pulling out the main battery 9 in the operating state, the detection of the preliminary operation of pulling out the main battery 9 by the battery pull-out detection switch 10 is performed.
If U1 is notified and the CPU1 does not finish the clock stop, the CPU reset control circuit 6 resets the CPU1 by the detection signal of the voltage detection circuit 8 to initialize the CPU1 and the voltage detection circuit 8 The abnormality storage circuit 12 is configured to store the fact that an abnormal operation has occurred according to a detection signal.

[0013]

[Function] When there is a preliminary operation to pull out the main battery 9 in the operating state, the main battery 9 is pulled by the battery pull-out detection switch 10.
The CPU 1 is notified of the detection of the preparatory movement for pulling out.

When the CPU 1 does not finish the clock stop, the CPU reset control circuit 6 resets the CPU 1 by the detection signal of the voltage detection circuit 8 to initialize the CPU 1 and the detection signal of the voltage detection circuit 8. The abnormal memory circuit 12 stores the fact that an abnormal operation has occurred.

[0015]

2 is a block diagram of an embodiment of the present invention. In the figure, 6 is a CPU reset control circuit which supplies a reset signal to a CPU by a signal of a voltage detection circuit 8, 8 is a voltage detection circuit which detects that the voltage of a power supply has dropped below a predetermined voltage, and sends out a signal, Reference numeral 12 is an abnormality storage circuit for storing that the battery voltage is abnormally lowered by the signal of the voltage detection circuit 8. In addition, the same reference numerals as those in FIG. 4 are the same.

When the main battery 9 is pulled out during operation, the CPU 1 receives a non-maskable interrupt (NMI) from the battery pull-out detection switch 10 immediately before pulling out, and enters a termination process.

When the termination process is completed normally, the same operation as the conventional one is performed. However, if the processing is not completed within a certain time due to some reason, the voltage drops. A capacitor is inserted in the power supply circuit for voltage stabilization, and a voltage that allows the circuit to operate for a certain period of time is supplied even when the battery is removed. This period is called voltage guarantee time, which is about microsecond. If the termination processing is not completed within the voltage guarantee time, the clock is operating. Therefore, even if the voltage stops below a certain level, if the clock is operating, the voltage detection circuit 8 detects that the voltage of the battery has become less than a predetermined voltage and sends a signal.

Then, the CPU reset control circuit 6 forcibly resets the CPU1 to set the CPU1 in the initial state to prevent runaway, and the abnormal memory circuit 12 is set by the signal to cause an abnormal voltage. Memorize

When the main battery 9 is inserted and restarted,
Since the abnormality storage circuit 12 stores that the voltage abnormality has occurred, the abnormality factor can be notified to the operator or saved as logging data.

FIG. 3 shows an embodiment of the CPU reset control circuit 6 and the abnormality storage circuit 12. In the figure, 21 to 24 are OR circuits, 25 and 26 are flip-flops (FF), and 27 is a delay circuit. The reset signal is formed by ORing the POW reset and the reset switch by the OR circuit 21 and the abnormality detection reset created by this control circuit by the OR circuit 24. The POW reset is a signal that is turned on to prevent the CPU 1 from running away when both the sub-battery and the main battery are below a certain voltage, and is turned off when the device is reset and the voltage of the main battery is restored to the operating voltage. The reset switch is a signal of a switch that the operator operates to reset the device when the operator wants to reset the device to the initial state.

Two flip-flops (FF) are used in this circuit, and the first stage FF25 is a voltage detection circuit.
When 8 outputs the signal that detected the voltage drop, it samples the signal that controls the oscillation of the clock. If the clock is not stopped, the Q output is turned on and an abnormal reset is generated. Here, the delay circuit 27 is provided to reset the FF 25 with the output signal of the voltage detection circuit 8 and then set it with a clock. The FF26 in the second stage stores the occurrence of an abnormal state and is set by setting the FF25 in the first stage. The status clear from the CPU and the POW reset / reset switch are set by the OR circuit 22. Cleared by taking the logical sum.

When the main battery is reinserted and the voltage is restored, the first stage FF 25 resets the POW by the OR circuit 21,
It is cleared by entering the reset input via the OR circuit 22 and OR circuit 23, and the reset created by the OR circuit 24 for the outputs of the FF 25 and the OR circuit 21 is released when the output of the OR circuit 21 ends. To be done.

As described above, the CPU is controlled by controlling the reset and storing the abnormal state by adding a simple circuit.
Can be set to the initial state to prevent runaway, and the fact that a voltage abnormality has occurred can be stored and notified to the operator.

[0024]

As is apparent from the above description, according to the present invention, when the processing of the CPU is not completed with respect to the removal of the main battery, a reset is applied, and a flag indicating the abnormal state is left to indicate the abnormal state. It has a remarkable industrial effect of being able to grasp.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 shows an embodiment of a CPU reset control circuit and an abnormality storage circuit.

FIG. 4 is a block diagram of a conventional portable terminal device.

[Explanation of symbols]

1 CPU 2 RAM / RO
M 3 bus 4 clock generation unit 5 oscillation control unit 6 CPU reset control circuit 7 power supply 8 voltage detection circuit 9 main battery 10 battery pull-out detection switch 11 sub-battery 12 abnormal memory circuit 13 stop switch 21-24 OR circuit 25, 26 flip-flop (FF) 27 Delay circuit

Claims (1)

[Claims] 1. A state holding function which detects the closing switch (13) being turned on, supplies holding power to the entire circuit to hold the state, and becomes a standby state when the CPU clock stops, In a device that maintains the state with the sub battery (11) even if the main battery (9) is removed, the battery withdrawal detection switch (10) that detects the preliminary operation of withdrawing the battery and sends a detection signal, and the power supply (7) A voltage detection circuit (8) that detects that the voltage has dropped below a predetermined voltage and sends a signal, a CPU reset control circuit (6) that supplies a reset signal to the CPU (1) by the signal, and the signal Has a failure storage circuit (12) that stores that the battery voltage has dropped below a predetermined voltage, and when there is a preliminary operation to remove the main battery (9) in the operating state, the battery removal detection switch ( 10) by the main battery (9)
Notify the CPU (1) of the detection of the preparatory movement when the
When U (1) does not finish the clock stop, the CPU reset control circuit (6) is detected by the detection signal of the voltage detection circuit (8).
Resets the CPU (1) to initialize the CPU (1), and stores the abnormal operation in the abnormal memory circuit (12) by the detection signal of the voltage detection circuit (8). A device having a characteristic state maintaining function.