JPH0581126A - Data processor and data processing system - Google Patents

Abstract

PURPOSE:To apply low-speed peripheral equipment concerning a memory or a memory control circuit while keeping a high-speed operation in a data processor. CONSTITUTION:The data processor 11 is provided with an input terminal BUSM0/1 inputting the setting signal of a basic memory access cycle in memory access and access cycle control circuits 122 and 123 which very the basic memory access cycle in accordance with the setting signal so as to set basic memory access time when the data processor 11 starts. Thus, the operation speed of the peripheral equipments such as the memory, etc., can correspond to speed from low speed to high speed without software while keeping the high-speed operation in the data processor adding arithmetic units 102 and 103. In result, the same data processor can correspond to a system from the system aiming at a high-speed data processing to the system aiming at cost performance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device such as a microprocessor, and more particularly to a data processing device capable of supporting both a low speed memory system and a high speed memory system while the data processing device remains operating at high speed. The present invention relates to a data processing system using a data processing device.

[0002]

2. Description of the Related Art Generally, various methods have been proposed in the past in order to adjust the operating speed of a data processing device such as a microprocessor and the operating speed of a memory system.
For example, the publication “Nikkei Electronics, 1989,
4.3 (no. 470) pp. 199-209 "(microprocessor 808
According to 60), the operations of both are adjusted by the following method. That is, when the microprocessor accesses the memory, the memory access time is extended as necessary to adjust the internal operation of the microprocessor and the memory access time. That is, a control circuit for memory access is provided, the address information output from the microprocessor is decoded by this control circuit, it is determined whether the memory corresponding to the address is ready for access, and the access preparation Input status signals to the microprocessor. For example, this status signal is set to "1" when the access is not ready and "0" when the access is ready. On the other hand, the microprocessor is provided with a READY # terminal, and the memory access preparation status signal is inputted to this terminal. Then, the microprocessor controls the extension of the memory access time according to the signal state of the READY # terminal for each memory access. In this way, even if the memory access time is extended, the microprocessor normally has a cache memory built-in, so even if the processor is operated at a relatively low speed with respect to the inside of the processor, the system performance does not deteriorate much. This is an effective method for reducing the system cost.

However, according to the above method, the memory access control circuit sets the preparation status signal to "0" or "1" by the time the basic memory access time (memory access time when not extended) ends. Since it is necessary to confirm it, the decoding of the above address must be completed by that time. On the other hand, the basic memory access time of the microprocessor is defined by the number of clocks that control internal operations. Therefore, in the case of the above method, if the operation speed of the microprocessor is increased, the basic memory access time is shortened accordingly. Therefore, the operation speed of the memory and the memory control circuit must be increased in accordance with the increase in the speed of the microprocessor. It will not happen.

However, the data processing system is used in various fields, and in terms of system cost,
In some cases, it may be desirable to apply a low-speed peripheral circuit such as a memory or a memory control circuit. Therefore, according to the above conventional technique, the speed of the microprocessor may be restricted by the operating speed of the peripheral circuits, which may prevent the speed of the general-purpose microprocessor from being increased, or the microprocessor should be prepared from low speed to high speed. There are problems such as having to do it.

As a method for solving such a problem, there has been proposed a method in which the operating speed of the microprocessor is varied by software when a system is constructed with a high-speed operating microprocessor and a low-speed operating memory ( Hitachi Review, 1988, 12 (vol.70), pp.1
7-24, "16-bit Microprocessor H16 and Its Applications"). This is because a register that variably specifies the memory access time is provided in the microprocessor, the number of memory cycles corresponding to the waiting time is specified by software in this register, and the microprocessor refers to the register to refer to the internal operation and memory access time. This is a method for adjusting. That is, when the number of waits of the memory cycle is designated in the register, when the microprocessor accesses a specific address space, the memory access time is extended by the designated amount.

[0006]

However, according to the conventional method of adjusting the memory access time by the latter register, the number of memory cycles is set in the register by software of the microprocessor. The information of the number of memory cycles is information about the memory of the system in which the microprocessor is mounted, that is, hardware information. Therefore, the hardware information is incorporated into the software, and the software of the system becomes unique to the memory, so that the software cannot be shared with other systems.

When developing a new microprocessor whose instructions are compatible with those of an existing microprocessor,
It is not possible to add a new register as in the prior art.

Therefore, a first object of the present invention is to provide a data processing device capable of coping with the speeding up of a microprocessor and varying the memory access time according to the operating speed of a peripheral device without depending on software. Especially.

On the other hand, in the processor having a built-in cache memory as in the above-mentioned conventional technique, when transferring data from the external memory to the cache memory, a plurality of consecutive bus cycles are occupied and a plurality of consecutive addresses of a plurality of words are occupied. Burst access transfer, which transfers data in a batch, is often used. This burst access transfer uses DRAM (Dinamic Random Access Memory) as the main memory.
When using a static column mode or a nibble mode which the DRAM has, data can be transferred at high speed. However, since the above-mentioned transfer modes have different timings from the case of access in units of one word, it is necessary to provide dedicated transfer control hardware outside the processor, which complicates the configuration.

Therefore, a second object of the present invention is to provide a data processing device capable of address control in accordance with the timing of burst access transfer without using dedicated hardware.

Further, a system using a data processing device may have to be provided with a system failure detecting means such as a parity check in order to maintain system reliability. However, TTL (Transistor Transistor Logi
The parity check means using individual parts such as c) causes a large-scale system and high cost, and thus has a problem that a highly reliable system cannot be easily realized.

Therefore, a third object of the present invention is to provide a data processing device capable of easily constructing a highly reliable system by providing a parity check means in the data processing device.

[0013]

In order to achieve the above first object, the present invention provides a data processing device with an input terminal for inputting a setting signal of a basic memory access cycle of a memory access control circuit, and the input terminal. An access cycle control circuit that variably sets the basic memory access cycle according to the setting signal fetched from the terminal is provided, and when the data processing device starts to start, select one from multiple types of basic memory access time. I decided to do it.

Further, in order to achieve the above second object, when the instruction or data relating to the memory access request of the present invention can be stored in the cache memory, the memory access control circuit continuously accesses a plurality of words. An address changing circuit is provided for switching to the burst access transfer mode and changing the content of a predetermined bit of the address output from the arithmetic unit according to the burst access transfer mode even when the circuit is in the middle of the memory access operation. Of.

In order to achieve the third object, the present invention provides a parity check circuit in the bus interface of the data processing device, and when the parity check circuit writes data from the arithmetic unit to the memory,
A predetermined parity is added to the write data and stored in a memory, and when the data with the parity is read from this memory, a parity of the data is newly generated and the generated parity and the read parity are Collate,
The parity check of the data bus is performed.

[0016]

According to the present invention, each of the above objects is achieved by the following actions. The access cycle control circuit of the data processing device fetches a setting signal of the basic memory access cycle from the outside, for example, when starting the activation, and variably controls the basic memory access cycle according to the contents of the setting signal. For example, if the setting signal is
When setting the length of the basic memory access cycle at High level or Low level, if it is set to High, the basic memory access time should be set to 2 cycles of the internal operation clock of the arithmetic unit, and if set to Low, set to 4 cycles. While maintaining the high-speed operation inside the data processing device including the arithmetic unit, the operation speed of the peripheral device such as the memory can be handled from low speed to high speed without depending on the software. As a result, it is possible to realize a data processing device capable of handling a system aiming at high-speed data processing and a system aiming at cost performance.

Further, according to the device provided with the address changing circuit, the signal indicating that the data to be accessed can be stored in the cache memory is received and is output from the arithmetic unit even during the memory access operation. Since the content of a predetermined bit of the address is changed according to the burst access transfer mode, the operation timing with the memory device can be synchronized and the address signal can be externally supplied when performing the burst access transfer. It is possible to reduce the scale of dedicated hardware for burst transfer control, such as eliminating the need for a latch circuit for storing data.

Further, according to the data processing device provided with the parity check means, it is not necessary to provide a special parity check means separately from the data processing device, and a highly reliable system can be easily constructed. ..

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to illustrated embodiments. 1 to 3 show a data processing device and a data processing system using the same according to an embodiment of the present invention. FIG. 1 is an overall configuration diagram of a data processing system of this embodiment, FIG. 2 is an overall configuration diagram of a data processing device itself of this embodiment, and FIG.
FIG. 3 is a configuration diagram of a main part of a bus interface of the data processing apparatus of this embodiment.

The data processing system shown in FIG. 1 shows a basic configuration necessary for performing basic data processing centering on the data processing device 11, and includes a memory control circuit 12 and a main memory 13. , Decoder 14, input / output device I / O 15, and SFU (Special Function Unit) 16
And a basic memory access cycle setting means 17 and a bus consisting of an address bus 21, a data bus 22 and a control bus 23 connecting these.
The illustrated data processing system is, for example, an input / output device I.
It can be applied as a data processing system such as a workstation or a laser printer by changing the function of / O.

The data processing device 11 sequentially reads the instructions stored in the main memory 13 while simultaneously reading the instructions from the main memory 13 and I.
/ O15 data is processed. The SFU 16 is a special arithmetic unit for complementing the processing of the data processing device 11 as needed. The I / O 15 is controlled by the control signal 26 output from the decoder 14. For example, if the system of FIG. 1 is applied to a workstation, peripheral devices such as a keyboard, a CRT, a hard disk, which are not shown, are connected using a plurality of I / Os 15.

Next, the data processing device 11 causes the main memory 13 to
The basic system operation when accessing is explained. First, the data processor 11 outputs the address for the main memory 13 to the address bus 21. At the same time, it outputs various control signals for the main memory 13 to the control bus 23. The memory control circuit 12 uses the information on the address bus 21 and the control bus 23 to generate an address signal 300 and a control signal 40 for the main memory 13.
0 is generated, which controls the reading and writing of instructions and data in the main memory 13. On the other hand, the main memory 13 outputs the instruction and data of the designated address to the data bus 22 in accordance with the instruction from the memory control circuit 12. Further, the memory control circuit 12 notifies the data processing device 11 via the control bus 23 that the main memory 13 has output the data to the data bus 22. Upon receiving this notification, the data processing device 11 reads the data on the data bus 22. This notification signal is sent to the data processing device 11
Must be determined within a fixed time determined by (hereinafter, the fixed time is referred to as a basic memory access cycle). Therefore, the memory control circuit 12 must decode the address information and control information output by the data processing device 11 within the basic memory access cycle. That is, the operation speed of the memory control circuit 12 and the main memory 13 is determined by the operation speed corresponding to the memory access cycle of the data processing device 11.
When a high-speed data processing device 11 is used,
As it is, the memory control circuit 12 and the main memory 13 having a low speed cannot be applied.

Therefore, in the data processing device 11 of the present embodiment, the above-mentioned basic memory access cycle is set in the memory control circuit 1.
2 and the main memory 13 can be variably set according to the low speed operation. That is, in order to select and set the basic memory access cycle from a plurality of preset values, the basic memory access cycle setting means 17 is provided and a terminal for fetching a signal input and set by the basic memory access cycle is provided.
It is provided in the data processing device 11. The basic memory access cycle setting means 17 specifies the basic memory access cycle by the number of cycles of the internal operation clock CLK of the data processing device 11. In FIG. 1, the basic memory access cycle setting means 17 causes the data processing device 11 to operate.
The basic memory access time is designated by inputting a setting signal formed by combining signals of "0" or "1" to the two input terminals BUSM0 and BUSM1 of. As a result, the memory access cycle of the data processing device 11 is set according to the operating speed of the memory system, so that the operating speed of the data processing device 11 itself is not restricted by the operating speeds of the memory control circuit 12 and the main memory 13. , It is possible to operate at the original speed. Therefore, in the case of a system aiming at high speed processing, the data processing device 11 and the main memory 1
It is realized by operating both 3 and 3 at high speed. On the other hand, even if the system of the main memory 13 is operated at low speed in order to reduce the cost, the high speed operation can be directly applied to the data processing device 11. Further, in the case where the data processing device is provided with the cache memory, the performance deterioration can be suppressed accordingly.

Here, a specific configuration of the data processing device 11 will be described with reference to FIGS. 2 and 3. As a preferable mode for realizing the data processing device 11, the data processing device 11 itself is an LSI (Large Scale Integrated Circuit). Therefore, the data processing device 11 will be described below as being configured by an LSI.

FIG. 2 shows the internal structure and terminals of the data processing device 11.

As shown in the figure, the data processing device 11 includes an arithmetic unit including a decoder 101, a floating point arithmetic unit 102 and an integer arithmetic unit 103, a cache memory 104, and an MMU for converting a memory address from a logical address to a physical address. (Memory Management Unit)
105, a PLL (Phase Locked Loop) 106 that generates a clock CLK that serves as a reference for internal operation, and a bus interface 110. The decoder 101 decodes the fetched instruction. The floating point arithmetic unit 102 includes registers and arithmetic units for floating point arithmetic. The integer arithmetic unit 103 is composed of registers and arithmetic units. The cache memory 104 is composed of an instruction cache memory, a data cache memory, and a control circuit therefor, and stores a part of the instructions and data in the main memory 13 to enable high-speed operation of arithmetic processing.
The PLL 106 doubles and converts the input clock from the CLKIN terminal and supplies the operation clock CLK to the entire data processing device 11.

Before describing the configuration of the bus interface 110, which is a characteristic part of the present invention, terminals for exchanging signals and data with the main part will be described. In addition, in each terminal code, those with% added are Low
Indicates that it is active.

(1) An input terminal for supplying power to the VCC data processing device 11.

(2) This is an input terminal for applying a reference of 0 V to the GND data processing device 11.

(3)% BREQ A bus master other than the data processing device 11 is an input terminal for requesting the data processing device 11 to release the bus.

(4)% BACK This is an output terminal for outputting a signal indicating that the data processing device 11 is releasing the bus.

(5)% SFU This is an output terminal for controlling the special arithmetic unit 16 which assists the data processing unit 11.

(6) BUSM0-1 This is two input terminals for inputting the setting data of the basic memory access cycle. The input data of this terminal is output only when the data processor 11 is reset by the% RST terminal.
It is taken into the inside of the bus interface 110.

(7)% CA This is an input terminal for instructing to store the data or instruction of the memory address output from the data processing device 11 in the cache memory 104, and this signal is input from the memory control circuit 12. When this terminal goes low, the data processor 11
Becomes a burst access mode in which 4 words are continuously accessed.

(8)% BUS8 An input terminal indicating that the memory corresponding to the address output by the data processing device 11 has an 8-bit width. When this terminal goes low, the data processing device 11 outputs 32 bits of data. The memory is accessed four times to access it.

(9)% BUS16 An input terminal indicating that the memory corresponding to the address output by the data processing device 11 has a 16-bit width. When this terminal goes low, the data processing device 11 outputs 32 bits of data. Two memory accesses are performed to access.

(10)% READY The signal input to this terminal is input from the memory control circuit 12. This signal is an input signal indicating that the data in the main memory 13 has been output to the data bus 22 when the data processing device 11 performs a read operation from the main memory 13, while a write operation is performed in the main memory 13. In this case, the data output from the data processing device 11 is used as the main memory 1
3 is an input signal indicating that 3 is ready for writing.

(11)% BS This is an output signal indicating that the data processing device 11 starts memory access. In burst access mode, it is not output from the second word access.

(12)% AC This is an output signal indicating that the memory address output from the data processing device 11 has changed. In burst access mode, it outputs 4 times.

(13) R /% W This is an output signal indicating whether the data processing device 11 is a read operation or a write operation in memory access. High is a read operation and Low is a write operation.

(14)% IF This is an output signal indicating that the memory data accessed by the data processing device 11 is an "instruction".

(16)% OC When the data processing device 11 performs a memory write operation,
It is an input terminal for controlling the data output timing to the data bus, and is input from the memory control circuit 12.

(17) D · 0 to 31 These are 32 data input / output terminals for the data processing device 11 to transfer data to the outside such as a memory.

(18) A · 0 to 31 are 32 output terminals for outputting addresses for the data processing device 11 to access the memory.

(19)% BE.0-3 These are four output terminals for designating specific byte data in one word accessed by the data processing device.

(20)% PED. This is an input terminal for instructing to perform a parity check on the data input / output from the terminals 0-31.

(21)% PERR D. An output signal indicating that a parity error has occurred at any of terminals 0 to 31.

(22) P.0-3 D.0-7 parity is P0, D.8-15 parity is P1, D.16-23 parity is P2, D.24-
It is four input / output terminals for inputting / outputting parity data by allocating 31 parities to P3, respectively.

(23)% RST This is an input terminal for resetting the data processing device 11.

(24) INT0 to 4 are five input terminals for generating an interrupt from the outside to the data processing device 11.

(25) CLKIN A terminal for inputting the operation clock of the data processing device 11,
It is a clock having a half frequency of the internal operation clock CLK.

(26) CLKOUT This is a terminal for outputting the internal operation clock CLK of the data processing device 11 and has a frequency twice that of the CLKIN terminal.

Here, the functional configuration of the bus interface 101 according to the characteristic part of the present invention will be described in detail.
The sequence control circuit 121 includes the cache memory 104.
When the signal for starting memory access is input from the control circuit, the operation is started, and the cycle (time) of memory access is controlled according to the operation clock and the generation of various signals necessary for access is controlled. The memory access cycle in the sequence control circuit 121 is based on the basic memory access cycle, and extension control similar to the conventional one is performed as necessary, but the feature of the present invention is that the basic memory access cycle itself can be changed. That is. The variable control of the basic memory access cycle is performed by the sequence control circuit 12 by the memory access cycle control circuit including the memory access cycle control unit 122 and the multiplexer MPX123.
This is done by changing the operation clock of 1. The memory access cycle control unit 122 of this embodiment uses the clock CLK
Is taken in, and two kinds of clocks, that is, the clock CLK as it is and the clock divided by 1/2 are generated and output. The MPX 123 selects these clocks according to the input to the BUSM · 0/1 terminal, and inputs the selected clocks to the sequence control circuit 121 as operation clocks. The output signal generation circuit 124 is the sequence control circuit 1.
Based on the instruction from 21, various output signals are generated.

Here, the above sequence control circuit 12
1, the memory access cycle control unit 122, the MPX 123,
Details of the output signal generation circuit 124 will be described with reference to FIG. The memory access cycle control unit 122 includes a flip-flop FF1 and MPXs two clocks, CLK and 1 / 2CLK, based on the input clock CLK.
Output to 123. MPX123 is an input terminal BUSM
A 0/1 basic memory access cycle setting signal is fetched and decoded, a clock corresponding to the content of the setting signal is selected and output to the sequence control circuit 121. Also,
The MPX123 has a 1-word unit access clock,
The burst access clock is output separately. When the memory access activation command is input to the sequence control circuit 121, the flip-flops of FF3 to FF5 activate the sequence control of 1-word access. When the High signal is output from the FF 5, the basic memory access cycle of 1-word access ends. In this case, if the% READY terminal is asserted, the clock from the MPX 123 is stopped by the gate 1,
The above sequence control is stopped until the% READY terminal is negated. If the% CA terminal is asserted while the FF4 is outputting a high signal, the burst access mode operation is started. The output of FF2 indicating the burst access mode is F by gate 4.
Control the output of F5. The output of this FF5 causes FF
The flip-flops 6 and FF7 control the basic memory access cycle of the second word of burst access. After that, FF9 and 10 control the basic memory access cycle of the third word of burst access by the output of FF7,
Further, the outputs of the FF 10 cause the FFs 11 and 12 to control the basic memory access cycle of the fourth word. Also,% RE
The basic memory access cycle is extended by stopping the clock by the gate 2 and stopping the sequence of FF6 to FF12 and FF16 only while ADY is asserted. The FF 15 asserts a data enable at each end timing of each basic memory access cycle to indicate that the data access is completed. The output signal generation circuit 124 includes G4, G5, FF13, and FF14.
Is used to control each terminal of% BS,% AC, R /% W and% IF.

Returning to FIG. 2, the data latch 125 temporarily stores the data input from the D · 0 to 31 terminals in the memory read operation and transfers it to the cache memory 104. In the memory write operation, the cache memory 1
The sequence control circuit 12 temporarily stores the data from 04.
Outputs to the D • 0 to 31 terminals according to the instructions from the 1 and% OC terminals. The lower 2 bits control circuit 126 is% CA
The lower 2 bits of the word address of the memory address output from the MMU 105 are sequentially set to 00, 01, 1 according to the input of the terminal, that is, according to the signal indicating that the data for writing can be stored in the cache memory.
Change it to 0 and 11. As a result, the data is transferred by burst access. Parity checker 127
Performs the parity check of the data on the data bus 22 by performing the parity check of the data of the D · 0 to 31 terminals. The interrupt control circuit 128 accepts an external interrupt by resetting the data processing device 11 or inputting INT.0 to 4 by inputting% RST. Also, Bus Arbiter 129
When an external bus master requests the data processing device 11 to use the bus, the bus release control is performed.

The operation of the bus interface 101 of the embodiment thus constructed will be described. Figure 4 shows BU
It shows the types of basic memory access cycles that can be selected by the SM · 0/1 terminal. BUSM · 0 and BU
When both SM1 and SM1 are "0", the access in 1 word unit is made to be 4 cycles of the internal operation clock CLK as 1 cycle of the basic memory access cycle (hereinafter referred to as basic memory cycle), and the burst access mode is set. Then 1
2nd word is 4 cycles of internal operation clock CLK
The second and subsequent words correspond to two cycles of the internal operation clock CLK. BUSM · 0 is “0” and BUSM · 1 is “1”
In this case, the second word and subsequent words in the burst access mode are four cycles of the internal operation clock CLK, which is different from the above case. BUSM · 0 is “1” and B
When USM.multidot.1 is "0", the basic memory cycle is two cycles of the internal operation clock CLK in both one word unit and burst access mode.

5 and 6 show a read operation in units of one word, and FIG. 5 shows "no wait".
6 shows the case of “with weight”. Also,
In the illustrated example, the basic memory cycle setting signal is BUSM.
0 = 1 and BUSM · 1 = 0. In the case of FIG. 5,% RE
The ADY terminal is asserted at the end of the basic memory cycle, and the memory cycle is not extended.
On the other hand, in FIG. 6, at the end of the basic memory cycle,% R
The EADY terminal is negated, and the basic memory cycle is extended by one cycle.

7 and 8 show the memory write operation. FIG. 7 shows the case of "no wait".
FIG. 8 shows the case of “with weight”. Also, the setting of the basic memory cycle is the same as in the case of FIG. In the write cycle, when the% BS terminal becomes High, the data processing device 11 outputs data from the D · 0 to 31 terminals.
By the way, when the read cycle is immediately before the write cycle, D · 0 to 3 connected to the data bus 22 are connected.
Output data from the main memory 13 may still exist in one terminal. Therefore, in the write cycle immediately after the read cycle, if the timing at which the data processing device 11 outputs the write data to D · 0 to 31 is too early, the output data from the main memory 13 in the read cycle immediately before the write cycle and its The output data of the data processing device 11 in the write cycle immediately after will collide on the data bus 22. In order to solve such a problem, the data processing device 11 has
A% OC terminal for externally adjusting the data output timing to D · 0 to 31 is provided. The data latch 125 takes in the signal of the% OC terminal and, as shown in FIG. 8, when the signal of the% OC terminal is High at the start t ₁ of the data write cycle, outputs the data to D.0 to 31. Prohibit for at least one basic memory cycle,
When the signal of the% OC terminal is Low, data output is permitted only during the High period of the% BS terminal in the write cycle.

FIG. 9 shows a memory read operation in the burst access mode. The basic memory cycle in this figure is the same condition as in FIG. The burst access mode is a memory access for storing the data or instruction of the main memory 13 accessed by the data processing device 11 in the cache memory 104 incorporated in the data processing device 11. In the address space accessed by the data processing device 11, in addition to the main memory 13, I / O
There are fifteen and so on. Therefore, there are two types of data that the data processing device 11 accesses, one that can be stored in the cache memory 104 and one that cannot. In the present embodiment, as a method for judging these two, as shown in FIG. 11, if the memory control circuit 12 decodes the output address of the data processing device 11 and the data to be read can be cached, the memory control is performed. Circuit 12 is% CA
A method is used in which the terminal is asserted to notify the data processing device 11 that caching is possible. And
When the% CA terminal is asserted, the data processing device 11 operates so as to access 4-word data continuously. When the data processing device 11 stores data or an instruction in the cache memory 104, the lower 2 bits of the word address are the addresses of the 4-word data, 00, 0.
The order must be 1, 10, 11. However, when the data processing device 11 outputs the first address, it is not clear whether or not the data can be cached, and thus the lower 2 bits of the word address first output are not necessarily 00. Therefore, the lower 2-bit control circuit 126 of the data processing device 11 is configured as shown in FIG.
When% CA is asserted, the lower 2 bits of the word address are forcibly changed to 00 when% CA is asserted as shown in FIG. As a result, the memory control circuit 12 can directly use the address of the first word output from the data processing device 11 without performing mask processing, so that the number of logic gates of the memory control circuit 12 can be reduced. 11
Shows the configuration of the memory control circuit 12 for supporting the burst access mode. Main memory 1
3 has a DRAM (Din
amic Random Access Memory) is used. The address decoder 201 decodes the address output from the data processing device 11, and if the address is a cacheable address as a result, activates the timing generation circuit 202. The timing generation circuit 202 asserts the% CA terminal to indicate that the data processing device 11 can be cached, and also generates a signal of the% READY terminal and a control signal to the main memory 13. The multiplexer 203 switches the address input to the main memory 13 based on the multiplex signal given from the timing generation circuit 202.

On the other hand, the data processing device 11 has a function of checking the parity of the data bus 22 in order to improve the reliability of the data processing system. Figure 12
Data processing device 11 for performing the parity check
2 shows the internal structure of the parity checker 127 of FIG. That is, the data of the data bus 22 is divided into four groups in units of 8 bits, the parity generators 131 to 134 are provided for the respective groups, and the parity is generated by these parity generators. Then, at the time of writing data, the parity generated by each of the parity generators 131 to 134 is output from the terminals P · 0 to 3 to output the main memory 1
Store in 3. After that, when reading the data, the parity is read by the P.0 to 3 terminals, and the parity check is performed. If four parity generators 131-
If even one of the 134 has an error, the parity control circuit 135 asserts the% PERR terminal.

As described above, according to the above embodiment, the basic memory cycle of the memory access control circuit of the data processing device 11 is set to the basic memory access cycle setting means 17
And the basic memory access cycle control unit 122 and MPX1
23 and the basic memory access cycle control circuit, that is, the hardware. Therefore, the data processing device 11 can operate the memory control circuit 12 and the main memory 13 at a low speed while maintaining the high speed operation without using software. As a result, a system having excellent cost performance or processing performance can be configured according to the requirements of the application system. Further, since the change of the basic memory cycle does not depend on the software, the compatibility of the software with other systems can be maintained. Further, since the data processing device can have the same operation speed regardless of the operation speed of the peripheral device, the versatility of the data processing device can be ensured.

Further, since the data processor 11 can control the address output in the burst access mode by the% CA terminal, it is possible to reduce the number of external circuits.

Further, the data processing device 11 is D.0 to 31.
Since the parity check of the terminal data can be performed, the system reliability can be improved.

[0064]

According to the present invention, since the basic memory cycle of the data processing device can be set from the outside, the data processing device maintains a high speed operation, while the external memory and its memory control circuit are operated from high speed to low speed. Can respond. As a result, the data processing device can be applied to a wide range of systems from a system that pursues high-speed performance to a system that pursues cost performance. Also, since the setting of the basic memory cycle does not depend on software, software compatibility can be achieved between different systems.

Further, according to the data processor provided with the means for checking the parity of the data bus, a highly reliable system can be realized at a low cost.

[Brief description of drawings]

FIG. 1 is an overall configuration of a data processing system using a data processing device according to an embodiment of the present invention.

FIG. 2 is an internal block diagram of the data processing device of FIG. 1 embodiment.

FIG. 3 is a configuration diagram of a main part of a bus interface.

FIG. 4 is a diagram illustrating an example of setting a basic memory access cycle.

FIG. 5 is a time chart showing an example of the timing of the memory read operation in the case of no wait according to the basic memory cycle of the data processing device.

FIG. 6 is a time chart showing an example of the timing of a memory read operation when there is a wait according to the basic memory cycle of the data processing device.

FIG. 7 is a time chart showing an example of a timing of a memory write operation according to a basic memory cycle of the data processing device.

FIG. 8 is a time chart showing an example of the timing of the memory read operation according to the basic memory cycle of the data processing device, showing an example in which the read cycle is extended.

FIG. 9 is a timing chart of the operation in the burst access mode, in which the first word shows an example of one cycle.

FIG. 10 is a timing chart of the operation in the burst access mode, showing an example in which the first word has two cycles or more.

FIG. 11 is a configuration diagram of a system centering on a memory control circuit supporting a burst access mode.

FIG. 12 is a configuration diagram of a parity checker of an embodiment of a data processing device of the present invention.

[Explanation of symbols]

 11 data processing device, 12 memory control circuit, 13 main memory, 21 address bus, 22 data bus, 23 control bus, 101 decoder 102 floating point arithmetic unit, 103 integer arithmetic unit, 104 cache memory, 105 MMU, 110 bus interface, 121 sequence control circuit, 122 basic memory access cycle control unit, 123 multiplexer, 124 output signal generation circuit, 125 data latch, 126 lower 2 bit control circuit, 127 parity checker, 128 interrupt control circuit, 201 address decoder 202 timing control circuit, 131-134 parity generator, 135 parity control circuit.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masahisa Narita 3-2-1, Sachimachi, Hitachi, Ibaraki Prefecture Hitachi Engineering Co., Ltd.

Claims (8)

[Claims] 1. An arithmetic unit for sequentially executing the contents of an instruction given according to a basic operation cycle, and a memory access control for controlling access to a memory according to the basic memory access cycle when a memory access request is input from the arithmetic unit. In a data processing device comprising a circuit, an input terminal for inputting a setting signal of a basic memory access cycle of the memory access control circuit, and the setting signal is fetched from the input terminal, and the setting signal is fetched according to the fetched setting signal. A data processing device, comprising: an access cycle control circuit for variably setting a basic memory access cycle. 2. The data processing device according to claim 1, wherein the access cycle control circuit fetches the setting signal when the data processing device is initialized. 3. An arithmetic unit for sequentially executing the contents of instructions given according to a basic operation cycle, a cache memory connected to the arithmetic unit, and a basic memory access cycle when a memory access request is input from the arithmetic unit. A memory access control circuit for controlling access to a memory according to the above, when the instruction or data relating to the memory access request can be stored in the cache memory, Is switched to a burst access transfer mode for continuous access, and the content of a predetermined bit of the address output from the arithmetic unit is changed according to the burst access transfer mode even when the circuit is in the middle of a memory access operation. Address change circuit Data processing apparatus, characterized in that digit. 4. An arithmetic unit for sequentially executing the contents of an instruction given in accordance with a basic operation cycle, and a bus interface for controlling data transfer between a memory and a memory based on a memory access request from the arithmetic unit. A parity check circuit is provided in the bus interface, and the parity check circuit adds predetermined parity to the write data when writing data from the arithmetic unit to the memory. When the data with the parity is read from the memory, the parity of the data is newly generated, the generated parity is collated with the read parity, and the parity of the data bus is stored. A data processing device characterized by performing a check. 5. The data processing device according to claim 4, further comprising a parity selection command input terminal for inputting a command to operate or stop the function of the parity check circuit. 6. An arithmetic unit for sequentially executing the contents of instructions given according to a basic operation cycle, and a memory access control for controlling access to a memory according to the basic memory access cycle when a memory access request is input from the arithmetic unit. A data processing device comprising: a circuit; and an input terminal to which a signal indicating that data is present in a data bus connecting the arithmetic unit and the memory is input, wherein the memory access control circuit includes the arithmetic unit. From the input terminal at the start of the one basic memory access cycle when writing data to the memory, the write operation is performed if the signal indicates that other data exists on the data bus. The output of data related to at least one cycle of the basic memory access cycle The data processing apparatus characterized by comprising comprises a that function. 7. A data processing device having an arithmetic processing unit and a bus interface, a bus connected to the data processing device via the bus interface, a memory connected to the bus, and the memory. A memory control circuit for controlling the memory device; and a memory access cycle setting means for setting a basic memory access cycle for the data processing apparatus to access the memory, wherein the arithmetic unit is provided with an instruction given in accordance with the basic operation cycle. And a memory access control circuit that controls access to a memory according to a basic memory access cycle when a memory access request is input from the arithmetic unit, and the memory access cycle. An input terminal for inputting a setting signal from the setting means, Captures the setting signal of the basic memory access cycle from the input terminal, in response to the setting signal taken the said memory access control circuit base memory access cycle comprising an access period control circuit for variably setting a data processing system. 8. A data processing device having an arithmetic processing unit, a cache memory, and a bus interface, a bus connected to the data processing device via the bus interface, a memory connected to the bus, and A memory device including a memory control circuit; and a memory access cycle setting means for setting a basic memory access cycle for the data processing apparatus to access the memory, wherein the arithmetic unit has contents of an instruction given in accordance with the basic operation cycle. The memory control circuit decodes an address input via the interface, and when a command or data related to a memory access request can be stored in the cache memory, a signal to that effect. Output to the bus interface. The interface includes a memory access control circuit for controlling access to the memory according to a basic memory access cycle when a memory access request is input from the arithmetic unit, and an input terminal for inputting a setting signal from the memory access cycle setting means. And an access cycle control circuit for fetching a setting signal of the basic memory access cycle from the input terminal and variably setting the basic memory access cycle of the memory access control circuit according to the fetched setting signal, and output from the memory control circuit Burst access for inputting a signal indicating that the data can be stored in the cache memory and a signal indicating that the data can be stored in the cache memory from the input terminal, and sequentially accessing the memory access control circuit for a plurality of words While switching to transfer mode, Is provided with an address changing circuit for changing the content of a predetermined bit of the address output from the arithmetic unit even in the middle of the memory access operation in accordance with the burst access transfer mode, and a parity check circuit. The parity check circuit, when writing data from the arithmetic unit to the memory, adds a predetermined parity to the write data and stores the data in the memory, and when the data with the parity is read from the memory, A data processing system configured to newly generate a parity of the data, collate the generated parity with the read parity, and perform a parity check of the data bus.