JPH0581086B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a frequency logic system, and particularly to a frequency logic system that has a plurality of logical functions and is easily fail-safe. [Conventional technology] For example, ATC (automatic train control device) for railway vehicles
Since these systems aim to prevent train collisions, protect human lives, and prevent serious damage, a high degree of fail-safe performance is required. For this reason, the circuits that make logical decisions have a multi-system configuration, and the outputs of each system are collected and the final output is determined by a fail-safe matching circuit or majority circuit. Here, in addition to making each logic circuit fail-safe, we also configured a multiplex system for these circuits to ensure complete safety. However, the majority circuit is a single system, and its fail-safety is largely related to the fail-safety of the entire device. For this reason, efforts are being made to construct fail-safe majority voting circuits, but at present only electromagnetic relays are used, which lags behind in terms of miniaturization, weight reduction, and power saving of devices. The reason why electromagnetic relays provide fail-safe properties is as follows. Failures in electromagnetic relays can be divided into contact continuity failures and non-continuity failures, but in general, the probability of occurrence of a continuity failure is less than 1/1000 of that of a non-continuity failure. This is because the cause of a continuity failure is only the welding of the contacts, whereas the cause of a non-continuity failure is poor contact due to dirt or oxidation of the contacts, disconnection or internal short circuit of the drive coil, failure of the drive power supply, breakage of the movable piece, etc. It is for a great deal. Furthermore, in order to prevent contact welding, if the contact current is suppressed below the welding limit, the only failure mode can be considered to be a non-conducting failure. Therefore, if the conduction of the contacts is made to be the control output on the dangerous side and the non-conduction side is made to be the control output on the safe side, the electromagnetic relay can be used as a fail-safe logic element. On the other hand, in the case of a semiconductor element, the probability of occurrence of a failure in a conductive state and a failure in a non-conductive state are approximately equal. In the case of semiconductors, diffusion of impurities, deterioration due to heat,
This is because failures caused by the same types of causes, such as breakage or fusion of lead wires, short circuits or fusing due to loaded current or overvoltage, can result in either conduction or non-conduction. For this reason, in semiconductors, it is impossible to specify the logic values on the fail-safe side and the fail-out side based on a certain physical state as in the case of electromagnetic relays, and it is impossible to specify the logic values on the fail-safe side and fail-out side using a certain physical state, so it is impossible to specify the logic values on the fail-safe side and fail-out side. As a method for making all arbitrary circuits configured together fail-safe, a method has been proposed in which a logical value is assigned to an alternating signal of a specific frequency value, and logical operations are performed in a frequency collection area. This method is called a "frequency logic method," and for example, in the case of binary logic, the logical values "1" and "0"
Assign an alternating signal with a specific frequency to each of It outputs an alternating signal having a frequency corresponding to the output truth value. In other words, by setting the frequency of the alternating signal to a logical value, it is possible to extremely reduce the probability that a dangerous output will be produced in the event of a self-failure, and also because a normal logic element makes a judgment regarding an abnormal input. ,
It is possible to reliably generate output on the safe side. In addition, in a logic circuit that requires two or more inputs, before the frequency band determination described above, a predetermined operation, such as addition, is performed between the frequency values of two or more input alternating signals, and the result is We are performing band judgment for As a result, in addition to the commonly used logic elements such as AND, OR, NAND, NOR, and EOR, the frequency logic system can also construct logical functions by combining these elements, such as majority logic, all at once. . Next, regarding the principle of the frequency logic method mentioned above,
This will be explained in detail with reference to the drawings. FIG. 7 shows the distinction between logic "1" and "0" by comparing an example of a general logic signal and an example of a logic signal in a frequency logic system. FIG. 7A shows the state of electrical signals representing logic "1" and "0" in general binary logic. For example, a voltage of 5V represents logic "1",
0V represents logic "0". In contrast,
Figure 7B shows an example of the logic signal of the frequency logic system, where a 300Hz alternating signal is a logic "1",
The Hz alternating signal represents a logic "0". The frequency logic system thus expresses different truth values depending on the difference in frequency. Next, examples of frequency band division will be explained with reference to FIGS. 8 to 10. Figure 8 shows an example of the simplest frequency band classification, where a frequency band higher than any frequency ₁ is defined as logic "1" and a frequency band lower than frequency ₁ is defined as logic "0". . Figure 9 uses three-value logic, and in addition to the logic "1" and "0" as in Figure 8, a frequency band indicating an abnormal state is set, and a frequency band lower than frequency ₂ is set as an abnormal state. It is defined as a state. FIG. 10 limits the normal logic "1" and logic "0" to different specific frequency bands,
An example is shown in which all other frequency bands are defined as abnormal states. That is, this example has 600
The 575-625Hz band centered on Hz and the 325-375Hz band centered on 350Hz are logic "1," the 75-125Hz band centered on 100Hz is logic "0," and all other frequency bands are in an abnormal state. Defined. Next, a frequency logic element using a frequency logic method will be explained. FIG. 11 is a basic block diagram showing an example of a frequency logic element. In FIG. 11, 4 and 5 are input terminals, 6 is an output terminal, 7 is an arithmetic unit, 8 is a frequency band determination unit, and 10 is an alternating signal The generator 12 is a frequency logic element. The frequency logic element 12 shown in FIG. 11 has a calculation section 7, a frequency band determination section 8, and an alternating signal generation section 10 connected in series, and the calculation section 7 has two input terminals 4, 5.
However, the output terminal 6 is provided in the alternating signal generating section 10, and two-input type OR, AND, EOR, NAND elements, etc. can be configured. The calculation unit 7 performs a predetermined calculation between the frequency values of the two alternating signals applied to the input terminals 4 and 5. This operation may be addition, subtraction, multiplication, or division. The frequency band determining unit 8 determines the frequency band of the frequency signal as a calculation result from the calculating unit 7, and determines whether the frequency band corresponds to a logic “1”, “0”, or an abnormal state. Alternate signal generator 10
give to Based on this determination result, the alternating signal generating section 10 outputs to the output terminal 6 an alternating signal having a frequency indicating a logic "1", "0" or an abnormal state. The arithmetic circuit 7 adds the frequency values of the input alternating signals from the input terminals 4 and 5, and sets the frequency of the alternating signal corresponding to logic "1" to _P , the frequency of the alternating signal corresponding to logic "0" to _N , Assuming that the frequency of the alternating signal corresponding to the abnormal state _{is E} , and the frequency of the alternating signal output from the calculation section 7 is a, the frequency logic element 12 performs the operations shown in Table 1.

[Problem that the invention seeks to solve]

However, although the prior art has a complicated circuit configuration as shown in FIG.
As shown in the symbol in Figure 6, only one type of logic function can be performed, and even when integrated into an LSI, one IC can only perform one type of logic function, making it difficult to perform two types of logic functions in general. Compared to value logic circuit ICs,
There is a problem that the area occupied by one logic element increases. Therefore, there is a problem in that a device using a frequency logic element according to the prior art requires a large mounting space. An object of the present invention is to solve the problems of the prior art, reduce the effective area occupied by one logic element, and improve the packaging density of logic elements in equipment using frequency logic elements. The object of the present invention is to provide a frequency logic system having logic functions. [Means for Solving the Problems] According to the present invention, the object is to simultaneously execute a plurality of logical functions using the same operation result for an input alternating signal, and to generate an output alternating signal for each logical function. This is achieved by outputting multiple pieces at the same time. [Operation] By simultaneously executing multiple logic functions using the same calculation result for an input AC signal, it becomes possible to use many of the circuit sections that constitute a logic element in common, and the number of circuits per logic element is reduced. The effective area occupied can be reduced. in general,
In actual circuit design, wiring patterns that apply the same logic input to multiple different logic elements are very common, and wiring patterns that apply the same logic input to multiple different logic elements are common, and wiring patterns that apply the same logic input to multiple different logic elements are common, and wiring patterns that apply the same logic input to multiple different logic elements are common.
In many cases, both (AND and NAND) outputs are required. In such a case, if the frequency logic method according to the present invention is used, the mounting space of the equipment can be reduced. [Embodiment] Hereinafter, an embodiment of a frequency logic system having a plurality of logic functions according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a memory configuration diagram, and FIG. 3 is an operation time chart. In FIG. 1, 621 is a latch circuit, 581 is a data string, 641 is a logic output circuit,
510 is a timing signal, other symbols are the first
This is the same as the case of the prior art shown in FIG. The difference between the embodiment of the present invention and the prior art is as follows:
One embodiment of the present invention has a latch circuit 612 and a logic output circuit 641 in addition to the conventional technology shown in FIG. ₁₀₉ , and time slots t ₁₂ and t ₅₁ are added. In this embodiment, the contents of the data string 58 are the fourteenth
As in the case of the figure, it is for the OR function, and data column 5
81 is for the AND function. The judgment level frequencies specified by the data string 56 are: ₁₀ = 620Hz, ₁₀₉ = 400
Hz, ₉ = 330Hz, ₈ = 120Hz, ₇ = 90Hz. The embodiment shown in FIG. 1 has a new judgment level frequency.
By adding ₁₀₉ , the logical input becomes (1, 0)
In other words, in the case of alternating input signals ( _P , _N ),
The output truth values for AND and OR are different. For simplicity, the time chart shown in FIG. 3 is limited to the operation in this case, that is,
The operation status is limited to the case where OR output = "1" and AND output = "0". The operation of the embodiment will be described below with reference to this time chart. When the input alternating signal is ( _P , _N ), the output alternating signal of the calculation unit 7 is _P + _N = 350Hz, which is between the judgment level frequency ₉ and ₁₀₉ , so the judgment signal 3
6 falls between time slots _t12 and _t2 , the latch circuit 62 receives data _P from the data string 58, and the latch circuit 621 receives data _N from the data string 581.
latch and hold. Latch 62 data _P
is 300Hz at time slot ₅ , and latch 6
The data _N of 21 is converted into a 50Hz alternating signal at time slot _t51 , and is sent to logic output circuits 64 and 641.
is output from. The logic element 13 of FIG. 1 operates in the same manner for other combinations of input alternating signals from the input terminals 4 and 5, with its output terminal 75 representing AND logic and its output terminal 76 representing OR logic. That is, the logic element 13 in FIG. 1 is equivalent to a composite logic element including a plurality of logic elements as shown in FIG. One embodiment of the present invention described above allows output data strings for different logics to flow from memory in parallel,
By latching these all at once using a determination signal and then outputting the alternating signals in a time-division manner, it is possible to output separate alternating signals corresponding to a plurality of logical functions. For this reason, whereas the conventional technology had a large circuit scale as one logic element, the embodiment of the present invention makes it possible to execute multiple logics with a slight increase in the amount of hardware. The amount of hardware per one logic element can be reduced. Furthermore, since the number of time slots is increased only in the output slot, there is little elongation of the computation period t, that is, a decrease in the computation speed. One embodiment of the present invention shown in FIG. 1 realizes the equivalent of two logic elements connected in parallel using two latches, but also adds a latch circuit, a logic output circuit, a memory, and an output time slot. if,
It is possible to increase the number of logic functions equivalently connected in parallel to a common input terminal, and it is possible to reduce the effective circuit scale of logic elements based on the frequency logic method. FIG. 4 is a block diagram of another embodiment of the present invention in which flexibility in selecting logical functions is added to the embodiment of FIG. 1. In FIG. 4, 77 is a group of function data terminals, 78 is a function setting terminal, and other symbols are the same as in FIG. In FIG. 4, data strings corresponding to data strings 58 and 581 in FIG. 1 are constantly output from the functional data terminal group 77, and their contents are as follows.
For example, it consists of a combination of data _P , _N , and _E for realizing the various logical functions shown in Table 1. Of course, other combinations or different frequency data may also be used. By selecting a necessary data string from among the data strings output to the function data terminal group 77 and connecting it to the function setting terminal 78, the embodiment shown in FIG. It can function as a composite logic element having a combination of logic functions, and is equivalent to a composite logic element in which logic elements with freely combinable logics are connected in parallel, as shown in FIG. In this embodiment, since the same circuit configuration can be configured into a composite logic element having any function, it is possible to reduce costs through mass production. [Effects of the Invention] As explained above, according to the present invention, by providing various logics that can be determined using the calculation results between output signals on the same circuit, one logic element employing frequency logic can be It is possible to provide a frequency logic system having a plurality of logic functions, in which the circuit scale per element can be reduced, and the decrease in calculation speed is smaller than the rate of increase in the number of logic gates.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a memory configuration diagram, Fig. 3 is an operation time chart, Fig. 4 is a block diagram showing another embodiment of the present invention, and Figs. 5 and 6 are logical function symbols of the embodiment of the present invention. The block diagram shown in Figure 7A,
B. Figures 8, 9, and 10 are diagrams explaining the principle of frequency logic, Figures 11 and 12 are basic block diagrams of frequency logic elements, and Figure 13 is a block diagram showing an example of conventional technology. 14 is a memory configuration diagram thereof, FIG. 15 is an operation time chart, and FIGS. 16A and 16B are block diagrams showing an example of the prior art using logical function symbols. 4, 5... Input terminal, 6, 17, 75, 76...
...Output terminal, 7...Calculation section, 8...Frequency band determination section, 10, 30...Alternating signal generation section, 12, 1
3... Frequency logic element, 18, 20... Sampling circuit, 22... Exclusive OR, 24... Clock signal generation circuit, 34... Frequency comparison circuit, 40
... Address circuit, 44 ... Timing circuit, 5
4...Memory, 60...Data switching circuit, 62,
621... Latch circuit, 64, 641... Logic output circuit, 66... Error detection circuit, 68... Failure detection output circuit.

Claims (1)

[Scope of Claims] 1. At least two alternating signals having different frequencies corresponding to at least two truth values are input, an operation is performed between the frequency values of these input alternating signals, and an alternating signal of the operation results is obtained. It is determined which frequency band the signal is in among the alternating signals of a plurality of reference frequency bands associated with a plurality of sets of output truth values, and the frequency band for the two truth values is determined according to the determined frequency band. A frequency logic system having a plurality of logic functions, which outputs alternating signals of frequencies corresponding to output truth values of a plurality of logics. 2. The plurality of frequencies according to claim 1, wherein the frequency corresponding to each input truth value is the same as the frequency corresponding to each output truth value in at least one set of output truth values. Frequency logic method with logic function. 3. Claim 1, wherein the calculation between the frequency values of the input alternating output is addition.
A frequency logic system having a plurality of logic functions according to item 1 or 2. 4. The frequency corresponding to each of the input truth values is selected to be a frequency that does not overlap with any of the frequencies resulting from the calculation. Frequency logic scheme with multiple logic functions as described. 5. Claims 1, 2, and 3, characterized in that the calculation of the input truth value is performed directly as an alternating signal, and the result of the calculation is compared with the plurality of reference frequency bands. A frequency logic system having a plurality of logic functions according to item 1 or 4. 6. The comparison between the result of the calculation and the plurality of reference frequency bands is performed by sharing a common frequency comparison circuit in a time-sharing manner and comparing the result of the calculation with each of the plurality of reference frequency bands. A frequency logic system having a plurality of logic functions as claimed in claim 5.