JPH0580719A - Display circuit for liquid crystal display - Google Patents

Abstract

PURPOSE:To greatly improve the mounting and power consumption by greatly decreasing the number of memories on the whole by the reduction of a memory chip and reducing the scale of the whole circuit. CONSTITUTION:Frame memories 10a and 10b, and 10c and 10d of double buffer constitution are provided independently for respective systems for odd-numbered and even-numbered column display data, look-up table memories 20a and 20b are arranged in front of them across data buffers writing for the respective odd-numbered and even-numbered column display data, and one selector 40 is arranged behind the frame memories across data buffers for reading.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit used in, for example, a liquid crystal display device used as a display device mounted on an aircraft. Memory part and lookup
The present invention relates to a display circuit of a liquid crystal display configured to reduce the power consumption by reducing the circuit scale of the display circuit including a table memory.

[0002]

2. Description of the Related Art FIG. 4 is a diagram of a display circuit of a conventional liquid crystal display. FIG. 5 is a diagram for explaining FIG. FIG. 6 is a diagram for explaining FIG.

In FIG. 4, reference numerals 1a to 1d indicate a double buffer memory structure having a function of storing display data at one end (a structure in which one is only for writing while the other is only for reading). Frame memory (hereinafter abbreviated as "FM"). At this time, for each of them, for example, as shown in FIG. 6, a RAM of five sides (one side is “32K × 8” bits)
Is used for the FM1a and 1b, and the odd column display data K is used.
d, the even column display data Gd is introduced to the FMs 1c and 1d, respectively. Reference numerals 2a to 2e are lookup table memories (hereinafter abbreviated as "LT") composed of a ROM or a RAM. Each LT has two sides, and input data is stored according to the contents of the table. It has the function of converting and outputting.

The functions of the FM and LT are usually C
Unlike the function of the circuit used for driving the RT (see, for example, Japanese Patent Publication No. 59-11916 and Japanese Patent Publication No. 62-13674), the FM is decomposed into R, G, and B color data. Data is stored, and the LT has the characteristics of a liquid crystal display (hereinafter abbreviated as "LCD") which is composed of an array as shown in FIG. 5 (the horizontal arrow in the drawing indicates the input direction of the data). It has a correcting function.

3a1, 3b1, 3c1 and 3d1 are data buses provided on a data bus connecting FM / LT (the number "8" displayed on the data bus in FIG. Represents a bit.
The same applies to the following drawings) Data buffer for switching (hereinafter abbreviated as "DB"), 3a2 and 3b2 are data on the input side of the odd-numbered display data of FM1a and 1b. DBs 3c2 and 3d2 provided on the bus are DBs provided on the data bus on the input side of the even column display data of FM1c and 1d. These DBs are controlled by a buffer control circuit (not shown). And indirectly controls the read / write of the data of each FM.

Reference numeral 4 is a selector for outputting the data converted by each LT to a digital / analog conversion circuit (hereinafter abbreviated as "D / A") 5. The D / A 5 is the data from the selector. Is converted into an analog signal and output as an analog display (30 lines) to a driver that drives an LCD not shown.

According to such a circuit configuration, the buffer control circuit turns on DB3a2 (or 3b2) and DB3c2 (or 3d2) and the odd column display data Kd is FM.
In 1a (or 1b), the even column display data Gd is FM1c (or
1d) are guided respectively.

Here, for example, as shown in the data input order based on the LCD array of FIG. 5, the horizontal direction is the data input direction and the vertical direction is an even numbered line (denoted by "O" and each suffix is Numbers indicate their respective order) and odd rows (indicated by "E" and the numbers of each suffix indicate their respective order), two rows of O1 and E1 indicated by α and two columns of four pixels Day
Input simultaneously. In this case, the data stored in the FM is 4 bits per pixel because it has not been converted by the LT.

Assuming that there are 160 columns for one row of the LCD, the FM storage method is as shown in FIG. 6 (in this case, the first column of the odd number "O" represents 5 FM) on each side. 1
Regarding the planes, O1-1, 1 ', O1-2, 2', ...
O-33, 33 ', ... For the two surfaces (the same applies to the following three surfaces) will be divided into five and stored in the row direction.

On the other hand, at this time, for example, when displaying an odd number of columns, the buffer control circuit causes the DB3b1
Is turned on and 5 bytes of FM1b (5 memory data
(In the case of an even-numbered column display, DB3d1 is ON-controlled and the storage data of FM1d) is simultaneously read out to LT2a-2e.

As a result, the LT outputs the corresponding display data of the data stored in advance to the selector based on the input data, whereby the selector → D / A → driver and data. Information is transmitted and LCD display is performed.

[0012]

The above-mentioned conventional technique has the following problems. RAM for FM
There are a total of 20 planes, the ROM for LT has a total of 10 planes, and a data buffer for switching the data bus and a circuit for controlling the read / write to the memory are arranged around them. Therefore, the overall circuit configuration becomes very large. Therefore, when it is used in an instrument that needs to be miniaturized, such as the aviation instrument described above, this is a major drawback in terms of mounting and power consumption.

The present invention has been made in view of the above problems of the prior art. The object of the present invention is to reduce the size of the entire circuit and significantly improve the mounting and power consumption. The present invention provides a display circuit for such a liquid crystal display.

[0014]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a frame structure comprising a double buffer memory structure in which one performs a data write operation and the other performs a read operation only. Memory is displayed on the odd-numbered column display data side and even-numbered column display data side.
Liquid crystal using a look-up table memory that is independently arranged on the data side, inputs read data stored in the frame memory, converts the read data according to the contents of the table, and outputs the converted data. In a display circuit of a liquid crystal display for causing a display to operate, a frame memory (10a / 10a) having a double buffer memory configuration in which the odd-numbered display data and the even-numbered display data are independently arranged for each system. Ten
b and 10c / 10d), a lookup buffer for each series of the odd-numbered column display data and the even-numbered column display data is provided through a write data buffer (30a2 to 30d2) in the preceding stage. The table memories (20a and 20b) are arranged, and one selector (40) is provided at each subsequent stage of the frame memory via the data buffer (30a1 to 30d1) for reading. In the double buffer memory configuration, two pieces are arranged in the odd column display data series, and two pieces are arranged in the even column display data series. Memory (A, B), each of the above data
The buffer is controlled by a buffer control circuit to control the frame.
Read / write of each data of the frame memory is performed, and the two memories (A, A, A) of the frame memory at the time of storing data of the frame memory are read by the selector.
It is characterized in that one of the stored data read out simultaneously from B) is selected and outputted.

[0015]

The LT is arranged for each series of the odd-numbered column display data and the even-numbered column display data through the write DB in each front stage of the FM, and the read DB is provided in each rear stage of the FM. As a circuit configuration in which one selector is arranged via the selector, the read data from the FM is output to each D / A via the selector for LCD display. That is, instead of reading 5 bytes at the same time from the FM, a plurality of FMs can be read at the same time by reading 5 bytes continuously at high speed.
The number of memory chips (IC) is reduced by eliminating the need to access the 5 chips. Further, by providing the LT, which has been provided in the latter stage of the FM until now, in the former stage of the FM, the number of memories and chips can be further reduced, and the number of memories can be significantly reduced as a whole, so that the entire circuit can be downsized, and mounting and power consumption can be reduced. Greatly improve.

[0016]

EXAMPLES Examples will be described with reference to the drawings.
In the following drawings, the same parts as those in FIGS. 4 to 6 are designated by the same reference numerals and the description thereof will be omitted. FIG. 1 is a diagram showing a specific embodiment of the display circuit of the liquid crystal display of the present invention. FIG. 2 is a diagram for explaining FIG. 1. Figure 3
Is a time chart (schematic operation timing chart of FIG. 1) used for the description of FIG.

In FIG. 1, 10a / 10b and 10c / 10
d is an FM having a double buffer memory configuration in which the odd-numbered display data Kd and the even-numbered display data Gd having a function of temporarily storing the display data are independently arranged for each system. For example, when 10a, 10c) is in the data writing operation, the other (for example, 10b, 10d) only performs the reading operation, and if the FM is being written, all the data for one screen is written. And read-only, and the other is for writing.

At this time, in the present invention, as shown in FIG. 2, two even numbers are simultaneously read from the five-sided FM at the same time in the odd-numbered column display data series of the double buffer memory structure. F with two arranged in the series of column display data
Further, two large-capacity memories A and B are used for each M. That is, for each of the two sides A, B
A RAM (one side is “128K × 8” bits) is used. Then, the FM10a and 10b have odd-numbered display data Kd.
Is an input data consisting of a ROM or a RAM provided in the preceding stage.
LT20 that has the function of converting data according to the table contents
The converted data is led through a data bus via a, and even column display data Gd is provided in FM10c and 10d.
Is guided from the data bus via LT20b.

30a1, 30b1, 30c1 and 30d1 are FM /
DB for reading provided on the data bus connecting between the selectors 40, 30a2 is between LT20a / FM10a, and 30b2 is L
D for writing provided on the data bus provided between T20a / FM10b for guiding (writing) the odd-numbered column display data converted by LT20a to FM10a or 10b on the writing side.
B, 30c2 is between LT20b and FM10c, 30d2 is LT20b
Guides (writes) the even-numbered column display data converted by LT20b between the FM / FM10d and the FM10c or 10d on the writing side.
Are DBs provided on the data bus on the input side for controlling the read / write of the data of each FM under the control of a buffer control circuit (not shown). ..

The selector 40 is the FM 10a (or 10b) 2
Since the planes A and B or the two planes A and B of the FM 10c (or 10d) are read out at the same time, one of these two data A and B is selected and outputted to D / A5. That is, each DB is controlled by the buffer control circuit to read the data of each FM data.
Read / write, and store data of FM with selector 40
During storage, one of the storage data read simultaneously from the two memories A and B of the FM is selected and output. D
Since / A is the same, description is omitted.

In such a structure, the operation is as follows. This will be described with reference to FIGS.

(A) First, the input data is converted by LT.

(B) The data of the LT output after conversion (here, 8 bits per pixel after LT output conversion) is F
Store in M. The data storage method at this time is shown in Fig. 2 *
As shown by 1, * 2, ..., * 10, * 20, ..., the pixel data sequentially input in the row direction are scattered on the A side in consideration of high speed reading at the time of reading. * 1 → O1 -1 (/ O1 -33 / O1 -67 / O1 -100 /
O1 −133) → * 2 → O1 −2 (/ O1 −34 / O1 −68 / ...): Similarly, for side B, similarly, * 10 → O1 −1 ′ (/ O1 −33 ′). / O1 -67 '/ O1
-100 '/ O1 -133') → * 20 → O1 -2 '(/ O1 -34' / O1 -68 '/ ...)

(C) At the time of reading, reading is performed in the order of addresses. In other words, in the present invention, the conventional simultaneous reading from the five FMs is performed at high speed from the two memories A and B as shown in FIG. 2γ.

(D) The selector 40 selects one of the read two data A and B and outputs it to D / A5.

(E) As a result, as shown in FIG. 3, it is possible to read the data groups which were simultaneously read out in the conventional manner at high speed in time series and to supply them to D / A5 with a slight time difference.

[0027]

As described above, according to the present invention, the LT is arranged in the preceding stage of the FM and the FM data storage method is changed. Play.

(A) By using a large capacity memory, I
The number of C can be reduced. That is, both the FM and the LT have large memory capacities, but the number of chips can be greatly reduced by reducing FM by 70% and LT by 80%.

(B) The data bus and DB can be greatly reduced by 60%.

(D) From this, a great improvement effect can be seen such as reduction in mounting and power consumption.

[Brief description of drawings]

FIG. 1 is a diagram showing a specific example of a display circuit of a liquid crystal display of the present invention.

FIG. 2 is a diagram for explaining FIG.

FIG. 3 is a time chart used to explain FIG.

FIG. 4 is a diagram of a display circuit of a conventional liquid crystal display.

5 is a diagram for explaining FIG. 4; FIG.

FIG. 6 is a diagram for explaining FIG. 4;

[Explanation of symbols]

 1a to 1d, 10a to 10d Frame memory (FM) 2a to 2e, 20a, 20b Look-up table (LT) 4, 40 Selector 5 Digital-analog conversion circuit (D / A)

Claims (1)

[Claims] 1. A frame memory having a double buffer memory structure in which one performs only a read operation while the other performs a data write operation, and an odd column display data side and an even column display data are provided in the frame memory.
Liquid crystal using a look-up table memory that is independently arranged on the data side, inputs read data stored in the frame memory, converts the read data according to the contents of the table, and outputs the converted data. In a display circuit of a liquid crystal display for performing a display operation, a frame memory (10a / 10a) having a double buffer memory configuration in which the odd-numbered display data and the even-numbered display data are independently arranged for each system. 10b and 10c / 10d)
, The data buffer for writing (30a2
.About.30d2), a look-up table memory (20a and 20b) is arranged for each series of the odd-numbered column display data and the even-numbered column display data, and each of the frame memories is arranged. Data buffer (30a1 to 30d1) for reading at the subsequent stage
), One selector (40) is arranged, and two are arranged in the odd-column display data series of the double buffer memory structure and two are arranged in the even-column display data series. Each frame memory further comprises two memories (A, B), and each of the data buffers is controlled by a buffer control circuit to store the data of each of the frame memories. Read / write is performed, and the storage data stored in the frame memory is read out simultaneously from the two memories (A, B) in the frame memory by the selector. A display circuit for a liquid crystal display, characterized in that one of the two is selected and output.