JPH0578938B2 - - Google Patents
Info
- Publication number
- JPH0578938B2 JPH0578938B2 JP59208619A JP20861984A JPH0578938B2 JP H0578938 B2 JPH0578938 B2 JP H0578938B2 JP 59208619 A JP59208619 A JP 59208619A JP 20861984 A JP20861984 A JP 20861984A JP H0578938 B2 JPH0578938 B2 JP H0578938B2
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- silicide
- insulating film
- point metal
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000002844 melting Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 17
- 230000008018 melting Effects 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E50/00—Technologies for the production of fuel of non-fossil origin
- Y02E50/30—Fuel from waste, e.g. synthetic alcohol or diesel
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体装置の
高融点金属あるいはそのシリサイドを電極配線に
用いた構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure of a semiconductor device in which a high melting point metal or its silicide is used for electrode wiring.
第２図ａ，ｂはそれぞれ従来の配線構造を説明
するための半導体装置の断面図であり、１はシリ
コン基板、２はフイールド酸化膜、３はゲート酸
化膜、４は多結晶シリコン、５は高融点金属ある
いはそのシリサイドである。ところで高融点金属
あるいはそのシリサイド５は後の工程の熱処理に
より多結晶シリコン５を通り抜け酸化膜２，３に
達する（第２図ｂ）。フイールド酸化膜２は厚い
ので高融点金属またはそのシリサイドによる影響
はほとんどないが、ゲート酸化膜３は薄いのでダ
メージを受け膜質が劣化し、半導体装置の信頼性
の低下の原因となつていた。
2A and 2B are cross-sectional views of a semiconductor device for explaining the conventional wiring structure, respectively, in which 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is polycrystalline silicon, and 5 is a It is a high melting point metal or its silicide. By the way, the high melting point metal or its silicide 5 passes through the polycrystalline silicon 5 and reaches the oxide films 2 and 3 by heat treatment in a later step (FIG. 2b). Since the field oxide film 2 is thick, it is hardly affected by the high melting point metal or its silicide, but the gate oxide film 3 is thin, so it is damaged and the film quality deteriorates, causing a decrease in the reliability of the semiconductor device.
本発明は上記従来例の欠点に鑑み提案されたも
のであり、ゲート酸化膜が高融点金属あるいはそ
のシリサイドからのダメージを受けることのない
電極配線構造を有する半導体装置の提供を目的と
する。
The present invention has been proposed in view of the above-mentioned drawbacks of the conventional example, and an object thereof is to provide a semiconductor device having an electrode wiring structure in which a gate oxide film is not damaged by a high-melting point metal or its silicide.
本発明による半導体装置は、半導体基板の表面
に形成されたゲート絶縁膜及びフイールド絶縁膜
を横切る電極配線が多結晶シリコンと高融点金属
あるいはそのシリサイドとでなる複合膜で構成さ
れた半導体装置において、上記ゲート絶縁膜上の
前記多結晶シリコンと高融点金属あるいはそのシ
リサイドとの間には絶縁膜が設けられ、上記多結
晶シリコンと上記高融点金属あるいはそのシリサ
イドとの接続は上記フイールド絶縁膜上のみで行
われていることを特徴とする。
A semiconductor device according to the present invention is a semiconductor device in which an electrode wiring that crosses a gate insulating film and a field insulating film formed on the surface of a semiconductor substrate is composed of a composite film made of polycrystalline silicon and a high melting point metal or a silicide thereof. An insulating film is provided between the polycrystalline silicon and the high melting point metal or its silicide on the gate insulating film, and the connection between the polycrystalline silicon and the high melting point metal or its silicide is only on the field insulating film. It is characterized by being carried out in
以下図面を参照して本発明を説明する。第１図
ａ，ｂはそれぞれ本発明に係る半導体装置を説明
するための断面図であり、１はシリコン基板、２
はフイールド酸化膜、３はゲート酸化膜、４は多
結晶シリコン、５は高融点金属、あるいはそのシ
リサイドであり、１６は多結晶シリコン４と高融
点金属あるいはそのシリサイド５を活性化領域上
で分離する絶縁膜である。多結晶シリコン４と高
融点金属５あるいはそのシリサイドとの接続は、
非活性領域上で行われている（なお活性化領域と
は、ゲート酸化膜が形成されているトランジスタ
等の存在する領域をいう。また非活性化領域とは
活性化領域以外の領域をいい、たとえば実施例で
示すように厚いフイールド酸化膜２が存在する領
域をいう。）。そのため後の熱処理工程を経ても活
性化領域上の多結晶シリコンはその上の絶縁膜に
より高融点金属あるいはそのシリサイドの侵入に
よるダメージは阻止され、ゲート酸化膜の劣化は
ない（第１図ｂ）。
The present invention will be explained below with reference to the drawings. FIGS. 1a and 1b are cross-sectional views for explaining the semiconductor device according to the present invention, in which 1 is a silicon substrate, 2
is a field oxide film, 3 is a gate oxide film, 4 is polycrystalline silicon, 5 is a high melting point metal or its silicide, and 16 is a polycrystalline silicon 4 and a high melting point metal or its silicide 5 separated on the active region. It is an insulating film that The connection between polycrystalline silicon 4 and high melting point metal 5 or its silicide is as follows:
The activation is performed on a non-active region (an active region refers to a region where a transistor, etc., on which a gate oxide film is formed is present; a non-active region refers to a region other than an active region; For example, as shown in the embodiment, it refers to a region where a thick field oxide film 2 exists.) Therefore, even after the subsequent heat treatment process, the polycrystalline silicon on the active region is prevented from being damaged by the intrusion of high-melting point metals or their silicides due to the insulating film thereon, and there is no deterioration of the gate oxide film (Figure 1b). .
〔発明の効果〕
以上説明したように、本発明によれば活性化領
域の多結晶シリコン上に絶縁膜が存在するため、
高融点金属あるいはそのシリサイドの通り抜けを
阻止できる。従つてゲート酸化膜の劣化等を防止
できるので半導体装置の信頼性の向上を図ること
ができる。[Effects of the Invention] As explained above, according to the present invention, since the insulating film exists on the polycrystalline silicon in the active region,
It can prevent high melting point metals or their silicides from passing through. Therefore, since deterioration of the gate oxide film can be prevented, the reliability of the semiconductor device can be improved.
第１図ａ，ｂはそれぞれ熱処理工程前及び後の
本発明の実施例に係る半導体装置の断面図、第２
図ａ，ｂはそれぞれ熱処理工程前及び後の従来例
に係る半導体装置の断面図である。
１……シリコン基板、２……フイールド酸化
膜、３……ゲート酸化膜、４……多結晶シリコ
ン、５……高融点金属あるいはそのシリサイド、
１６……絶縁膜。
1a and 1b are cross-sectional views of a semiconductor device according to an embodiment of the present invention before and after a heat treatment process, respectively;
Figures a and b are cross-sectional views of a conventional semiconductor device before and after a heat treatment process, respectively. 1...Silicon substrate, 2...Field oxide film, 3...Gate oxide film, 4...Polycrystalline silicon, 5...High melting point metal or its silicide,
16...Insulating film.
Claims (1)
及びフイールド絶縁膜を横切る電極配線が多結晶
シリコンと高融点金属あるいはそのシリサイドと
でなる複合膜で構成された半導体装置において、 前記ゲート絶縁膜上の前記多結晶シリコンと高
融点金属あるいはそのシリサイドとの間には絶縁
膜が設けられ、前記多結晶シリコンと前記高融点
金属あるいはそのシリサイドとの接続は前記フイ
ールド絶縁膜上のみで行われていることを特徴と
する半導体装置。[Scope of Claims] 1. A semiconductor device in which an electrode wiring that crosses a gate insulating film and a field insulating film formed on the surface of a semiconductor substrate is composed of a composite film of polycrystalline silicon and a high melting point metal or its silicide, An insulating film is provided between the polycrystalline silicon and the high melting point metal or its silicide on the gate insulating film, and the connection between the polycrystalline silicon and the high melting point metal or its silicide is only on the field insulating film. A semiconductor device characterized by being made in.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59208619A JPS6185843A (en) | 1984-10-04 | 1984-10-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59208619A JPS6185843A (en) | 1984-10-04 | 1984-10-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6185843A JPS6185843A (en) | 1986-05-01 |
| JPH0578938B2 true JPH0578938B2 (en) | 1993-10-29 |
Family
ID=16559221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59208619A Granted JPS6185843A (en) | 1984-10-04 | 1984-10-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6185843A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745967A (en) * | 1980-09-04 | 1982-03-16 | Toshiba Corp | Semiconductor device |
| JPS57122540A (en) * | 1980-12-09 | 1982-07-30 | Fairchild Camera Instr Co | Multilayer metallic silicide mutual wire for integrated circuit |
| JPS5893347A (en) * | 1981-11-30 | 1983-06-03 | Toshiba Corp | Metal oxide semiconductor type semiconductor device and its manufacture |
-
1984
- 1984-10-04 JP JP59208619A patent/JPS6185843A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745967A (en) * | 1980-09-04 | 1982-03-16 | Toshiba Corp | Semiconductor device |
| JPS57122540A (en) * | 1980-12-09 | 1982-07-30 | Fairchild Camera Instr Co | Multilayer metallic silicide mutual wire for integrated circuit |
| JPS5893347A (en) * | 1981-11-30 | 1983-06-03 | Toshiba Corp | Metal oxide semiconductor type semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6185843A (en) | 1986-05-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |