JPH0577341B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor circuit such as a semiconductor memory constructed using MOS transistors, such as a semiconductor device such as a dynamic MOS/RAM, and particularly relates to a semiconductor device such as a dynamic MOS/RAM. The present invention relates to a semiconductor device including a circuit.

(Prior Art) Fig. 4 is a diagram showing an example of the configuration of a conventional semiconductor device. (This circuit will be referred to as a MOS circuit in the following explanation.) and aluminum wiring for supplying a power supply voltage to the MOS circuit. In FIG. 4, reference numeral 1 is a semiconductor chip for dynamic MOS/RAM. Reference numeral 2 denotes a power supply voltage supplying aluminum wiring (Vcc aluminum wiring) which is wired on the semiconductor chip 1 and supplies the power supply voltage (Vcc) to the MOS circuit. Reference numeral 3 denotes a power supply terminal (Vcc
power supply terminal). 4 is the ground (Vss) level power supply voltage wired on the semiconductor chip 1.
This is aluminum wiring (aluminum wiring for Vss) that supplies the circuit. Reference numeral 5 denotes a power supply terminal (Vss power supply terminal) for externally applying a ground level voltage to the semiconductor chip 1 through the Vss aluminum wiring 4.

Reference numeral 6 denotes a MOS circuit constructed using MOS transistors arranged on the semiconductor chip 1.

A conventional semiconductor device is configured as described above. In this case, the Vcc power terminal 3 is directly connected to the Vcc aluminum wiring 2, and the Vss power terminal 5 is directly connected to the Vss aluminum wiring 4. semiconductor chip 1
In the MOS circuit 6 arranged above, a Vcc level voltage applied from the outside between the Vcc power supply terminal 3 and the Vss power supply terminal 5 is directly applied to the Vcc aluminum wiring 2 and the Vss aluminum wiring 4. The MOS circuit 6 is made to operate by applying the voltage through the MOS circuit 6.

(Problems to be Solved by the Invention) However, in the above conventional device, as shown in FIG.
Resistor 7 in the diagram between aluminum wiring 4 for Vss
When an electrical short-circuit condition as expressed by
It flows for a long time between it and the Vss power supply terminal 5.

For example, when the semiconductor chip 1 is in a wafer state, a voltage at the Vcc level is applied to each of the Vcc power supply terminal 3 and the Vss power supply terminal 5 through a probing needle (probe needle). Then, the excessive short-circuit current i flows through the probe needle for a long time, and as a result, the probe needle may melt due to the excessive short-circuit current, or the external power supply that applies the voltage at the Vcc level may be destroyed. The following problem arises.

Furthermore, as shown in FIG. 5, in particular, when a large number of RAM semiconductor chips 1 are arranged on a wafer and assembled without scribing the wafer, in other words, the wafer is assembled as is (called wafer scale integration). ), there are also problems as described below.

In FIG. 5, a large number of RAM semiconductor chips 1a,
1a', 1a''..., 1b, 1b', 1b'',..., 1
c, 1c', 1c'', ..., 1d, 1d', 1d'', ...
each corresponds to the semiconductor chip 1 shown in FIG.
The Vcc power supply terminals 3 on each semiconductor chip are commonly connected to each other using separate aluminum wiring on the wafer, and the Vss power supply terminals 5 on each semiconductor chip are connected together using separate aluminum wiring on the wafer. They are commonly connected to each other.

Even if there is only one semiconductor chip on a wafer, there is an electrical short circuit between the Vcc aluminum wiring 2 (indicated by a solid line) and the Vss aluminum wiring 4 (indicated by a broken line). If so, in the case of the power supply voltage supply circuit in the conventional semiconductor device shown in FIG. 4, the power supply voltage would drop due to an excessive short circuit current flowing through the semiconductor chip in which the electrical short circuit exists. There is a problem in that a normal level power supply voltage cannot be applied to other normal semiconductor chips.

The present invention solves the above problems and provides a
Even if an electrical short circuit exists between both aluminum wiring lines for Vss, it prevents excessive short circuit current from flowing for a long period of time, and even after that, current consumption in the semiconductor chip is suppressed to zero. The object of the present invention is to provide a semiconductor device that can perform the following steps.

(Means for Solving the Problems) In order to achieve the above object, the present invention takes the following configuration. The power supply voltage supply circuit includes a semiconductor circuit and a power supply voltage supply circuit for the semiconductor circuit, and the power supply voltage supply circuit includes a power supply terminal for applying a power supply voltage to the semiconductor circuit, a ground terminal for applying a ground potential, and a power supply terminal for applying a power supply voltage to the semiconductor circuit. A semiconductor device including a power supply wiring that is electrically connected to supply a current to the semiconductor circuit, and a ground wiring that is electrically connected to the ground terminal and supplies a ground potential to the semiconductor circuit. The circuit includes switching means provided in series between the power supply terminal and the power supply wiring, between the ground terminal and the ground wiring, or between both, and the switching means being disconnected. a fuse element for inactivating the fuse element, a retaining means for keeping the switching means inactive after disconnection of the fuse element, and a high voltage voltage higher than the power supply voltage applied to the power supply terminals for sufficiently turning on the switching means; It is characterized by comprising a high voltage generating means for generating voltage.

(Function) The function of the configuration of the present invention is as follows. That is, according to this configuration, the switching means provided in series between the power supply terminal and the ground wiring in the power supply voltage generating circuit and between the ground terminal and the ground wiring can be turned off by the fuse element.

Further, since the power supply voltage generating circuit includes a high voltage generating means, the switching means can be sufficiently turned on by the high voltage output of the high voltage generating means.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention, and numerals 1 to 6 are the same as those of the conventional semiconductor device described above. That is, 1 is a semiconductor chip, 2 is an aluminum wiring for Vcc, 3 is a power supply terminal for Vcc, 4 is an aluminum wiring for Vss, 5 is a power supply terminal for Vss, and 6 is a MOS circuit as a semiconductor circuit.

8 is N channel as a switching means
It is a MOS transistor, and this transistor 8
has its gate connected to the node N2, its source connected to the Vss power supply terminal 5, and its drain connected to the Vss aluminum wiring 4.
In other words, the source and drain of the transistor 8 are inserted and connected to the aluminum wiring 4 for Vss. A fuse element 9 has one end connected to the Vcc power supply terminal 3 via the Vcc aluminum wiring 2, and the other end connected to the node N1. The fuse element 9 can be cut by laser light or by electrically passing an excessive current, but the specific cutting method is not the subject matter of the present invention and will therefore be omitted. be done.

Reference numeral 14 denotes a high voltage generating circuit that generates a voltage higher than the Vcc level, and current is supplied to this high voltage generating circuit 14 from the Vcc power supply terminal 3 through the fuse element 9. The output voltage higher than the Vcc level from the high voltage generation circuit 14 is output to the radar N2.

Reference numeral 10 denotes a resistor serving as a holding means, which has one end connected to the node N2 and the other end connected to the Vss power supply terminal 5. The resistor 10 has a sufficiently high resistance value. Therefore, the value of the current flowing from the Vcc power supply terminal 3 to the Vss power supply terminal 5 via the fuse element 9 is limited to an extremely small value due to the large resistance value of the holding resistor 10.

FIG. 2 shows the high voltage generation circuit 14 shown in FIG.
It is a figure showing an example. In Figure 2, reference numeral 1
Reference numeral 5 denotes a ring oscillator constructed by cascading an odd number of inverters, and current is supplied to the ring oscillator 15 through a node N1.
16 is a capacitor, and one end of the capacitor 16 is connected to a node N3 which is the output of the ring oscillator 15.
The other end is connected to node N4. 17 is connected to the node N along with the gate and drain.
1 and the source connected to node N4; 18 is an N-channel MOS transistor connected together with the gate and drain to node N4 and the source connected to node N2;
It is a MOS transistor. Then, the charge pump circuit composed of the capacitor 16 and the transistors 17 and 18 receives the oscillation clock that is the output of the ring oscillator 15, and outputs the signal to the node N2.
Generates a voltage V _GG higher than the Vcc level.

Since the output load of the high voltage generating circuit 14 having such a configuration is only the resistor 10 having a sufficiently high resistance value, the current consumption in the high voltage generating circuit 14 can be suppressed to an extremely low level.

Therefore, even if current is supplied to the high voltage generation circuit 14 through the fuse element 9, the fuse element 9 will not be disconnected, and the voltage drop there can be ignored.

In the semiconductor device configured as described above, in a normal case, that is, when the fuse element 9 is not cut, a voltage at the Vcc level is applied between the Vcc power supply terminal 3 and the Vss power supply terminal 5. Then, the high voltage generating circuit 14 operates and a voltage higher than the Vcc level is applied to the gate of the transistor 8. In other words, since the transistor 8 is turned on sufficiently, the Vss aluminum wiring 4 has Vss.
The level is transferred through transistor 8 and there is no loss of voltage. The wiring resistance value of the Vss aluminum wiring 4 is determined by the width of the wiring, for example.
If the resistance is 50μm and the length is 10mm, then the sheet resistance of aluminum is 50mΩ/□ and it becomes 10Ω.
Therefore, if the channel width of the transistor 8 is set so that the impedance of the transistor 8 is smaller than 10Ω, the impedance loss caused by the transistor 8 can be ignored.

By the way, when an electrical short circuit exists between the Vcc aluminum wiring 2 and the Vss aluminum wiring 4, an excessive short circuit current i flows. Here, the semiconductor chip 1 is in a wafer state, and a voltage at the Vcc level is applied to each of the Vcc power supply terminal 3 and the Vss power supply terminal 5 via a probe needle. An excessive short circuit current is detected by an external tester, and in conjunction with this, the fuse element 9 is cut using, for example, a laser beam. Then, the node N2 is fixed at the Vss level by the resistor 10, so the gate voltage of the transistor 8 becomes the Vss level, and the transistor 8 is completely turned off.

By the above operation, it is possible to prevent an excessive short circuit current i from flowing between the Vcc power terminal 3 and the Vss power terminal 5 for a long time. Current consumption can be reduced to zero. This means that even if a large number of semiconductor chips 1 are arranged on a wafer and assembled as a wafer without scribing the wafer as shown in FIG.
If there is an electrical short circuit between the Vcc aluminum wiring and the Vss aluminum wiring in a semiconductor chip, the fuse element of the semiconductor chip can be cut to prevent current from flowing. Therefore, it is possible to prevent the power supply voltage from dropping due to an excessive short-circuit current flowing in a semiconductor chip where an electrical short circuit exists, and from being unable to apply a normal level of power supply voltage to other normal semiconductor chips. As a result, the wafer can be assembled without affecting other normal semiconductor chips.

FIG. 3 is a block diagram of a semiconductor device according to still another embodiment of the invention. In Fig. 3, reference numeral 1
6 to 6 and 8 to 10 are exactly the same as the embodiments of the present invention described above. However, instead of supplying current to the high voltage generation circuit 14 from the Vcc power supply terminal 3, the fuse element 9
One end of is connected to the output of the high voltage generation circuit 14,
The difference is that the other end is connected to node N2.
In FIG. 6, the same effect as in FIG. 1 can be achieved by cutting the fuse element 9.

In addition, in the above embodiment, the dynamic MOS
Although the case of RAM has been described, it goes without saying that the present invention can be broadly applied to semiconductor memories such as static RAM and ROM.

(Effects) As is clear from the above explanation, according to the present invention, switching means is provided between the power terminal and the power wiring, between the grounding terminal and the grounding wiring, or between both, and the switching Since the switching means is inactivated by cutting the fuse element, and the holding means maintains the inactive state of the switching means even after the fuse element is cut, there is no electricity between the power supply terminal and the ground terminal. Even if a short-circuit condition occurs and an excessive short-circuit current attempts to flow, the fuse element is cut and the switching means becomes inactive, resulting in electrical non-continuity between the power supply or ground terminal and the wiring. This can prevent the short circuit current from flowing.

Therefore, in the present invention, as described above, it is possible to prevent the probe needles used in the semiconductor chip from melting due to the short circuit current in conventional semiconductor devices, and the destruction of the external power supply. Moreover, wasteful current consumption due to short circuit current can be suppressed to zero.

[Brief explanation of drawings]

1 to 3 are configuration diagrams of semiconductor devices showing respective embodiments of the present invention. FIG. 4 is a block diagram of a conventional semiconductor device, and FIG. 5 is a plan view of a wafer on which a large number of semiconductor chips are arranged. In the figure, 1 is a semiconductor chip, 2 is an aluminum wiring for Vcc, 3 is a power supply terminal for Vcc, and 4 is a Vss
5 is the power supply terminal for Vss, 6 is the aluminum wiring for
MOS circuit, 8 is an N-channel MOS transistor, 9 is a fuse element, 10 is a resistor, and 14 is a high voltage generation circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor circuit, and a power supply voltage supply circuit for the semiconductor circuit, wherein the power supply voltage supply circuit includes: a power supply terminal that applies a power supply voltage to the semiconductor circuit; and a ground terminal that applies a ground potential. A semiconductor comprising: a terminal; a power wiring electrically connected to the power terminal to supply a current to the semiconductor circuit; and a ground wiring electrically connected to the ground terminal to supply a ground potential to the semiconductor circuit. In the apparatus, the power supply voltage supply circuit is connected to a switching means provided in series between either the power terminal and the power wiring, the ground terminal and the ground wiring, or both; a fuse element for inactivating the switching means by cutting; a holding means for keeping the switching means inactive after cutting the fuse element; 1. A semiconductor device comprising: high voltage generating means for generating a high voltage higher than a power supply voltage.