JPH0576043B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit having a plurality of reference voltage output lines.

There are cases in which a circuit power source is stepped down to provide a reference voltage for a necessary circuit section, and a voltage dividing circuit using a resistor element is used as a simple method. however,
In this method, since the DC output impedance is not small, the output reference voltage fluctuates due to load fluctuations. In particular, when the load is heavy and there are DC-like load fluctuations, the output voltage fluctuates significantly. Therefore, if there are other loads that are supplied with a common reference voltage, Adversely affect.

An object of the present invention is to provide a reference voltage generation circuit having a simple configuration, low DC output impedance, and a plurality of reference output lines.

A reference voltage generating circuit according to the present invention is a reference voltage circuit used in an overshoot suppression circuit of a switching noise reduction system including an amplifier that amplifies an input signal and an amplitude limiting circuit that limits the amplitude of the output signal of the amplifier. The series circuit includes a pair of complementary transistors whose emitters are connected to each other and a DC voltage is applied between their collectors, and two diodes connected in series with the same forward direction. a voltage dividing circuit whose voltage at both ends is the base voltage of each of the transistors, a heavy load reference voltage as a bias power source for the amplitude limiting circuit is derived from the connection point between the emitters, and a connection between the two diodes. A light load reference voltage as a bias voltage for the input signal of the amplifier is derived from the point.

The present invention will be explained below with reference to the drawings.

FIG. 1 shows a reference voltage generation circuit according to an embodiment of the present invention. In this circuit, a simple resistive voltage divider circuit 1 divides a DC circuit power supply V _CC into a plurality of divided voltage outputs.
Basically, the resistors R ₁ and R ₂ are connected in series, but between the resistors R ₁ and R ₂ there are two diodes D ₁ and D ₂ connected in series. A circuit is added, and these diodes D ₁ , D ₂
A first reference voltage output V _R1 is derived from the common connection point of .

Furthermore, a pair of mutually complementary active elements, NPN and PNP transistors Q ₁ and Q ₂
are connected in series between the DC circuit power supply V _CC and the ground, forming a so-called single-ended configuration 2. That is, the emitters, which are controlled electrodes that are involved in the threshold value (V _BE ) of both transistors, are commonly connected, and the collector, which is the other controlled electrode, is connected to the positive power supply V _CC and the ground. The voltage across the diodes D ₁ and D ₂ , which _is the divided voltage output of the voltage divider circuit 1, is applied between the bases, which are the control electrodes _, of both _transistors . , Q ₂ base bias is generated. The common emitter of both transistors serves as a second reference voltage output V _R2 . Note that _C1 is an AC bypass capacitor.

The above is the configuration of the embodiment of the reference voltage generation circuit according to the present invention, and the plurality of outputs V _R1 and V _R2 are used as the reference voltage in, for example, a circuit device as shown. The figure shows a part of the so-called Dolby noise reduction system circuit (C type), which is a noise reduction method for tape recorders, and is an example of an overshoot suppression circuit in the sub-signal path of the high-level stage. It is.

In the Dolby noise reduction method,
The low-level mid-high range signal is compressed and recorded, and then expanded during playback to restore the original signal. The degree of signal compression and expansion is changed depending on the level of the signal being recorded or played back. When the level of the signal is low, the signal is recorded relatively highly compressed so that it has a relatively high level relative to noise, and is correspondingly expanded relatively greatly and played back. When the signal level is relatively high, the signal itself has a high level relative to the noise, and a relatively large signal/noise ratio may be obtained, so that the signal is hardly compressed or expanded. When the signal in the mid-high range has a large level, by doing little compression when recording the signal,
This means that the maximum recordable signal level can be maintained at a large value regardless of the saturation characteristics of the recording tape.

In order to control the amount of compression and expansion according to the signal level, a detection circuit for detecting the signal level is provided. When there is a sudden and large change in the input signal level for recording, the signal detection circuit must be equipped with a time constant circuit for rectification. Distortion may occur when the upper limit of the dynamic range is exceeded, so an overshoot subtraction circuit 3 is used to prevent this.
This circuit 3 has a well-known amplitude limiting (slicer) circuit configuration consisting of diodes D ₃ to _{D 6} , and the amplitude limiting circuit consisting of diodes D ₃ and D ₄ controls the signal passed through the resistor R ₄ of the amplified output of the operational amplifier OP. An amplitude limiting circuit consisting of diodes D ₅ and D ₆ connects the signal line via resistors R ₄ and R ₅ of the amplified output of the operational amplifier OP to the reference voltage (V _R2 ) line and the reference voltage (V R2 ) line. It is provided between the voltage (V _R2 ) line. Note that the resistors R ₆ and R ₇ and the capacitor C ₂ form a negative feedback network for the operational amplifier OP.

Here, there are two Dolby noise reduction methods, type B and type C. One of the differences between the two types is that the B type has one circuit stage for signal compression and expansion, whereas the C type has a relatively high operating threshold for signal compression and expansion. A circuit stage with a relatively low operating threshold for signal compression and expansion (low-level stage) is arranged in a cascade relationship. There is. The circuit stages forming the B type and the high level stage in the C type are made to almost correspond in terms of characteristics, but the slice levels of the overshoot suppression circuits in each are made to be different. The slice level of the overshoot suppression circuit shown in FIG. 1 can be changed so that it can be applied to both the C type and the B type. i.e. diode D ₃ and
In order to control the slice level by turning on and off the amplitude limiting circuit consisting of _D4 , a switching transistor _Q3 , which is turned on by a B-type method, is provided between this circuit and the reference voltage (V _R2 ) line. There is.

The divided voltage output V _R1 from the resistor voltage divider circuit 1 is applied to the positive phase input, which is the signal input of the operational amplifier OP, via the resistor _R8 , and the input signal is passed through the coupling capacitor _C3 for DC blocking. This is the positive phase input of this operational amplifier OP. Since the positive-sequence input of the operational amplifier has a high input impedance, the inflow of DC current can be ignored, and the bias power supply to this positive-sequence input can be used without any problem even if its DC output impedance is small. The divided voltage output V _R1 of a simple resistance voltage divider circuit 1 is used.

On the other hand, overshoot suppression circuit 3
When transistor Q ₃ is turned on and off to control the characteristics of transistor Q 3 , a DC current flows through transistor Q ₃ from its collector to emitter, and the bias current value fluctuates greatly. There needs to be.
Therefore, the output voltage V _R2 of the single-ended configuration 2 formed by transistors Q ₁ and Q ₂ is used. Since this circuit 2 has a common emitter output for the transistors Q ₁ and Q ₂ , it operates as a so-called emitter follower circuit and exhibits an extremely low DC output impedance and also has a large current driving or drawing ability. Therefore, it is most suitable as a reference voltage supply source for a heavy load with severe DC load fluctuations, such as the overshoot suppression circuit 3 shown in the figure.

FIG. 2 is a block diagram schematically showing the above-mentioned Dolby C type noise reduction system, in which the input signal to be recorded passes through a main signal path consisting of a spectral shifting circuit 10 and an anti-saturation circuit 11. . The spectral skiving circuit 10 constitutes a filter for preventing extremely high frequency signals from being input to the subsequent high level stage 13 and the like.

Although the details of the high level stage 13 are not shown in the drawings since they are not directly related to the present invention, the high level stage 13 includes a variable filter that receives the signal from the spectral skewing circuit 10 and passes the middle and high frequency signals, and a It includes a detection circuit that receives an output signal, detects its level, and controls the variable filter according to the detected output, and an overshoot suppression circuit as shown in FIG. 1 described above that receives the output of the variable filter. . The output of the overshoot suppression circuit in the high level stage 13 is sent to the adder 15.
is supplied to The detection circuit in the high level stage 13 is configured to detect and rectify a relatively large level signal. The variable filter includes a variable resistor that is controlled by the output of the detection circuit, and the amount of signal attenuation therein increases as the detection output increases. As a result, the high-level stage 13 converts the mid-high range signal into the adder 15 with a relatively small attenuation amount when the mid-high range signal is at a relatively low level.
When the signal in the middle and high range reaches a relatively large level, it is transmitted to the adder 15 with a large amount of attenuation.

Adder 15 adds the input signal from spectral skewing circuit 10 and the input signal via high level stage 13 . Since the high level stage 13 is made to have the above-mentioned characteristics, the output of the adder 15 is a signal obtained by increasing (ie compressing) the low level middle and high range signal.

Anti-saturation circuit 11 is configured to limit the passage of high level signals.

Low-level stage 14 has substantially the same configuration as high-level stage 13, except that the characteristics of its detection circuit are made different from those of the high-level stage so that its operating threshold is a relatively small value. be made into

Adder 16 includes anti-saturation circuit 1
1 and the output of the low level stage 14 are added.

The output from the adder 16, in which the low-level middle and high frequency signals are compressed, is input to the deck 12 and recorded on tape.

In the Dolby C type noise reduction system, the low-level middle and high frequency signals during recording are compressed by 20 dB through the so-called encoding process.

During playback, decompression processing, so-called decoding processing, is performed in response to compression processing during recording. That is, the low-level mid-high frequency signal is expanded by 20 dB, contrary to the encoding process.

Circuits 16', 14', 1 for decoding processing
1', 13', 15', and 10' have the same structure as the above-mentioned circuits having numerical symbols without the ``'''.

As shown in the figure, the output of the adder 16' is phase-inverted by the signal inversion circuit INV and then supplied to the anti-saturation circuit 11' and the low level stage. In effect,
Low level stage 1 from output of deck 12
It functions as a subtracter that subtracts the output of 4' (mid-high range signal). As a result, adder 1
6' outputs a signal in which low-level middle and high frequency signal components are reduced.

Similarly, by phase inversion by the signal inversion circuit INV provided on the output side of the adder 15', the adder 15' outputs a signal in which the low-level middle and high frequency signals are reduced.

In the Dolby B type noise reduction system, the spectral skewing circuit 1
0,10' and anti-saturation circuit 11,
11' is bypassed, and switching control is performed so that the compression/expansion of the mid-high range signal in the auxiliary signal path is 10 dB.

Since the functions of these circuits are well known, they will not be particularly explained.

As described above, according to the present invention, the light load reference voltage for setting the bias voltage of the input signal to the amplifier circuit at the front stage of the overshoot suppression circuit of the switching type noise reduction system with a simple configuration, It becomes possible to generate reference voltages for multiple systems together with the heavy load reference voltage as a bias power supply for the amplitude limiting circuit that limits the amplitude of the output of the amplifier circuit, and thus effectively prevents adverse effects between loads. It's going to be a success.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a Dolby noise reduction system for a tape recorder. Explanation of symbols of main parts, 1... Voltage divider circuit, 2...
…Single-ended circuit using transistors,
3...overshoot suppression circuit,
Q ₁ , Q ₂ ... single-ended transistors.

Claims (1)

[Claims] 1 A reference voltage generation circuit used in an overshoot suppression circuit of a switching noise reduction system including an amplifier that amplifies an input signal and an amplitude limiting circuit that limits the amplitude of the output signal of the amplifier, the emitters of which are connected to each other. It includes a series circuit of a pair of complementary transistors connected to each other and having a DC voltage applied between their collectors, and two diodes connected in series with the same forward direction, and the voltage across the series circuit is set to the voltage across the transistors. It consists of a voltage dividing circuit for each base voltage, derives a heavy load reference voltage as a bias power supply for the amplitude limiting circuit from the connection point between the emitters, and inputs the amplifier from the connection point between the two diodes. A reference voltage generation circuit characterized in that a light load reference voltage is derived as a bias voltage for a signal.