JPH0574748A - History information recording system and semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a technique capable of recording easily more information in a unit of chip. CONSTITUTION:Information on the history in every chip is marked by inflicting damage on a pattern 8 for exclusive use for chip history information record with a laser beam, whereby it becomes possible to record more information, such as positional information on semiconductor chips 10 in a wafer 9, a lot number of the wafer 9 and a wafer number, in a unit of chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for recording history information for each chip on a semiconductor chip,
For example, the present invention relates to a technique effectively applied to a semiconductor memory device.

[0002]

2. Description of the Related Art A semiconductor integrated circuit chip such as a semiconductor memory device is provided with a chip number as the chip identification information. Conventionally, such chip numbering is
It has been performed by patterning a photomask for processing a passivation film with different numerical information corresponding to all the chips on the wafer, and transferring the pattern information of such a photomask onto the wafer.

Incidentally, as an example of a document describing pattern formation and transfer of pattern information onto a wafer,
"LSI Handbook (Pages 423 to 426) issued by Ohmsha, Ltd. on November 30, 1984.
Page) ”.

[0004]

As a result of the present inventor's examination of the conventional chip numbering, the patterning of numerical information on the passivation film processing photomask merely distinguishes the chip positions on the wafer. In other words, it was made clear that only information common to all lots could be recorded, and information was lacking in analysis of variations in chip characteristics. For example, in analyzing characteristics variations of chips, not only the chip position on the wafer, but also knowing the lot number and the wafer number is extremely useful on the product monitor,
In the above-described conventional chip numbering, it is only possible to grasp the chip position information on the wafer, but it is impossible to grasp the other information. If the photomask is made on a wafer-by-wafer basis, more information can be recorded, but in order to do so, photomasks must be produced for the number of wafers,
It takes time and labor, and the manufacturing cost of the LSI increases.

An object of the present invention is to provide a technique capable of easily recording more information in chip units.

Another object of the present invention is to provide a technique capable of easily recording information useful for each chip in analysis of variations in characteristics of chips.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, it includes a step of marking the history information for each chip by damaging the dedicated pattern for recording the history information for each semiconductor chip with a laser beam. At this time, the history information includes the position information of the chip on the wafer, the lot number of the wafer,
And a wafer number. The dedicated pattern for recording the history information for each semiconductor chip may be a fuse formed of polysilicon or the like.

[0010]

According to the above-mentioned means, marking the history information for each chip by damaging the dedicated pattern with the laser beam enables more information to be easily recorded in chip units. In addition, including the position information for each chip on the wafer, the lot number of the wafer in which the chip is included, and the wafer number in the history information makes it easy to provide useful information in analysis of chip characteristic variations in chip units. Can be recorded on.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 3 shows a silicon wafer (referred to as a wafer) for forming a dynamic RAM according to an embodiment of the present invention. As shown in the figure, a plurality of semiconductor chips 10 are arranged in a matrix on a substantially circular wafer 9.
Is formed. The semiconductor chip 10 is not particularly limited, but is a dynamic RAM formed by a known semiconductor integrated circuit manufacturing technique. In the present specification, a chip or a semiconductor chip also means a formation region thereof on the wafer.

FIG. 1 shows a dynamic RAM (random access memory) which is one of the plurality of semiconductor chips 10.
Memory) building blocks are shown.

In FIG. 1, a dynamic memory cell array (MA) 2 is arranged at the center of the dynamic RAM 1. The memory cell array 2 is matted into four arrays 2A, 2B, 2C and 2D, although not particularly limited thereto. Between the memory cell arrays 2A and 2B,
A column address decoder (YDEC) 3A is arranged,
Similarly, a column address decoder 3B is arranged between the memory cell arrays 2C and 2D. A sense amplifier (SA) 4A for amplifying the data read from the memory cell array 2A is arranged between the memory cell array 2A and the column address decoder 3A, and between the memory cell array 2B and the column address decoder 3A. A sense amplifier 4B for amplifying the data read from the memory cell array 2B is arranged. Similarly, a sense amplifier 4C for amplifying data read from the memory cell array 2C is arranged between the memory cell array 2C and the column address decoder 4C, and a sense amplifier 4C is arranged between the memory cell array 2D and the column address decoder 3B. A sense amplifier 4D for amplifying data read from memory cell array 2D is arranged. A row address decoder (XDEC) 5 for selecting word lines of the memory cell arrays 2A and 2B is provided between the memory cell arrays 2A and 2C.
A is arranged, and similarly, a row address decoder 5B for driving the word line of the memory cell arrays 2B and 2D is arranged between the memory cell arrays 2B and 2D. further,
In this embodiment, the dynamic RAM memory cell array 2A,
In the peripheral section 6 on the 2B side, a timing generation circuit (TG) for generating a timing signal supplied to each section of the dynamic RAM, a data input buffer (DinB) for fetching data from the outside, and a memory cell array are provided. A data output buffer (DoutB), etc., which enables the external output of the read data of (1) is arranged. Then, the memory cell arrays 2C, 2 of the dynamic RAM according to the present embodiment.
A row address buffer (XADB) for fetching a row address signal from the outside and a column address buffer (YADB) for fetching a column address signal from the outside are arranged in the peripheral portion 7 on the D side.

In FIG. 1, reference numeral 8 denotes a chip history information recording dedicated pattern formed for each chip. The dedicated pattern 8 is not particularly limited, but the layout of functional modules is prohibited. It is formed by utilizing a portion, for example, a bonding pad forming area around the chip.

FIG. 2 shows an example of the chip history information recording dedicated pattern 8.

The chip history information recording-dedicated pattern 8 shown in FIG. 2 is a fuse group for recording the position information of the chip on the wafer, although not particularly limited thereto. This fuse group includes a first fuse group Xi that indicates position information of the chip in the X direction on the wafer, and a second fuse group Yi that indicates position information of the chip in the Y direction on the wafer. In the example shown in FIG. 2, the first fuse group Xi, as indicated by X1, X2 and X3,
In the second fuse group, a plurality of fuses are arranged in one direction, as indicated by Y1, Y2, and Y3. For example, the maximum number of chips on one wafer is X
Considering the case of 8 in the direction and 8 in the Y direction, in such a wafer, the X of one chip included in it is
Since each of the coordinates and the Y coordinate is represented by a binary number, 4 bits are required. Therefore, the first and second fuse groups Xi and Y are required.
i is set to 4 each. Such fuses are
Although not particularly limited, it can be formed of polysilicon, and the position information of the chip on the wafer can be written by damaging it by irradiation of laser light.

Here, a fuse used in a redundancy repair circuit of a semiconductor memory device or the like is electrically coupled to a power source or a circuit element such as a MOSFET, and a function can be selected depending on whether or not the fuse is blown. However, the fuse in the present embodiment is sufficient if it can physically indicate the positional information of the chip on the wafer depending on the presence or absence of damage, and therefore, the fuse is not required to be connected to a power source or a circuit element such as MOSFET. To be done. In other words, the chip history information recording dedicated pattern 8 is electrically isolated from the circuit element of the chip on which it is formed. This makes it possible to form a chip history information recording dedicated pattern in a region such as a bonding pad formation region where the placement of functional modules is prohibited and facilitates the layout design of the dedicated pattern 8. Further, for the same reason as above, the fuse does not have to be completely blown by the laser light, and it is sufficient if the fuse is melted to the extent that it is possible to determine the presence or absence of damage.

In the above description, the case of recording the position information of the semiconductor chip on the wafer has been described. However, the lot number and the wafer number of the wafer are also recorded in the same format as the pattern 8 for recording the chip history information shown in FIG. can do.

For example, the lot number and wafer number are replaced with binary numbers and recorded. When the lot number or wafer number is composed of an alphabet and a number, it is preferable to first replace the alphabet part with a number and then with a binary number. Although not particularly limited, “A”, “B”, “C”, “D”, ... are numbers such as “1”, “2”, “3”, “4”, ... Can be replaced with Therefore, in that case, the lot number "B8" is "000001", "100".
It is replaced with "0" and the fuse number is irradiated with the laser beam according to such information, so that the lot number and the wafer number can be recorded.

FIG. 4 shows another configuration example of the chip history information recording dedicated pattern.

The chip history information recording dedicated pattern 8A shown in FIG. 4 is a fuse group as in the case shown in FIG. 2, and this is the arrangement state of the plurality of semiconductor chips 10 on the wafer 9 shown in FIG. Are arranged in a matrix corresponding to. By damaging the fuse in such a chip history information recording dedicated pattern 8A with a laser beam, it becomes possible to record the position information of the semiconductor chip on the wafer 9. For example, the chip history information recording dedicated pattern 8A formed on the chip shown by hatching in FIG. 3 is damaged by irradiating the portion shown by hatching in FIG. It is possible to record position information.

According to the above embodiment, the following operational effects can be obtained.

(1) Chip history information recording dedicated pattern 8
By marking the history information for each chip by damaging 8A or 8A with a laser beam, more information such as the position information of the semiconductor chip 10 on the wafer 9, the lot number of the wafer 9 and the wafer number can be obtained on a chip basis. Can be recorded easily.

(2) When a semiconductor memory device such as a dynamic RAM includes a redundancy repair circuit, information is recorded on the chip history information recording dedicated pattern 8 or 8A in the step of blowing the fuse included in the repair circuit. Therefore, it is possible to avoid making a large change in the manufacturing process.

(3) In particular, including the position information for each chip in the wafer, the lot number of the wafer containing the chip, and the wafer number in the chip history information prevents inconvenience such as lot mixing after dicing. Dynamic RAM depending on chip position
The electrical characteristics and reliability of can be traced accurately, and useful information can be obtained in defect analysis of the dynamic RAM as a finished product.

(4) Pattern 8 dedicated to recording chip history information
And 8A are electrically isolated from the circuit element of the chip on which they are formed, so that a pattern for recording chip history information is formed in an area where the arrangement of functional modules is prohibited, such as a bonding pad formation area. And the layout design of the dedicated pattern is facilitated.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the case where the fuse is applied to the chip history information recording dedicated pattern has been described, but the chip history information may be recorded by directly irradiating the semiconductor substrate with laser light. Further, the chip history information recording-dedicated patterns may be dispersedly arranged on the same chip. Further, the shape, size, and location of the fuse forming the pattern for recording chip history information are arbitrary.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM which is the field of use as the background has been described. However, the present invention is not limited thereto and the static RA is used.
It can be widely applied to various semiconductor integrated circuits such as semiconductor memory devices such as M and ROM (read only memory), and further to microcomputers.

The present invention can be applied on condition that a plurality of semiconductor chips are cut out from at least one wafer.

[0031]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, more information can be easily recorded on a chip-by-chip basis by marking the history information for each chip by damaging the dedicated pattern with laser light. Further, by including the position information for each chip in the wafer, the lot number of the wafer in which the chip is included, and the wafer number in the history information, information useful in analysis of the characteristic variation of the chip is obtained in chip units. be able to.

[Brief description of drawings]

FIG. 1 is a dynamic R according to an embodiment of the present invention.
It is a layout plan view of a main block in AM.

FIG. 2 is an explanatory diagram of a chip history information recording dedicated pattern formed in the dynamic RAM.

FIG. 3 is a plan view of a wafer including the dynamic RAM.

FIG. 4 is an explanatory diagram of another configuration example of the chip history information recording dedicated pattern.

[Explanation of symbols]

 1 dynamic RAM 2, 2A to 2D memory cell array 3A, 3B column address decoder 4A to 4D sense amplifier 5A, 5B row address decoder 8, 8A chip history information recording dedicated pattern 9 wafer 10 semiconductor chip

Claims (6)

[Claims] 1. A history information recording system for recording history information for each semiconductor chip, wherein a pattern for exclusive use of history information formed on each semiconductor chip on a wafer before dicing is damaged by laser light. A history information recording method, characterized by including the step of marking the history information of each semiconductor chip by giving it. 2. The history information recording method according to claim 1, wherein the history information includes chip position information on the wafer, a wafer lot number, and a wafer number. 3. The history information recording system according to claim 1, wherein the history information recording dedicated pattern is a fuse electrically isolated from a circuit element included in a semiconductor chip. 4. A semiconductor integrated circuit including a history information recording dedicated pattern formed for each semiconductor chip, wherein the history information of the chip is imprinted by damaging the history information recording dedicated pattern with a laser beam. circuit. 5. The semiconductor integrated circuit according to claim 4, wherein the history information includes chip position information on a wafer, a wafer lot number, and a wafer number. 6. The semiconductor integrated circuit according to claim 4, wherein the history information recording dedicated pattern is a fuse electrically isolated from a circuit element included in the semiconductor chip.