JPH0574163A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a power current flowing at the resetting of an SRAM. CONSTITUTION:In a flip flop comprising CMOS inverter circuits 1 and 2 composing a memory cell of an SRAM, a power voltage Vcc' to be applied to the inverter circuit 2 is separated from a power source Vcc to be applied to the inverter circuit 2. In the normal operation of a memory cell, the power source voltage Vcc' to be applied to the inverter circuit 2 is made equal to the power source voltage Vcc to be applied to the inverter circuit 1 and the power source voltage Vcc' applied to the inverter circuit 2 in the resetting is changed to an earth potential. The earth potential GND can be applied in stead of the power source voltage Vcc' to turn an output of the inverter circuit 2 to a 'L' level thereby enabling the resetting of the memory contents of a memory cell 10 to '0'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a reset function for clearing the stored contents.

[0002]

2. Description of the Related Art FIG. 10 is a circuit diagram showing a system configuration of a conventional static random access memory (hereinafter referred to as SRAM). As shown in the figure, the output terminal of the inverter circuit 1 is connected to the input terminal of the inverter circuit 2, and the output terminal of the inverter circuit 2 is connected to the input terminal of the inverter circuit 1. A flip-flop formed by the inverter circuits 1 and 2 forms a memory cell 11. The output terminal of the inverter circuit 2 is connected to one terminal of the NchMOS transistor 4 via the point A, and the other terminal of the NchMOS transistor 4 is connected to the bit line B ₁ . Further, the output terminal of the inverter circuit 1 is connected to one terminal of the NchMOS transistor 5 via the point B, and the other terminal of the NchMOS transistor 5 is connected to the inverted bit line * B ₁ .
(* Indicates a bar. The bar is indicated by a bar symbol in the figure.)
The gates of the NchMOS transistors 4 and 5 are connected to the word line W ₁ .

Word lines W _{1 to} W _n and bit line B
_{1 to} B _m / inverted bit lines * B ₁ to * B _m are arranged in a matrix, and word lines W _{1 to} W _n and bit lines B _{1 to} B _m / inverted bit lines * B ₁ to * B _m.
Each memory cell is arranged at the intersection of. The memory cells connected to the bit lines B _{1 to} B _m / inverted bit lines * B ₁ to * B _m respectively form the first column 100 to the m-th column m00 of this SRAM.

Further, the word decoder 5 has a word line W.
_{1 to} W _n , the bit decoder 6 transmits the bit lines B _{1 to} B _n.
m / inverted bit line * B ₁ ~ * is connected to the B _m. Further, a sense amplifier / write driver 7 is connected to the bit decoder 6. A write enable signal * WE, a chip enable signal * CE, and a data input D are given to the sense amplifier / write driver 7, and a data output Q is output. Further, the address signal A is given to the word decoder 5 and the bit decoder 6.

Next, the operation of the SRAM will be described step by step. (1) First, the chip enable signal * CE becomes "L" level to enable read / write access to the SRAM. (2) The word decoder 5 and the bit decoder 6 receive the address signal A and select a word line and a bit line / inverted bit line corresponding to the address signal A. The selected word line becomes "H" level, and the selected bit line / inverted bit line is connected to the sense amplifier / write driver 7. Therefore, points A and B in the memory cell arranged at the intersection of the selected word line and the bit line / inverted bit line are connected to the sense amplifier / write driver 7. (3) At this time, the write enable signal * WE is "H"
If the level is in the read state, the potential difference between the points A and B is detected by the sense amplifier section in the sense amplifier / write driver 7, and this is output to the outside as the data output Q. (4) Conversely, if the write enable signal * WE is in the write state at the “L” level, the data input D is given to the points A and B by the write driver section in the sense amplifier / write driver 7. It is written in the memory cell 11. (5) When the address designated by the address signal A changes, the word line and the bit line / inverted bit line which have been selected so far are brought into the non-selected state, and other memory cells are accessed. At this time, the contents of the memory cell accessed last time are held in the flip-flop.

FIG. 11 is a circuit diagram showing a configuration for resetting the conventional SRAM system shown in FIG. At this time, the word decoder 5 selects the word line W
All _{1 to} W _n are selected. (Ie "H"
To level. ) The bit decoder 6 is a bitch of bit lines B ₁ ~B _m / inverted bit line * B ₁ ~ * B _m selected. (I.e., connected to the write driver portion of the sense amplifier write driver within 7.) Next, the storage contents of the memory cells for example, "L" when the level of the bit lines B ₁ ~B _m "L" level, to inverted bit line * B ₁ ~ * a B _m "H" level. Therefore, for example, the point A in the memory cell 11 becomes "L" level, the point B becomes "H" level, and the stored content of the memory cell 11 becomes "0".

[0007]

Since the conventional semiconductor memory device is configured as described above, when the semiconductor memory device is reset, for example, by the write driver unit in the sense amplifier / write driver 7, for example, the bit line B ₁ ~
The B _m to "L" level and the inverted bit line * B ₁ ~ * B
_{When m is set} to the “H” level and the stored content of the memory cell 11 is at the “H” level, as shown in the figure, the output terminal of the inverter circuit 2 in the memory cell 11 is connected to the sense amplifier via the point A. The power supply current I _cc flows to the write driver section in the write driver 7. This power supply current I _cc is small when viewed from one memory cell, but a large number of memory cells are consumed when the whole semiconductor memory device is viewed, and therefore a large amount of power supply current I _cc is consumed. There was a point.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor memory device capable of suppressing the power supply current flowing at the time of resetting.

[0009]

According to another aspect of the present invention, there is provided a semiconductor memory device having a memory cell formed of a flip-flop composed of first and second logic elements. Of the high-potential power supply and the low-potential power supply given to the logic element and the high-potential power supply and the low-potential power supply given to the second logic element, the high-potential power supply and the low-potential power supply given to the first and second logic elements are One of them is provided from another terminal.

[0010]

According to the present invention, the memory cell is the first or first of the high potential power supply and the low potential power supply supplied to the first logic element and the high potential power supply and the low potential power supply supplied to the second logic element. Since one of the high-potential power supply and the low-potential power supply provided to the second logic element is supplied from another terminal,
When the second logic element is composed of a CMOS inverter circuit and each of them is connected in a loop manner to form a flip-flop, for example, one of the high potential power supply and the low potential power supply supplied to the first logic element is changed to the other. Then, the output of the second logic element can be changed to one level of the high potential power supply or the low potential power supply, and the output of the second logic element can be changed to the other level of the high potential power supply or the low potential power supply. it can.

[0011]

1 is a SRA showing a first embodiment of the present invention.
It is a circuit diagram of a memory cell of M. As shown in the figure, P
The output terminal of the CMOS inverter circuit 1 constituted by the chMOS transistor 1a and the NchMOS transistor 1b has the PchMOS transistor 2a and the NchMOS.
It is connected to the input terminal of the CMOS inverter circuit 2 formed by the transistor 2b. The output terminal of the inverter circuit 2 is connected to the input terminal of the inverter circuit 1. The flip-flop formed by the inverter circuits 1 and 2 constitutes the memory cell 11a.

The output terminal of the inverter circuit 2 is connected to one terminal of the NchMOS transistor 4 via the point A, and the other terminal of the NchMOS transistor 4 is connected to the bit line B. Similarly, the output terminal of the inverter circuit 1 is connected to one terminal of the NchMOS transistor 5 via the point B, and the other terminal of the NchMOS transistor 5 is connected to the inverted bit line * B. The gates of the NchMOS transistors 4 and 5 are connected to the word line W.

The source of the PchMOS transistor 1a is connected to the power supply terminal V ₁ , and the source of the NchMOS transistor 1b is grounded. Also, Pc
The source of the hMOS transistor 2a is connected to the power supply terminal V ₂ , and the source of the NchMOS transistor 2b is grounded.

FIG. 2 is a sectional view showing an example of the vertical structure of the memory cell shown in FIG. As shown in the figure, P ⁻ substrate p
N ⁻ wells n1 and N ⁻ wells n2 are formed in the first region 1. In the N ^- well n1, a P ⁺ diffusion region p11 that serves as a source of the PchMOS transistor 1a and an N ⁺ diffusion region n3 used for fixing the potential of the N ^- well n1.
1 are formed adjacent to each other. Also, PchMO
P ⁺ diffusion region p1 which becomes the drain of the S transistor 1a
2 is formed. Further, a gate conductive layer c11 is formed on the surface of the N ⁻ well n1 between the P ⁺ diffusion regions p11 and p12.

Similarly, in the N ^- well n2, P ⁺ diffusion regions p21 and p22, a gate conductive layer c13, and an N ⁺ diffusion region n32 for fixing the potential of the N ^- well n2 are formed.

Further, in the P ⁻ substrate p1, N ⁺ diffusion regions n11 and P serving as sources of the NchMOS transistor 1b are formed.
^- P ⁺ diffusion region p31 to be used for fixing the potential of the substrate p1 is formed adjacent. Also Nch
An N ⁺ diffusion region n12 that serves as the drain of the MOS transistor 1b is formed. Further, a gate conductive layer c12 is formed on the surface of the P ⁻ substrate p1 between the N ⁺ diffusion regions n11 and n12.

Similarly, an N ⁺ diffusion region n is formed in the P ⁻ substrate p1.
21, n22, the gate conductive layer c14, and the P ⁻ substrate p1
A P ⁺ diffusion region p32 for fixing the potential of is formed.

The power supply terminal V ₁ has P ⁺ diffusion regions p11 and N ^+.
It is connected to the diffusion region n31 and the power supply terminal V ₂ is P ^+.
It is connected to the diffusion region p21 and the N ⁺ diffusion region n32. Further, the ground terminal GND is connected to the N ⁺ diffusion regions n11 and n1.
2 and P ⁺ diffusion regions p31 and p32. Further, the point A is the conductive layers c11 and c12 and the P ⁺ diffusion region p2.
In the 1, N ⁺ diffusion region n22, the point B is the conductive layer c13, c1.
4 and P ⁺ diffusion regions p12 and N ⁺ diffusion regions n12.

[0019] Conventional flip-flop, P ^- 1 single N in the substrate ^- since two PchMOS transistors in the wells have been formed, the N ^- when given different potentials to the wells, the N ^- well An electric current flows. However, in the flip-flop having the vertical structure shown in FIG.
N ^- wells n1 and n2 for forming the PchMOS transistors 1a and 1b are formed separately on the P ^- substrate p1. Therefore, no current flows in each N ^- well n1, n2.

FIG. 3 is a sectional view showing another example of the vertical structure of the memory cell shown in FIG. As shown in the figure, an N ^- well n1 is formed in a P ^- substrate p1. In this N ^- well n1, a P ⁺ diffusion region p11 which becomes the source of the PchMOS transistor 1a and an N ⁺ diffusion region n31 used for fixing the potential of the N ^- well n1 are formed adjacently. Also, similarly, PchMOS transistor 1
A P ⁺ diffusion region p12 that serves as the drain of a is formed. Further, the P ⁺ diffusion region p1 on the surface of the N ⁻ well n1
The conductive layer for gate c11 is formed in the portion between 1 and p12.

Similarly, a PchMOS is formed in the N ^- well n1.
A P ⁺ diffusion region p21 serving as the source of the transistor 1b is formed. The N ⁺ diffusion region p32 used for fixing the potential of the N ⁻ well n1 is formed without being adjacent to the P ⁺ diffusion region p21. Further, a P ⁺ diffusion region p22 which is also the drain of the PchMOS transistor 1b is formed. Furthermore, P ^{+ on} the surface of the N ^- well n1
A gate conductive layer c is formed between the diffusion regions p21 and p22.
13 is formed.

Further, an N ⁺ diffusion region n11 serving as the source of the NchMOS transistor 1b is formed in the P ⁻ substrate p1. Similarly, NchMOS transistor 1
N ⁺ diffusion region n12 to be the drain of b and P ⁻ substrate p1
A P ⁺ diffusion region p31 used for fixing the potential of is formed adjacently. Further, a gate conductive layer c12 is formed on the surface of the P ⁻ substrate p1 between the N ⁺ diffusion regions n11 and n12.

Similarly, an N ⁺ diffusion region n is formed in the P ⁻ substrate p1.
21, n22 and the gate conductive layer c14 are formed. Further, the N ⁺ diffusion region n22 is the above-mentioned P ⁻ substrate p1.
It is adjacent to the P ⁺ diffusion region p31 for fixing the potential.

The power supply terminal V ₁ has P ⁺ diffusion regions p11 and N ^+.
The power supply terminal V is connected to the diffusion regions n31 and n32.
₂ is connected to the P ⁺ diffusion region p21. The ground terminal GND is connected to the N ⁺ diffusion regions n12 and n22 and the P ⁺ diffusion region p31. Further, the point A is the conductive layer c1.
1, c12 and P ⁺ diffusion region p22, N ⁺ diffusion region n21
At the point B is the conductive layers c13 and c14 and the P ⁺ diffusion region p1.
2, N ⁺ diffusion region n11.

[0025] Conventional flip-flop, N ^- this by respectively adjacent to the source of the two PchMOS transistor formed in the well N ^- 2 for potential fixation of wells
Since the N ⁺ diffusion regions are formed, a current flows in the N ^- well when different potentials are applied to the two N ⁺ diffusion regions. However, in the flip-flop having the vertical structure shown in FIG. 3, the P ⁺ diffusion region p21 which is the source of the PchMOS transistor 1b and the N ⁺ diffusion region n32 for fixing the potential of the N ⁻ well n1 are formed separately from each other. The power supply terminals V ₂ and V ₁ are connected. Therefore, N
^- current does not flow to the well n1.

Next, the reset operation of the memory cell shown in FIG. 1 will be described step by step. FIG. 4 is a diagram showing a reset operation of the memory cell shown in FIG. In addition, in FIG.
Forcibly changing the level at point A of the memory cell to the "L" level is defined as reset. FIG. 4 illustrates the operation when the level at the point A is the “H” level immediately before resetting. It should be noted that in FIG. 4 and FIG. 5, the symbol ◯ indicates that the MOS transistor is in the conductive state, and the symbol x indicates that it is in the cutoff state. (1) First, a relationship of = V _cc 'V _cc between' voltage V _cc supplied from the voltage V _cc and the power supply terminal V ₂ supplied from the power supply terminal V ₁ was in immediately before the reset operation. At this time, since the word line W is also in the non-selected state, the flip-flop formed by the inverter circuits 1 and 2 holds the "H" level at the point A and the "L" level at the point B,
It is in a stable state. (2) At this time, V _cc ′ = V _cc given to the source of the PchMOS transistor 2a of the inverter circuit 2
To the ground potential GND. As a result, the ground potential GND is the PchMOS in which the inverter circuit 2 is conducting.
It is output to the point A through the transistor 2a, and the point A becomes "L" level. Further, at this time, the Nch MOS transistor 1b of the inverter circuit 1 is cut off and the Pch
The MOS transistor 1a becomes conductive. As a result, the point B becomes "H" level. When point B becomes "H" level,
The PchMOS transistor 2a of the inverter circuit 2 is cut off, and the NchMOS transistor 2b is turned on. At this time, the point A remains at the "L" level. (3) Next, when V _cc ′ = V _cc is returned again, the outputs of the inverter circuits 1 and 2 do not change, and the flip-flop formed by the inverter circuits 1 and 2 becomes stable.

Next, the case where the level at the point A is the "L" level immediately before the reset will be described. FIG. 5 sequentially explains the reset operation of the memory cell shown in FIG. 1 in this case. (1) First, immediately before the reset operation, since V _cc ′ = V _cc and the word line W is also in the non-selected state, the flip-flop formed by the inverter circuits 1 and 2 has the “L” level at point A, Holds "H" level at point B,
It is in a stable state. (2) At this time, V _cc ′ = V _cc given to the source of the PchMOS transistor 2a of the inverter circuit 2
To the ground potential GND. However, the inverter circuit 2
The PchMOS transistor 2a of the
Since the chMOS transistor 2b is conductive, the point A becomes the same "L" level as immediately before the reset. Therefore, at this time, the states of the PchMOS transistor 1a and the NchMOS transistor 1b of the inverter circuit 1 do not change. As a result, the point B becomes the same "H" level as immediately before the reset. (3) Next, returning again to V _cc '= V _cc. However, since the PchMOS transistor 2a of the inverter circuit 2 is cut off and the NchMOS transistor 2b is conductive, the levels at points A and B do not change, and the flip-flop becomes stable.

As described above, in the memory cell shown in FIG.
Regardless of the levels at points A and B immediately before resetting, the level at point A can be set to "L" level after resetting.

As described above, according to the first embodiment, the inverter circuit 1 and Pc composed of the PchMOS transistor 1a and the NchMOS transistor 2b are provided.
In the memory cell 11a configured by connecting the inverter circuit 2 configured by the hMOS transistor 2a and the NchMOS transistor 2b in a loop manner, the PchMOS transistor 1a and the PchMO transistor are operated during normal operation.
The power supply voltages _Vcc and _Vcc 'applied to the source of the S-transistor 2a have a relationship of _Vcc ' = _Vcc , and the power supply voltage _Vcc applied to the source of the PchMOS transistor 2a when the memory cell 11a is reset. ′ = V _cc is changed to the GND potential. Therefore, the power supply current I
_The content stored in the memory cell 11a is set to "0" without flowing _cc.
Can be reset to.

In the first embodiment, the example in which the memory cell of the 4-transistor structure of the CMOS structure is formed on the P ^- substrate is shown, but the same effect can be obtained by the memory cell formed on the N ^- substrate. Can be obtained. FIG. 6 is a circuit diagram of an SRAM memory cell showing a second embodiment of the present invention. As shown in the figure, the PchM of the inverter circuit 1 is
OS transistor 1a, PchMO of inverter circuit 3
The S transistor 3a is connected to the power supply terminal V ₁ .
In addition, the NchMOS transistor 1 of the inverter circuit 1
The source of b is connected to the ground terminal G ₁ and Nc of the inverter circuit 3
The source of the hMOS transistor 3b is connected to the ground terminal G ₂ . In the case of this memory cell, A of the memory cell
Forcibly changing the level of a point to the “H” level is defined as reset.

FIG. 7 is a sectional view showing an example of a vertical structure formed in the N ⁺ substrate of the memory cell shown in FIG. Since this vertical structure has the same structure as the memory cell formed in the P ⁺ substrate shown in FIG. 2, description thereof will be omitted.

FIG. 8 is a sectional view showing another example of the vertical structure formed in the N ⁺ substrate of the memory cell shown in FIG. Since this vertical structure has the same structure as the memory cell formed in the P ⁺ substrate shown in FIG. 2, description thereof will be omitted.

As described above, according to the second embodiment, the inverter circuit 1 and Pc composed of the PchMOS transistor 1a and the NchMOS transistor 2b are provided.
In the memory cell 11b configured by connecting the inverter circuit 3 configured by the hMOS transistor 3a and the NchMOS transistor 3b in a loop manner, the NchMOS transistor 1b and the NchMO transistor 1b are operated during normal operation.
Ground voltage GN applied to the source of the S transistor 3b
D and GND 'have a relationship of GND' = GND, and the ground voltage GND '= applied to the source of the NchMOS transistor 3a when the memory cell 11b is reset.
GND is changed to the power supply voltage _Vcc . Therefore,
The stored content of the memory cell 11a can be reset to "1" without flowing the power supply current _Icc .

In the first and second embodiments, the example in which the memory cell is composed of four transistors has been shown. However, the load device of the memory cell may have another structure. It is not limited to those shown in FIGS. 1 and 6. FIG. 9 is a circuit diagram showing the structure of the memory cell in this case, and a load device may be a resistor or a MOS transistor. Thus, by separating the power supply terminal of one of the logic elements forming the memory cell from the power supply terminal of the other logic element, the same effect can be obtained in any type of memory cell. ..

At the time of resetting the memory cell, in the memory cell shown in FIG. 1, the power source of one logic element is _Vcc '=
_Vcc → GND → _Vcc, and in the memory cell shown in FIG. 6, the power supply for one logic element is GND ′ = GND → _Vcc.
→ I am changing it to GND. However, it is not always necessary to change the power supply of one of the logic elements of the memory cell to GND or V _cc at the time of reset, and the voltage of V _cc ′ or G is set to a voltage at which the output of the flip-flop in the memory cell is inverted.
It is sufficient to change ND '.

[0036]

As described above, according to the present invention, in a semiconductor memory device having a memory cell composed of a flip-flop composed of first and second logic elements,
The memory cell has a high-potential power supply and a low-potential power supply provided to the first logic element, and a high-potential power supply and a low-potential power supply provided to the second logic element. Since one of the potential power supply and the low potential power supply is supplied from another terminal, the power supply can be changed by changing one of the high potential power supply or the low potential power supply supplied to one of the first and second logic elements to the other. There is an effect that the memory cell can be reset without consuming current.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory cell of an SRAM showing an embodiment of the present invention.

2 is a cross-sectional view showing an example of a vertical structure of a semiconductor of the SRAM shown in FIG.

3 is a cross-sectional view showing another example of the vertical structure of the semiconductor of the SRAM shown in FIG.

FIG. 4 is a diagram showing an operation of the SRAM shown in FIG.

5 is a diagram showing an operation of the SRAM shown in FIG. 1. FIG.

FIG. 6 is a circuit diagram of a SRAM memory cell showing a second embodiment of the present invention.

7 is a cross-sectional view showing a vertical structure of a semiconductor of the SRAM shown in FIG.

8 is a cross-sectional view showing a vertical structure of a semiconductor of the SRAM shown in FIG.

FIG. 9 is a circuit diagram of an SRAM memory cell showing another configuration of the present invention.

FIG. 10 is a circuit diagram showing a structure of a conventional SRAM.

11 is a circuit diagram showing an operation at reset of the SRAM shown in FIG.

[Explanation of symbols]

 1, 2, 4, 5 Inverter circuit 1a, 2a, 4a, 5a PchMOS transistor 1b, 2b, 4b, 5b NchMOS transistor

Claims (4)

[Claims] 1. A semiconductor memory device having a memory cell composed of a flip-flop composed of first and second logic elements to which a high potential power source and a low potential power source are applied, wherein the high potential power source and the low potential power source are provided. A semiconductor memory device characterized in that one of the two is applied to the first and second logic elements from different terminals, respectively. 2. The first and second logic elements are respectively constituted by first and second CMOS inverter circuits each of which is composed of a first conductivity type MOS transistor and a second conductivity type MOS transistor. Semiconductor memory device. 3. The first-conductivity-type MOS transistor and the second transistor, which constitute the first CMOS inverter circuit,
3. The MOS transistor of the first conductivity type, which constitutes the CMOS inverter circuit of claim 1, is formed in each of two wells of the second conductivity type which are separately formed in the substrate of the first conductivity type. Semiconductor memory device. 4. Two MOS transistors of the first conductivity type, which form the first and second CMOS inverter circuits, are formed in one well of the second conductivity type in a substrate of the first conductivity type. 3. The semiconductor memory device according to claim 2, wherein only one of the separate terminals is connected to the well.