JPH0573830B2 - - Google Patents

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Publication number
JPH0573830B2
JPH0573830B2 JP14526783A JP14526783A JPH0573830B2 JP H0573830 B2 JPH0573830 B2 JP H0573830B2 JP 14526783 A JP14526783 A JP 14526783A JP 14526783 A JP14526783 A JP 14526783A JP H0573830 B2 JPH0573830 B2 JP H0573830B2
Authority
JP
Japan
Prior art keywords
reactive gas
film
temperature
reduced pressure
polysilane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14526783A
Other languages
Japanese (ja)
Other versions
JPS6036662A (en
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP14526783A priority Critical patent/JPS6036662A/en
Publication of JPS6036662A publication Critical patent/JPS6036662A/en
Publication of JPH0573830B2 publication Critical patent/JPH0573830B2/ja
Granted legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24Deposition of silicon only

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  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)

Description

【発明の詳細な説明】 この発明は、低温減圧気相法(LT CVD法と
いう)によりポリシランを主成分とする被膜を作
製する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for producing a film containing polysilane as a main component by a low temperature reduced pressure vapor phase method (referred to as LT CVD method).

この発明は反応性気体のポリシランを370〜650
℃の温度に加熱し、分解するとともに、被形成面
を150〜350℃の温度に保持することにより、水素
が再結合中心中和剤として添加されたアモルフア
ス構造を含む珪素を主成分とする非単結晶半導体
を作製する方法に関する。
This invention uses polysilane as a reactive gas at 370 to 650
By heating the surface to a temperature of 150°C and decomposing it, and keeping the surface on which it is formed at a temperature of 150 to 350°C, a silicon-based non-containing material containing an amorphous structure with hydrogen added as a recombination center neutralizing agent is produced. The present invention relates to a method for manufacturing a single crystal semiconductor.

この発明はモノシランを含むシランの反応性気
体を用いてLT CVDを行うに際し、同時に300n
m以下の波長の紫外光を被形成面または反応性気
体に照射することにより、反応性気体を高密度化
し、さらにその被膜形成速度を大きくすることを
特徴としている。即ち、光CVD法とLT CVD法
とを併用することを特徴としている。
This invention is a method for performing LT CVD using a reactive gas of silane including monosilane.
The method is characterized in that by irradiating the surface to be formed or the reactive gas with ultraviolet light having a wavelength of less than m, the density of the reactive gas is increased and the rate of film formation is increased. That is, it is characterized by the combined use of the optical CVD method and the LT CVD method.

この発明は、プラズマCVD法を用いた場合に
観察される被膜形成表面をスパツタ(損傷)する
ことなく、加えて実質的な被膜成長速度を高速度
化せしめることを特徴としている。
The present invention is characterized in that it does not cause spatter (damage) on the surface on which the film is formed, which is observed when using the plasma CVD method, and in addition, it increases the substantial growth rate of the film.

従来、減圧気相法(以下CVD法という)は、
反応炉内を減圧下とし、被形成面を有する基板が
最も温度が高く、反応性気体の温度がそれに比べ
て等しいまたは低い方法であつた。
Conventionally, the reduced pressure vapor phase method (hereinafter referred to as CVD method)
In this method, the inside of the reactor was kept under reduced pressure, the substrate having the surface to be formed had the highest temperature, and the temperature of the reactive gas was equal to or lower than that.

その一例として、本発明人による発明(特公昭
51−1389多結晶半導体被膜の形成方法、特公昭57
−49133半導体被膜の形成方法、特公昭53−14518
窒化珪素被膜の作製方法、特公昭53−33667半導
体装置作製方法、特公昭56−52877酸化珪素被膜
の作製方法)が知られている。
As an example, an invention by the present inventor (Tokuko Sho
51-1389 Method of forming polycrystalline semiconductor film, Special Publication 1987
-49133 Method of forming semiconductor film, Special Publication No. 53-14518
A method for manufacturing a silicon nitride film, a method for manufacturing a semiconductor device in Japanese Patent Publication No. 53-33667, and a method for manufacturing a silicon oxide film in Japanese Patent Publication No. 56-52877 are known.

しかし本発明方法はこれらとは逆に、被形成面
の温度が反応性気体の温度に比べて低い温度とし
ていることを特徴とする低温気相反応方法に関す
る。さらに本発明は反応性気体として、ポリシラ
ンを用いたLT CVD法またはシランを用いた光
エネルギ併用のLT CVD法を特徴とし、その結
果、被形成面の温度を150〜350℃とすることによ
り形成される半導体被膜中には1〜15atom%の
濃度に水素が添加されていることをその構成要件
とし、半導体被膜の形成に関し、被形成面をスパ
ツタ(損傷)させることなく、50Å/分以上の高
い被膜成長速度を得たものである。
However, the method of the present invention, on the contrary, relates to a low-temperature gas phase reaction method characterized in that the temperature of the surface to be formed is lower than the temperature of the reactive gas. Furthermore, the present invention is characterized by the LT CVD method using polysilane as a reactive gas or the LT CVD method using silane in combination with light energy. The constituent requirement is that hydrogen be added to the semiconductor film at a concentration of 1 to 15 atom%, and the semiconductor film can be formed at a rate of 50 Å/min or more without sputtering (damaging) the surface to be formed. A high film growth rate was obtained.

以下に図面に従つて本発明を記す。 The present invention will be described below with reference to the drawings.

第1図は本発明に用いられた横型CVD装置の
概要を示す。
FIG. 1 shows an outline of the horizontal CVD apparatus used in the present invention.

図面において、反応系10は石英反応炉2、
300nm以下の波長の光、例えば185nm、254nm
の光エネルギを供給する水銀灯9、反応性気体を
加熱する外部加熱を行う抵抗加熱炉3、被膜が石
英上にコートされないようにする油膜48、被形
成面を有する基板1、基板ホルダ4、ホルダの温
度を所定の温度とする冷却媒体の供給源5、流量
計6、ノズル8にて作製した。
In the drawing, the reaction system 10 includes a quartz reactor 2,
Light with a wavelength of 300nm or less, e.g. 185nm, 254nm
a mercury lamp 9 that supplies light energy, a resistance heating furnace 3 that performs external heating to heat a reactive gas, an oil film 48 that prevents a film from being coated on quartz, a substrate 1 having a surface to be formed, a substrate holder 4, and a holder. A cooling medium supply source 5, a flow meter 6, and a nozzle 8 were used to set the temperature to a predetermined temperature.

基板1を所定の温度150〜350℃に冷却した後、
真空ポンプ7にて外部に放出している。
After cooling the substrate 1 to a predetermined temperature of 150 to 350°C,
It is discharged to the outside by a vacuum pump 7.

この図面では冷却媒体として窒素を用いた。ガ
ス系20は26よりポリシラン(主成分をジシラ
ン〔Si2H6〕とする)またはシラン一般にはモノ
シラン(SiH4)を流量計29、バルブ28を経
て加えた。またキヤリアガスまたはパージ用ガス
である水素を27より供給した。
In this drawing, nitrogen was used as the cooling medium. To the gas system 20, polysilane (the main component is disilane [Si 2 H 6 ]) or silane, generally monosilane (SiH 4 ), was added through a flow meter 29 and a valve 28 . Further, hydrogen as a carrier gas or purge gas was supplied from 27.

排気系30はバルブ13を経て真空ポンプ12
により排気する。
The exhaust system 30 is connected to the vacuum pump 12 via the valve 13.
Exhaust by.

第2図は第1図の反応炉でLT CVD法にて作
製した場合の被膜成長速度を示す。
Figure 2 shows the growth rate of a film produced by the LT CVD method in the reactor shown in Figure 1.

図面において、被膜面の温度と被膜成長速度と
の関係を示す。曲線15は空間の温度370℃、さ
らに500℃16、570℃17、650℃18をそれぞ
れ有している。この場合ジシランは5c.c./分であ
り、圧力は160torr以下の減圧下ここでは10〜
0.5torr特に2torrとした。これをジシランではな
くモノシラン(SiH4)を用いると、曲線14が
得られるのみであつた。実用上の被膜成長速度
(50Å/分以上)を水素を含有する400℃以下、好
ましくは350〜150℃の温度で有せしめることは不
可能であつた。
In the drawing, the relationship between the temperature of the coating surface and the coating growth rate is shown. Curve 15 has a space temperature of 370°C, 500°C 16, 570°C 17, and 650°C 18, respectively. In this case, the disilane is 5 c.c./min, and the pressure is 10 ~
0.5torr, especially 2torr. When monosilane (SiH 4 ) was used instead of disilane, only curve 14 was obtained. It has been impossible to achieve a practical film growth rate (more than 50 Å/min) at temperatures below 400°C, preferably from 350 to 150°C, containing hydrogen.

他方、本発明に示されるごとく、ポリシランを
用いることは、被膜成長速度を50Å/分〜150
Å/分と実用上可能な範囲で行うことができ、き
わめて有効であることが判明した。
On the other hand, as shown in the present invention, using polysilane increases the film growth rate from 50 Å/min to 150 Å/min.
It has been found that the process can be carried out within a practically possible range of Å/min, and is extremely effective.

第2図において、反応空間の温度をそれぞれ
650℃(曲線18)、570℃(曲線17)、470℃
(曲線16)、370℃(曲線15)として各曲線が
得られた。
In Figure 2, the temperature of the reaction space is
650℃ (curve 18), 570℃ (curve 17), 470℃
(Curve 16) and 370°C (Curve 15).

さらに被形成面の温度を150℃以下とすると、
形成されるものが被膜に加えてフレークが混在し
て、実用上半導体の特性を得ることができなかつ
た。かかる反応温度に対し、300nm以下の波長
を有する紫外光(5〜500mW/cm2例えば250m
W/cm2)を照射して、フオトLT CVDとして実
施した。すると被膜成長速度をモノシランを用い
た場合でも曲線14より曲線24にさらに向上さ
せることができた。さらに重要なことは、形成さ
れた被膜の電気特性に見られる。即ち、第1図に
示すごとく、紫外光(254nm、185nm)を照射
すると、そのシリコン膜の不純物を添加していな
い場合であつても、AM1(100mW/cm2)にて8
×104(Ωcm)-1、暗伝導度3×1011(Ωcm)-1を得る
ことができた。紫外光を照射しない場合は、1×
104(Ωcm)-1と1×1010(Ωcm)-1であつた。即ちフ
オトセンシテイビテイを1桁以上向上させること
が判明した。
Furthermore, if the temperature of the surface to be formed is 150℃ or less,
What was formed was a mixture of flakes in addition to the film, making it impossible to obtain semiconductor characteristics in practice. For such a reaction temperature, ultraviolet light having a wavelength of 300 nm or less (5 to 500 mW/cm2, e.g. 250 mW/cm 2
W/cm 2 ) and carried out as PhotoLT CVD. As a result, even when monosilane was used, the film growth rate could be further improved from curve 14 to curve 24. What is more important is the electrical properties of the formed film. That is, as shown in Fig. 1, when ultraviolet light (254 nm, 185 nm) is irradiated, even if the silicon film is not doped with impurities, the power of AM1 (100 mW/cm 2 ) is 8.
×10 4 (Ωcm) -1 and dark conductivity of 3 × 10 11 (Ωcm) -1 were obtained. When not irradiating ultraviolet light, use 1×
10 4 (Ωcm) -1 and 1×10 10 (Ωcm) -1 . That is, it has been found that the photosensitivity can be improved by one order of magnitude or more.

これを紫外光を併用してポリシランの反応性気
体とする場合も6桁のフオトセンシテイビテイを
得ることができた。
When this was used in combination with ultraviolet light to form a reactive gas for polysilane, a six-digit photosensitivity could be obtained.

本発明方法において、その不純物の含有量を
SIMS(カメラ社製3F型)およびFTIR(フーリエ
型赤外線分量器)で調べると、その中にある酸素
は5×1017cm-3以下であり、炭素は5×1017cm-3
以下であつた。これは本発明方法においては、不
純物として水または炭化水素がかかる温度でジシ
ランと反応せず、結果としてその反応生成物とし
ての酸化珪素、炭化珪素を被膜中に取り込まない
ためと推定される。
In the method of the present invention, the content of impurities is
When examined using SIMS (3F model manufactured by Camera Company) and FTIR (Fourier infrared spectroscopy), the amount of oxygen in it is less than 5×10 17 cm -3 and the amount of carbon is 5×10 17 cm -3
It was below. This is presumed to be because, in the method of the present invention, water or hydrocarbons as impurities do not react with disilane at such temperatures, and as a result, silicon oxide and silicon carbide as reaction products are not incorporated into the film.

このことはPCVD法(プラズマ気相反応法)と
比べた場合、その不純物混入の程度が一般には1
〜20×1019cm-3であることを考えると、出発材料
の純度に対し、工業的な余裕を有せしめることが
できることが判明した。
This means that when compared to the PCVD method (plasma vapor phase reaction method), the degree of impurity contamination is generally 1
Considering that it is ~20×10 19 cm −3 , it has been found that an industrial margin can be given to the purity of the starting material.

また紫外光を照射した場合、反応性気体がモノ
シランであつても、その被膜成長速度が第2図曲
線14より曲線24に変成することが可能となつ
た。このため、光エネルギは1KW出力(基板面
積2×20cm2(40cm2)250mW/cm2)であつた。
Furthermore, when ultraviolet light was irradiated, even if the reactive gas was monosilane, the film growth rate could be changed from curve 14 in FIG. 2 to curve 24. Therefore, the light energy was 1 KW output (250 mW/cm 2 for a substrate area of 2×20 cm 2 (40 cm 2 )).

水銀励起法を用いることなく、シランを分解す
ることが370〜650℃の温度の熱エネルギを併用す
ることにより可能となつたことは、きわめて工業
的効果が大きい。特にポリシランは1g当たり1
万〜2万円するに対し、モノシランは1g当たり
100〜130円であることを考えると、反応に光エネ
ルギを必要としても工業的採算ベースにのるもの
と推定される。
The fact that it has become possible to decompose silane without using mercury excitation by using thermal energy at a temperature of 370 to 650°C has an extremely large industrial effect. In particular, polysilane has a
Whereas monosilane costs 10,000 to 20,000 yen per gram.
Considering that the price is 100 to 130 yen, it is estimated that even if light energy is required for the reaction, it will be commercially viable.

また本発明方法において、反応性気体として
LT CVD法においては、ポリシランを用いたこ
と、または光エネルギを併用してLT CVD法に
おいてはモノシランまたはポリシランを用いたこ
とを特徴としている。しかしかかる本発明方法を
実施する際これらは価または価の不純物であ
るジボランまたはフオスヒンを同時に添加したP
またはN型の水素の添加されたシリコン半導体を
形成してもよい。
In addition, in the method of the present invention, as a reactive gas
The LT CVD method is characterized by the use of polysilane, or the combination of light energy and the use of monosilane or polysilane in the LT CVD method. However, when carrying out the method of the present invention, these are P containing simultaneously added diborane or phosphin as a valence or valence impurity.
Alternatively, an N-type hydrogen-doped silicon semiconductor may be formed.

本発明において、8μ以上の遠赤外特にSi−Hの
共鳴吸収が起きる10〜13μの波長において0.1〜
1W/cmの光エネルギを加えることも紫外光照射
と同様に有効である。
In the present invention, in far infrared rays of 8μ or more, especially at wavelengths of 10 to 13μ where Si-H resonance absorption occurs,
Adding light energy of 1 W/cm is also effective, as is ultraviolet light irradiation.

さらにシリコン半導体の添加物としてフオスヒ
ン、メタン、ゲルマンに添加して、SixC1-x(0<
x<1)、Si3N4-x(0<x<4)、SixGe1-x(0<
x<1)を作ることは可能である。
Furthermore, by adding phosphin, methane, and germane as additives to silicon semiconductors, Si x C 1-x (0<
x<1), Si 3 N 4-x (0<x<4), Si x Ge 1-x (0<
x<1).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に用いた装置の概要を示す。第
2図は本発明方法で得られた被膜成長速度の特性
を示す。
FIG. 1 shows an outline of the apparatus used in the present invention. FIG. 2 shows the characteristics of the film growth rate obtained by the method of the present invention.

Claims (1)

【特許請求の範囲】 1 減圧下にポリシランを主成分とする反応性気
体を導入し、被形成面に水素が添加された非単結
晶珪素を主成分とする被膜を作製するに際し、前
記反応性気体のポリシランを370〜650℃の温度に
加熱するとともに、前記被膜表面は150〜350℃に
保持させたことを特徴とする減圧気相法。 2 減圧下にシランを主成分とする反応性気体を
導入し、被形成面に水素が添加された非単結晶珪
素を主成分とする被膜を作製するに際し、前記反
応性気体のシランを370〜650℃の温度に加熱する
とともに、前記被膜表面は150〜350℃に保持さ
せ、さらに加えて300nm以下の波長の紫外光ま
たは8μ以上の遠赤外光の光エネルギを被形成面
または反応性気体に照射することを特徴とする減
圧気相法。
[Scope of Claims] 1. When a reactive gas containing polysilane as a main component is introduced under reduced pressure to produce a film containing hydrogen as a main component and non-single-crystal silicon added to the surface to be formed, the reactive gas is A reduced pressure vapor phase method characterized in that gaseous polysilane is heated to a temperature of 370 to 650°C, and the surface of the coating is maintained at 150 to 350°C. 2. When introducing a reactive gas mainly composed of silane under reduced pressure and producing a film mainly composed of non-single crystal silicon to which hydrogen has been added to the surface to be formed, the reactive gas silane is While heating to a temperature of 650°C, the coating surface is maintained at 150 to 350°C, and in addition, optical energy of ultraviolet light with a wavelength of 300 nm or less or far infrared light with a wavelength of 8 μ or more is applied to the surface to be formed or the reactive gas. A reduced pressure vapor phase method characterized by irradiation.
JP14526783A 1983-08-08 1983-08-08 Vapor phase method under reduced pressure Granted JPS6036662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14526783A JPS6036662A (en) 1983-08-08 1983-08-08 Vapor phase method under reduced pressure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14526783A JPS6036662A (en) 1983-08-08 1983-08-08 Vapor phase method under reduced pressure

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP24679194A Division JP2511808B2 (en) 1994-09-16 1994-09-16 Depressurized gas phase method

Publications (2)

Publication Number Publication Date
JPS6036662A JPS6036662A (en) 1985-02-25
JPH0573830B2 true JPH0573830B2 (en) 1993-10-15

Family

ID=15381173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14526783A Granted JPS6036662A (en) 1983-08-08 1983-08-08 Vapor phase method under reduced pressure

Country Status (1)

Country Link
JP (1) JPS6036662A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614257A (en) * 1991-08-09 1997-03-25 Applied Materials, Inc Low temperature, high pressure silicon deposition method
JP3121131B2 (en) * 1991-08-09 2000-12-25 アプライド マテリアルズ インコーポレイテッド Low temperature and high pressure silicon deposition method
US9837271B2 (en) 2014-07-18 2017-12-05 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US9443730B2 (en) 2014-07-18 2016-09-13 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US10460932B2 (en) 2017-03-31 2019-10-29 Asm Ip Holding B.V. Semiconductor device with amorphous silicon filled gaps and methods for forming

Also Published As

Publication number Publication date
JPS6036662A (en) 1985-02-25

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