JPH0573607A - Vector instruction generation processing method - Google Patents

Abstract

PURPOSE:To efficiently generate a vectoring parallel processing program on a compiler processing in a computer. CONSTITUTION:In the processing of the computer generating a target program having vector instruction strings which are parallel-processed from a prescribed source program, the vector instruction strings are generated as a single processing on the necessary part of the source program in the first processing step 1. In the second processing step 2, the vector instruction strings are copied, they are set to be the vector instruction strings of the necessary number of parallel processings, data being a processing object is divided and they are distributed into the vector instruction strings of the number of the parallel processings. The operands of the respective vector instruction strings are altered to operands corresponding to distributed data so as to make the parallel processing program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector instruction generation processing method for generating a vectorized parallel processing program so that a plurality of vector processing devices can perform parallel processing in the program generation processing of a computer.

[0002]

2. Description of the Related Art In the processing of an automatic parallelizing compiler for generating a parallelized object program from a source program, a program portion forming a loop by a so-called loop slice method. Is divided into a plurality of loops, and a plurality of processing devices execute each loop in parallel.

That is, in the loop slice method, as shown in FIG.
If there is a loop that repeats from 1 to N, it is divided into, for example, two loops, a loop from 1 to N / 2 and a loop from N / 2 + 1 to N.

In this case, since the parallelization causes a change in the processing order as compared with the case of the single sequential processing,
Prior to parallelization, known so-called data dependency analysis processing is performed, and checks and necessary measures are performed.

In the data dependency analysis process, a change in the processing order causes a contradiction with the original program logic (the order is changed so that the reference is made before the update although the update content should be referred). If there is no contradiction, or if there is no contradiction, the slicing process is performed as described above.

Further, in the processing of a so-called automatic vectorizing compiler for generating a vector instruction string to be executed by a so-called vector processing device, each innermost loop of the source program is replaced with a loop, as is well known. It can be replaced by a sequence of vector instructions.

Therefore, as shown in FIG. 5, by processing each loop divided by the loop slice by the automatic vectorizing compiler, a vectorizing program for parallel processing by a plurality of vector processing devices can be generated.

However, this automatic vectorization process requires a relatively large amount of translation time, and according to the above method, when parallelization and vectorization are performed, the vectorization process time is further increased by the parallel number. Doubled, greatly increasing compiler processing time.

An object of the present invention is to provide a vector instruction generation processing method capable of efficiently generating a vectorized parallel processing program.

[0010]

FIG. 1 is a block diagram showing the configuration of the present invention. The figure shows a configuration of a vector instruction generation processing method, which is processing of a computer that generates a target program having a vector instruction sequence that has been parallelized from a predetermined source program.

In the first processing stage 1, a vector instruction sequence is generated as a single process for the required part of the source program. In the second processing stage 2, the vector instruction sequence is copied into a required number of parallel processing vector instruction sequences, and the data to be processed is divided and distributed to the parallel instruction vector instruction sequences. The operands of the vector instruction sequence are changed to the operands corresponding to the distributed data, respectively, to form a parallel processing program.

[0012]

According to the processing method of the present invention, automatic vectorization processing requiring a relatively long translation time is integrated into one time regardless of the parallel processing number, and then the vectorization program is copied into the parallel processing number, Since the parallel processing program is generated by replacing the operands with required values, the generation processing time of the vectorized parallel processing program can be significantly reduced.

[0013]

FIG. 2 is a diagram showing the flow of processing of an embodiment of the present invention. In the processing stage 1, first, in the processing step 10, automatic vectorization processing is performed to perform vectorization of a single sequential processing, Generate a vector instruction sequence.

Next, in processing step 11, data dependency relationship analysis processing is performed on this vector instruction sequence to obtain the above-described meaning dependency relationship for the data appearing in the vector operation range.

In the processing step 12, the vector instruction is inspected based on the result of the data dependency, etc., and the non-parallelizable parts are grouped into the smallest possible parts so that the parallelizable parts are enlarged. If the same data is accessed during parallel processing, the position for inserting the necessary instruction for synchronization and exclusive control is designated.

When the parallelized vector instruction sequence is obtained as identified in the processing step 13, the vector instruction sequence and necessary control information are passed to the second processing stage. In processing step 14, the vector instruction string of the parallelizable portion is copied so that the predetermined parallel number is obtained.

At processing step 15, the contents of the operands of the copied vector instruction are replaced so that the data is divided and assigned to each parallel processing. In processing step 16, corresponding instructions for the synchronous processing and the exclusive control processing are inserted at designated positions in correspondence with the data to be shared, and in processing step 17, parallel processing is performed before and after each parallel processing part. Add start and end procedures.

FIG. 3 and FIG. 4 are diagrams for explaining the above processing for a program example, FIG. 3 (a) is an example of a loop of the source program, and FIG. 3 (b) is a representation of it closer to the target program. It is a so-called intermediate representation program converted into intermediate instructions. Note that, etc. in the figure show the correspondence between both programs.

FIG. 3C shows a result of separating the non-vectorizable portion and converting the other vectorizable portions into a vector instruction sequence by a known vectorization process in the program of FIG. 3B. ..

In FIG. 3 (c), "SVCT" and "EVCT" are instructions inserted to indicate the start and end of the vector operation, respectively, and "VSUM" is a vector instruction for performing the sum operation. , "VRC" is a vector instruction of linear regression operation, and like "VLOAD", etc., vector instructions are those prefixed with "V", such as "LOAD" which is indicated by the name following V for vector data. It represents the instruction to be executed.

In the operand of each vector instruction, the one expressed as "A (1: N)" is an operand for indicating vector data. In this example, vector data A (1) to A (N ).

Note that the portions (1) and (2) cannot be vectorized simply due to the data dependence, so they are vectorized by a special conversion process. As described above, regarding the result of vectorization in the case of single processing, the part which cannot be parallelized is separated and the part which can be parallelized is copied according to the result of the data dependency analysis. Parallel processing is performed, operands are replaced, synchronization and exclusive control are added, and the instruction sequence of FIG. 4 is generated.

In FIG. 4, "SMUTEX" and "EMUTEX" inserted in the part of are instructions for starting and ending the exclusive control, and the values are assigned to the same variable SUM in both parallel processes. , Exclusive control is required.

In the other part, "POST" inserted in the processing on the left side and "WAIT" on the right side are synchronous control instructions, and load to the array data E by the processing on the left side (VLOAD immediately before POST Command), store E by processing on the right
Synchronize because it must be executed before (VSTORE instruction immediately after WAIT).

The method of the present invention is particularly effective in the case of a single loop. For the multiple loop part, the innermost loop is first vectorized, and then the loop slice method is applied to the outer loop. ..

[0026]

As is apparent from the above description, according to the present invention, there is a remarkable industrial effect that the vectorized parallel processing program can be efficiently generated in the compiler processing of the computer.

[Brief description of drawings]

FIG. 1 is a process flow chart showing the configuration of the present invention.

FIG. 2 is a process flow chart of an embodiment of the present invention.

FIG. 3 is a diagram illustrating a program example.

FIG. 4 is a diagram illustrating a program example.

FIG. 5 is a diagram illustrating an example of a loop slice.

[Explanation of symbols]

 1 First processing stage 2 Second processing stage 10 to 17 processing steps

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideki Nozaki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

[Claims] 1. A process of a computer for generating an object program having a vector instruction sequence parallelized from a predetermined source program, wherein a vector instruction sequence is generated as a single process for a required part of the source program (1 ), Copying the vector instruction sequence into a vector instruction sequence of the required number of parallel processes, dividing the data to be processed, and allocating to the vector instruction sequence of the parallel process number, and the operand of each vector instruction sequence Is configured as a parallel processing program by changing the operands corresponding to the distributed data respectively (2).