JPH0235349B2 - RUUPUNAIHAIRETSUSHORIBEKUTORUKASHORIHOSHIKI - Google Patents

Description

[Detailed Description of the Invention] (A) Technical Field of the Invention The present invention relates to an in-loop array processing vectorization processing method, particularly for converting a high-level language using arrays into machine language executed on a vector processing device. The present invention relates to an in-loop array processing vectorization processing method that promotes vectorization that speeds up the execution of conversion results.

(B) Technical Background and Problems When common processing procedures are applied to multiple pieces of data, so-called vector processing devices are used that execute the procedures in parallel. for example,
When creating a program in a high-level language such as FORTRAN, the program creator does not need to be aware that the program will be executed by a vector processing device; the program creator converts the high-level language into machine language. When converting, the so-called compiler,
Generate vector instructions for what is possible. The more things that can be converted into vector instructions, the faster the execution will be due to parallel processing.

FIG. 1 is an explanatory diagram of general vector instruction generation, and FIG. 2 is an explanatory diagram of problems in the prior art.

For example, in the translated command group 4 input from the card reader 1, the high-level language sentence instructs to repeat the command sentences up to the sentence 10 times while changing the control variable i from 1 to 10. . The statement indicates that the sum of the data in array B and the data in array C should be stored in array A. control variable i
are used as subscripts of arrays A, B, and C. When expanding the translated instruction group 4 into machine language, the translation processing device 2 considers the intermediate representation 5 as shown in the figure, and Machine language instructions as shown in machine language instruction group 6 are generated. The instruction is a vector instruction that loads the data of array B into the 0th vector register. The instruction is an instruction that loads the data of array C into the first vector register.
The instruction is an instruction to store the sum of the 0th vector register and the first vector register in the second vector register. The instruction is an instruction to store the contents of the second vector register into array A.
These instructions are actually given in binary code. The translation processing device 2 generates a machine language instruction group 6 and stores it in the magnetic disk device 3, for example.
By expanding into vector instructions like this,
Normally, the process should be repeated 10 times, but
It can be executed in one parallel process.

The vectorization process shown in FIG. 1 is not always possible. For example, in the case of the translated instruction group 4 as shown in FIG. It becomes like this. However, if you convert it into a vector and process it, the result will be like array data 7-3, so
This will result in incorrect data. That is, in such a case, vectorization cannot be performed. This is because, in an array assignment statement, there is an overlapping relationship between the data groups indicated by the subscripts on the right and left sides. From this, conventionally, for example, in the case of the translated instruction group 4 shown in FIG. However, it is unclear what kind of relationship there is, and the overlapping relationship of the arrays cannot be recognized, so it was not possible to vectorize them.

(C) Object and structure of the invention The present invention aims to solve the above-mentioned problems, and by replacing variables in the subscript expression of the array in the loop with the definition expression of the variable that includes the control variable or constant of the loop, The purpose is to clarify the relationship between arrays, promote vectorization, and generate objects that can be executed at high speed. Therefore, the in-loop array processing vectorization processing method of the present invention is
In a translation processing device into machine language instructions in a vector processing device equipped with a vector unit that executes a vector instruction that processes multiple pieces of data in parallel, and a scalar unit that executes a scalar instruction that processes scalar data, A subscript scanning means that searches for a subscript of an array that appears in a group of translated instructions expressed in a form that is repeatedly executed and that includes a variable whose behavior is unknown, and a definition expression that searches for an expression that defines the variable whose behavior is unknown. a scanning means, and a subscript expression incorporating means for incorporating the definition content of the expression found by the definition expression scanning means into the subscript information in a form that replaces a variable whose operation is unknown in the subscript;
determining means for determining whether vectorization is possible by examining the operating range based on the new subscript information generated by the subscript expression incorporating means;
The present invention is characterized by comprising a vector instruction generation processing section that generates the vector instruction according to the determination result of the determination means. This will be explained below with reference to the drawings.

(D) Embodiments of the Invention Fig. 3 shows the configuration of an embodiment of the invention, Fig. 4 is an explanatory diagram of processing of an embodiment of the invention, and Fig. 5 shows an explanation of a specific processing mode of an embodiment of the invention. Show the diagram.

In FIG. 3, numerals 2 and 3 correspond to those in FIG. 1, 10 is a vector processing device, 11 is a vector unit, 12 is a scalar unit, 22 is a main storage device, 23 is a channel device, and 24 is an object processor. module, 25 is a source module, 30 is a parsing unit, 31 is a subscript scanning unit, 32
33 is a definition formula scanning unit, 33 is a subscript formula embedding unit, 34 is a vectorization possibility determining unit, 35 is a vector instruction generation unit, and 36 is a scalar instruction generation unit.

The translation processing device 2 is a device that fetches and executes sequential instructions, and inputs a source module 25 consisting of a group of instructions to be translated written in a high-level language such as FORTRAN, and converts it into binary machine language instructions. This is a device that converts the object module 24 and outputs it to, for example, the magnetic disk device 3.
The translation processing device 2 may be the same device as the vector processing device 10, or may be another processing device.

The vector processing device 10 is a device that processes normal scalar instructions and vector instructions that process multiple pieces of data simultaneously in parallel, and is composed of a vector unit 11 and a scalar unit 12. Scalar unit 12 is buffer storage 19
, a general-purpose register, a floating point register 20, and a scalar arithmetic unit 21. Data on a main memory 22 is loaded into the register 20, and the scalar arithmetic unit 21 sequentially processes scalar instructions. Vector unit 11 is activated when the instruction fetched from main memory 22 is a vector instruction. Multiple load/store pipeline 1
For example, it has 256 mask registers 14 consisting of 32 words x 1 bit and 256 vector registers 14' consisting of 32 words x 64 bits. The mask circuit 15 is, for example,
In order to include procedures that include IF statements in FORTRAN programs as vectorization targets, it indicates the data for which the condition is true. Addition/logic operator 16, multiplier 17 and divider 1
8 process data groups in the vector register 14' in parallel using vector instructions.
Since large amounts of data are processed simultaneously, high-speed data processing is possible. An object module 24 including a vector instruction or a load module edited therefrom is loaded in advance into the main storage device 22 via a channel device 23.

Due to the configuration of the vector processing device 10 as described above, it is desirable that as many vector instructions as possible be used as the instructions executed by the vector processing device 10, as long as the processing contents are the same. Therefore, the translation processing device 2 according to the present invention particularly has the following configuration.

The syntax analysis unit 30 analyzes the syntax of the source module 25 to be translated. The subscript scanning unit 31 performs a process of searching for variables in the subscript expression whose movements are unknown. Note that the subscript may be considered to indicate a position within an array consisting of a plurality of pieces of data. The subscript scanning unit 31 particularly processes variables other than the control variables of all loops including that statement among the subscripts of the array. Here the loop is for example FORTRAN's
A group of instructions that are repeatedly processed by DO statements,
A processing variable is a variable whose value depends on the number of repetitions of the loop.

The definition expression scanning unit 32 scans a definition expression indicating in advance by what kind of variable or constant the variable to be processed that has been found by the subscript scanning unit 31 is determined.
It executes the following search process from a predetermined range. The blocks to be scanned by the expression are the block where the variable to be processed appears, then the block that must be passed on the path to the block where the variable to be processed appears in the loop, and the block where the variable to be processed appears. This is the initialization block of the loop in which the variable to be processed appears. Note that a block is a processing unit of translation, and refers to a part where the flow of processing is uniquely determined.

The subscript expression incorporation section 33 performs processing of incorporating the expression found by the definition expression scanning section 32 into the subscript expression, and replacing the variable to be processed with another variable or constant. If the expression that defines the variable is an expression that contains only constants, if it is an expression that includes one of the control variables of the loop that includes the statement to be processed, or if the variable to be processed does not appear in the expression If so, perform the embedding. For example, if the control variables of a loop are i and J, and the assignment statement for array A is given as A(J)=A(i+K), then within the same block, variable K is given as K=J+10 If it is defined as A(J)=A(i+J+10), the above assignment statement is replaced by the subscript expression embedding unit 33 as A(J)=A(i+J+10).

The vectorization possibility determination unit 34 includes the subscript incorporation unit 3
After the embedding process in step 3 is completed, the subscript expressions appearing on the right and left sides of the array assignment expression are compared, and it is determined whether vectorization is possible depending on whether there is an overlapping relationship. If the array names are different, it is assumed that the parts do not overlap, but even if there is overlap in the assigned data, vector If the processing results are the same when processing by converting into vectors and when processing sequentially, it is determined that vectorization is possible.

The vector instruction generation unit 35 generates an object consisting of vector instructions for a sentence that the vectorization possibility determination unit 34 has determined can be vectorized, and the scalar instruction generation unit 36 generates an object consisting of a vector instruction for a sentence that cannot be vectorized. It executes the process of expanding into

With the above configuration, the translation processing device 2 performs processing as shown in FIG. 4, for example. Note that although the processing related to the present invention will be mainly described, other processing may be considered to be the same as the conventional processing. First, the fourth
Subscript information is created by the diagram illustrating process 40.
The subscript expression in the source is extracted. Next, in process 41, structural analysis is performed according to a predetermined grammar. Next, the process 43
to process 50 are repeated. Process 43 searches for variables in the subscript expression whose movement is unknown. If there is a subscript whose behavior is unknown, a process 44 searches for an expression that defines a variable used in the subscript to be processed in the same block B1. As a result of the determination in process 45, if it is found, the process moves to process 49. In process 46, the variable K to be processed appears
In the DO loop, search for defining expressions for blocks that must pass, such as B2 and B3. Since branching blocks B4 and B5 are not necessarily passed through, they are excluded from the search target. If it is found in process 47, the process moves to process 49. In process 48, a search is made to see if there is a definition expression outside the DO loop in which the variable to be processed appears, such as in initialization blocks B6 and B7.

In the judgment of process 49, if it is determined that the definition expression is not found, or if it is determined that even if it is found, it is determined that it does not match the built-in condition, the process returns to process 42 with the variable whose behavior is unknown as it is,
Move on to processing the next text. If it is possible to incorporate it, in step 50, the definition expression is incorporated and the variable is replaced with something whose behavior is known, such as a control variable for a loop. Thereafter, control is transferred to process 42.

After processing 43 and subsequent steps are performed on all texts, the process moves to step 51. In process 51, the overlapping relationship of subscripts is checked. If it is determined by the process 52 that vectorization is possible, the process 53 expands it to a vector instruction.
If vectorization is not possible, a process 54 generates an object using a normal scalar instruction. Next, in process 55, it is determined whether the translation of all texts into machine language has been completed, and if not, processes 51 to 54 are repeated for the next text content.

Next, the processing mode will be explained according to a specific example with reference to FIG. For example, assume that a group of instructions to be translated 4 as shown in FIG. 5A is given. Sentences S1, S3,
S5 and S6 are assignment statements that respectively instruct to assign the value of the expression on the right side to the variable on the left side. In particular, for sentence S6, array data is handled. Statements S2 and S4 are statements that instruct a so-called DO loop, and indicate that the command statements up to statement S7 should be repeatedly executed. There are multiple loops for loop control variables J and L.

The subscript scanning unit 31 searches the group of translated instructions 4 for subscripts of arrays that include variables whose behavior is unknown. In this example, there is an array in sentence S6, and its subscript information is as shown in Figure 5B, and the relationship between subscripts is clear, but the relationship between subscripts is unclear. It has become a state. Note that for array A, array B to be assigned
Since it is a different array from , it does not affect whether or not it can be vectorized. Conventionally, when there is a relationship between subscripts whose behavior is unknown, it has been thought that vectorization cannot be performed. In the case of the present invention, vectorization is promoted by clarifying the subscript relationship as follows.

The definition formula scanning unit 32 searches for definition formulas for variables iB and iA whose operations are unknown. In this example, sentences S3 and S5 are found. The subscript expression incorporation unit 33 incorporates the definition expressions given by statements S3 and S5 into subscript information. As a result, the subscript information regarding the sentence S6 is replaced with the subscripts ',',' as shown in FIG.

Here, if you check the relationship of subscripts, the first term on the left side and the right side have exactly the same subscript, so
There are no problems with vectorization. The relationship between the subscripts ' and ' is clarified by examining the operating ranges of the loop control variables L and J.
That is, from the sentence S4, 1≦L≦J 0≦L−1≦J−1 is obtained, and from this it can be seen that N≧NL+1≧N−J+1. Therefore, the relationship between the subscripts is as shown in FIG. 5D, and since the subscript ' is at least larger than "N-J+1", it can be seen that they do not overlap. This makes it possible to vectorize the in-loop array appearing in the group of instructions to be translated 4.

(E) Effects of the Invention As explained above, according to the present invention, the vectorization rate can be increased, and parts that could not be vectorized in the past are vectorized, thereby improving the execution performance of the generated objects. improves.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of general vector instruction generation, Fig. 2 is an explanatory diagram of problems in the conventional technology, and Fig. 3 is an explanatory diagram of general vector instruction generation.
The figure shows the configuration of an embodiment of the present invention, FIG. 4 is an explanatory diagram of processing of an embodiment of the invention, and FIG. 5 is an explanatory diagram of a specific processing aspect of an embodiment of the invention. In the figure, 2 is a translation processing device, 4 is a group of instructions to be translated,
10 is a vector processing device, 11 is a vector unit, 12 is a scalar unit, 22 is a main storage device, 23 is a channel device, and 24 is an object processor.
25 is a source module, 30 is a syntax analysis unit, 31 is a subscript scanning unit, 32 is a definition expression scanning unit, 33 is a subscript expression embedding unit, 34 is a vectorization possibility determination unit, 35 is a vector instruction generation unit, 36 represents a scalar instruction generator.

Claims (1)

[Claims] 1. Machine language instructions in a vector processing device equipped with a vector unit that executes vector instructions that process multiple pieces of data in parallel and a scalar unit that executes scalar instructions that process scalar data. a subscript scanning means for searching a subscript of an array appearing in a group of translated instructions expressed in a repeatedly executed form that includes a variable whose operation is unknown; A definition expression scanning means for searching for a defined expression; and a subscript expression embedding method for incorporating the definition content of the expression found by the definition expression scanning means into the subscript information in the form of replacing a variable whose behavior is unknown in the above subscript. means, determining means for determining whether vectorization is possible by examining the operating range based on the new subscript information generated by the subscript expression incorporating means; and according to the determination result of the determining means. An in-loop array processing vectorization processing method, comprising: a vector instruction generation processing section that generates the vector instruction described above.