JPH0573283B2 - - Google Patents
Info
- Publication number
- JPH0573283B2 JPH0573283B2 JP10590886A JP10590886A JPH0573283B2 JP H0573283 B2 JPH0573283 B2 JP H0573283B2 JP 10590886 A JP10590886 A JP 10590886A JP 10590886 A JP10590886 A JP 10590886A JP H0573283 B2 JPH0573283 B2 JP H0573283B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- outputs
- inputs
- amplified signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はアナログ分周器に関し、特に可変容量
ダイオードを含むアナログ分周器に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog frequency divider, and more particularly to an analog frequency divider including a variable capacitance diode.
衛星放送の実用化に伴う一般家庭へのマイクロ
波受信装置の普及によつて、将来、そこに使われ
るマイクロ波安定化発振器の需要が大量に見込ま
れている。そこで低コスト・高信頼度で量産に適
したマイクロ波安定化発振器の開発、特にIC化
が急務となつているが、その中で位相同期ループ
（PLL）を用いる方法はそれを可能にする１つの
方法である。この場合、マイクロ波安定化発振器
を構成するマイクロ波の分周器を実現することが
技術的重要ポイントであり、現在、それには特性
的にアナログ分周器が有望視されている。
BACKGROUND OF THE INVENTION With the spread of microwave receiving devices in general households with the practical use of satellite broadcasting, it is expected that there will be a large demand for microwave stabilizing oscillators used therein in the future. Therefore, there is an urgent need to develop a microwave stabilized oscillator that is low-cost, highly reliable, and suitable for mass production, and especially to integrate it into an IC. Among these, the method of using a phase-locked loop (PLL) makes this possible1. There are two methods. In this case, the technologically important point is to realize a microwave frequency divider that constitutes a microwave stabilization oscillator, and currently, analog frequency dividers are considered promising for this purpose due to their characteristics.
第２図は従来のアナログ分周器の一例のブロツ
ク図である。 FIG. 2 is a block diagram of an example of a conventional analog frequency divider.
この従来例のアナログ分周器は、分周信号を入
力して第１の増幅信号を出力する第１の増幅器１
３と、入力端子１からの入力信号と第１の増幅信
号とを入力してミクス信号を出力するミクサ２
と、ミクス信号を第１の遅延線路３を介して入力
し第２の増幅信号を出力する第２の増幅回路４
と、第２の増幅信号を入力し分周信号を出力端子
１２を介して出力する第２の遅延線路１１とで構
成される。 This conventional analog frequency divider includes a first amplifier 1 which inputs a frequency-divided signal and outputs a first amplified signal.
3, and a mixer 2 which inputs the input signal from the input terminal 1 and the first amplified signal and outputs a mix signal.
and a second amplification circuit 4 which inputs the mix signal via the first delay line 3 and outputs a second amplified signal.
and a second delay line 11 that inputs the second amplified signal and outputs the frequency-divided signal via the output terminal 12.
即ち、この従来例では、入力端子１から周波数
f0の入力信号を入力して、f0／（ｍ＋１）とnf0／
（ｍ＋１）の周波数成分を閉ループ内に存在させ、
その中からf0／（ｍ＋１）の周波数の分周信号を
出力端子１２より取出すことができる（電子通信
学会電子デバイス研究会、ED85−58「11GHz帯
GaAsモノリシツクアナログ1/4分周器」本城他
参照）。ここで、ｍは正の整数である。 That is, in this conventional example, the frequency is
Input an input signal of f 0 and obtain f 0 /(m+1) and nf 0 /
(m+1) frequency components exist in a closed loop,
From among them, a frequency-divided signal with a frequency of f 0 /(m+1) can be extracted from the output terminal 12 (IEICE Electronic Device Study Group, ED85-58 "11GHz band
GaAs Monolithic Analog 1/4 Frequency Divider” (see Honjo et al.). Here, m is a positive integer.
上述した従来のアナログ分周器は、閉ループの
固有周波数がf0／（ｍ＋１）近傍にないと１／
（ｍ＋１）分周動作が可能とならないので、その
為、例えばモノリシツクIC化した場合等には固
有周波数を調整できず回路定数のばらつきにより
閉ループの固有周波数が設計値からずれ、目的と
した周波数の分周動作ができないという欠点があ
つた。
The conventional analog frequency divider described above has a 1/
Since (m+1) frequency division operation is not possible, for example, when a monolithic IC is used, the natural frequency cannot be adjusted, and the natural frequency of the closed loop deviates from the designed value due to variations in circuit constants, resulting in the desired frequency. The drawback was that it could not perform frequency division operations.
本発明の目的は、周波数範囲の広い入力信号に
対して応答すると共に分周比も変更できしかも製
造上のばらつきによる固有周波数のずれも調整で
きる柔軟性に富むアナログ分周器を提供すること
にある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a highly flexible analog frequency divider that can respond to input signals with a wide frequency range, change the division ratio, and adjust deviations in natural frequencies due to manufacturing variations. be.
本発明のアナログ分周器は、分周信号を入力し
て第１の増幅信号を出力する第１の増幅器と、入
力信号と前記第１の増幅信号とを入力しミクス信
号を出力するミクサと、前記ミクス信号を第１の
遅延線路を介して入力し第２の増幅信号を出力す
る第２の増幅器と、前記第２の増幅信号を可変容
量ダイオードを介して入力し前記分周信号を出力
する第２の遅延線路とを有して成る。
The analog frequency divider of the present invention includes a first amplifier that inputs a frequency-divided signal and outputs a first amplified signal, and a mixer that inputs the input signal and the first amplified signal and outputs a mix signal. , a second amplifier that inputs the mixed signal via a first delay line and outputs a second amplified signal; and a second amplifier that inputs the second amplified signal via a variable capacitance diode and outputs the frequency-divided signal. and a second delay line.
次に、本発明の一実施例について図面を参照し
て説明する。
Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明のアナログ分周器の一実施例の
ブロツク図である。 FIG. 1 is a block diagram of one embodiment of the analog frequency divider of the present invention.
この実施例は、第１図に示すように、分周信号
を入力して第１の増幅信号を出力する第１の増幅
器１３と、入力端子１を介して入力する入力信号
と第１の増幅信号とを入力してミクス信号を出力
するミクサ２と、ミクス信号を第１の遅延線路３
を介して入力し第２の増幅信号を出力する第２の
増幅器４と、高周波阻止用の抵抗６及び９を介し
て電源７と接続することによつて直流逆バイアス
電圧値によつて容量値が変わる可変容量ダイオー
ド８と、コンデンサ５及び１０によつて直流バイ
アスを阻止しかつ高周波信号を通過出来るように
接続した可変容量ダイオード８を介して第２の増
幅信号を入力し分周信号を出力端１２を介して出
力する第２の遅延線路１１とで構成される。 This embodiment, as shown in FIG. a mixer 2 that inputs the signal and outputs a mix signal, and a mixer 2 that outputs a mix signal;
The capacitance value is determined by the DC reverse bias voltage value by connecting the second amplifier 4 which inputs the signal through the input terminal and outputs the second amplified signal to the power supply 7 through the high frequency blocking resistors 6 and 9. The second amplified signal is input through the variable capacitance diode 8, which is connected to the capacitors 5 and 10 to block DC bias and allow high frequency signals to pass through, and outputs a frequency-divided signal. and a second delay line 11 outputting through an end 12.
従つて、この実施例は、外部電源７を除いて
IC化が可能である。 Therefore, in this embodiment, except for the external power supply 7,
It is possible to convert it into an IC.
次に、この実施例の動作を説明すると、先ず、
入力端１に周波数f0の入力信号を入力すると入力
信号の周波数成分の１つであるmf0／（ｍ＋１）
（ここでｍは整数）の周波数の信号はミクサ２、
第１の遅延線路３、増幅器４、可変容量ダイオー
ド８、第２の遅延線路１１及び第１の増幅器１３
を通して増幅され再びミクサ２に加えられる。次
に、ミクサ２ではその増幅信号と入力信号とを混
合しf0±mf0／（ｍ＋１）の周波数の信号を出力
する。従つて、閉ループの固有周波数をf0／（ｍ
＋１）近傍におけばf0−mf0／（ｍ＋１）＝f0／
（ｍ＋１）成分のみを効率よく出力端子１２から
取出すことができる。ここで、閉ループ回路に必
要な特性は(1)f0で増幅作用をもたない、(2)mf0／
（ｍ＋１）とf0／（ｍ＋１）の周波数成分の信号
を増幅する、(3)固有周波数がf0／（ｍ＋１）近傍
にある、等を満足する必要がある。 Next, to explain the operation of this embodiment, first,
When an input signal with frequency f 0 is input to input terminal 1, one of the frequency components of the input signal, mf 0 / (m + 1)
(where m is an integer) the signal of frequency is mixer 2,
First delay line 3, amplifier 4, variable capacitance diode 8, second delay line 11 and first amplifier 13
The signal is amplified through the filter and added to mixer 2 again. Next, the mixer 2 mixes the amplified signal and the input signal and outputs a signal with a frequency of f 0 ±mf 0 /(m+1). Therefore, the natural frequency of the closed loop is f 0 /(m
+1) In the vicinity, f 0 −mf 0 /(m+1)=f 0 /
Only the (m+1) component can be efficiently extracted from the output terminal 12. Here, the characteristics required for a closed loop circuit are (1) f 0 with no amplification effect, (2) mf 0 /
It is necessary to amplify signals with frequency components of (m+1) and f 0 /(m+1), and (3) the natural frequency is near f 0 /(m+1).
又、この実施例の閉ループの固有周波数は、こ
の閉ループの回路定数によつて決るが、可変容量
ダイオード８がこの閉ループの中に含まれている
のでこの可変容量ダイオード８の容量変化の範囲
内で固有周波数を変えることができる。 Further, the natural frequency of the closed loop in this embodiment is determined by the circuit constant of this closed loop, but since the variable capacitance diode 8 is included in this closed loop, the natural frequency of the closed loop is determined within the range of the capacitance change of this variable capacitance diode 8. The natural frequency can be changed.
以上説明したように本発明は、可変容量ダイオ
ードを閉ループ内に挿入することにより非常に柔
軟性に富むアナログ分周器を実現し、周波数範囲
の広い入力信号に対して分周信号の出力が可能に
なるという効果と、同じ周波数の入力信号に対し
ても分周比を変えることができるという効果と、
更に、製造上のばらつきによつて閉ループの固有
周波数が設計値からずれた場合でも製造後の調整
によつて、製造上のばらつきによる不良品の発生
率を大幅に低減することができる効果がある。
As explained above, the present invention realizes a highly flexible analog frequency divider by inserting a variable capacitance diode into a closed loop, and is capable of outputting a frequency-divided signal for input signals with a wide frequency range. and the effect that the division ratio can be changed even for input signals of the same frequency.
Furthermore, even if the natural frequency of the closed loop deviates from the design value due to manufacturing variations, post-production adjustments can significantly reduce the incidence of defective products due to manufacturing variations. .
第１図は本発明のアナログ分周器の一実施例の
ブロツク図、第２図は従来のアナログ分周器の一
例のブロツク図である。
１…入力端子、２…ミクサ、３…遅延線路、４
…増幅器、５…コンデンサ、６…抵抗、７…電
源、８…可変容量ダイオード、９…抵抗、１０…
コンデンサ、１１…遅延線路、１２…出力端子、
１３…増幅器。
FIG. 1 is a block diagram of an embodiment of an analog frequency divider according to the present invention, and FIG. 2 is a block diagram of an example of a conventional analog frequency divider. 1...Input terminal, 2...Mixer, 3...Delay line, 4
...Amplifier, 5...Capacitor, 6...Resistor, 7...Power supply, 8...Varactor diode, 9...Resistor, 10...
Capacitor, 11...delay line, 12...output terminal,
13...Amplifier.
Claims (1)
る第１の増幅器と、入力信号と前記第１の増幅信
号とを入力しミクス信号を出力するミクサと、前
記ミクス信号を第１の遅延線路を介して入力し第
２の増幅信号を出力する第２の増幅器と、前記第
２の増幅信号を可変容量ダイオードを介して入力
し前記分周信号を出力する第２の遅延線路とを有
することを特徴とするアナログ分周器。1 A first amplifier that inputs a frequency-divided signal and outputs a first amplified signal; a mixer that inputs the input signal and the first amplified signal and outputs a mix signal; a second amplifier that inputs the second amplified signal via a delay line and outputs the second amplified signal; and a second delay line that inputs the second amplified signal via a variable capacitance diode and outputs the frequency-divided signal. An analog frequency divider comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10590886A JPS62262504A (en) | 1986-05-08 | 1986-05-08 | Analog frequency divider |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10590886A JPS62262504A (en) | 1986-05-08 | 1986-05-08 | Analog frequency divider |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62262504A JPS62262504A (en) | 1987-11-14 |
| JPH0573283B2 true JPH0573283B2 (en) | 1993-10-14 |
Family
ID=14419967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10590886A Granted JPS62262504A (en) | 1986-05-08 | 1986-05-08 | Analog frequency divider |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62262504A (en) |
-
1986
- 1986-05-08 JP JP10590886A patent/JPS62262504A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62262504A (en) | 1987-11-14 |
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