JPH0572196B2 - - Google Patents

Description

Detailed Description of the Invention (a) Field of Industrial Application The present invention relates to a pulse generation circuit that generates a pulse of a predetermined width according to the falling edge of a pulse train from a pulse train having opposite phases to each other, and particularly relates to an IC ( This invention relates to a pulse generation circuit suitable for integration (integrated circuit). (B) Prior Art Conventionally, a monostable multivibrator is generally used to generate pulses of a predetermined width from a pulse train depending on the rise and fall of the pulse train. Furthermore, a method has also been commonly used in which a delay circuit is configured with an integrator using a logic circuit or a capacitor, and a pulse of a predetermined width is generated by performing a logical operation on an input signal and an output signal of the delay circuit.
The monostable multivibrator is manufactured in 1973, for example.
It is described on page 102 of "Pulse Circuit Design" published by CQ Publishing Co., Ltd. on June 1, 2017. (c) Problems to be Solved by the Invention However, the monostable multivibrator has a drawback in that it is not suitable for IC implementation because it includes a capacitor. Furthermore, the method of forming a delay circuit using logic circuits has the drawback that since the amount of delay per stage is small, a plurality of stages must be connected in cascade, making the circuit complex. (d) Means for Solving the Problems The present invention has been made in view of the above points, and includes an input stage circuit that generates first and second output signals consisting of pulse trains having mutually opposite phases; An amplifier circuit that amplifies the first output signal and an AND gate that ANDs the signal obtained at the input terminal of the amplifier circuit and the second output signal are provided, and the carrier accumulation effect of the transistors forming the amplifier circuit is utilized. and generates a pulse corresponding to the fall of the first output signal. (e) Effects According to the present invention, since the amplifier circuit is constituted by a plurality of transistors whose bases and emitters are connected in cascade, the carrier accumulation effect of the transistors can be utilized and there is no need to use a capacitor. (F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
1 has an input terminal 2 to which an input signal is applied and generates an output signal in phase with the input signal; 3 has first and second transistors 4 and 5 whose emitters are commonly connected; , a first transistor in phase with the input signal is connected to the collector of the first transistor 4.
a differential amplifier circuit that generates a second output signal having an opposite phase to the input signal to the collector of the second transistor 5 ; 8, a first amplifier circuit for amplifying the first output signal obtained at the collector of the first transistor 4; 9 , fifth and sixth transistors whose base and emitter are cascade-connected;
A second amplifier circuit is made up of transistors 10 and 11 and amplifies the second output signal obtained at the collector of the second transistor 5; 12 is an input terminal of the first amplifier circuit 6 ; an AND gate 13 for ANDing the signal obtained at the input end of the second amplifier circuit 9 , that is, the base of the fifth transistor 10;
is an inverting transistor that inverts the signal obtained at the output terminal of the AND gate 12, and 14 is a first output terminal connected to the collector of the inverting transistor 13. Signal applied to input terminal 2, front stage amplifier circuit 1
The output signal of the second transistor 4 and the first output signal obtained at the collector of the first transistor 4 of the differential amplifier circuit 3 are
The result is a pulse train as shown in Figure A. Further, the second output signal obtained at the collector of the second transistor 5 of the differential amplifier circuit 3 becomes a pulse train having the opposite phase to that of the above-mentioned FIG. 2A, as shown in FIG. 2B. The first output signal obtained at the collector of the first transistor 4 is amplified by the first amplifier circuit 6 and sent to the second output terminal 1.
5 to the subsequent stage. Further, the second output signal obtained at the collector of the second transistor 5 is
The signal is amplified by the second amplifier circuit 9 and transmitted from the third output terminal 16 to the subsequent stage. The signals transmitted from the second and third output terminals 15 and 16 to the subsequent stage are used for their original purpose. The third to sixth transistors 7 to 11 constituting the first and second amplifier circuits 6 and 9 are used in a saturation region, and excessive carriers are injected into their bases. Further, the bases of the third and fifth transistors 7 and 10 are connected to the first and second transistors 4 and 5, respectively, which have high impedance.
The values of load resistors 17 and 18 connected to the collectors of the first and second transistors 4 and 5, respectively, are set to be relatively large. Therefore, a carrier accumulation effect occurs, and the time required for the accumulated carriers to be discharged, that is, the storage time becomes extremely long. The carrier accumulation effect delays the response to the pulse and causes the waveforms of the first and second output signals applied to the bases of the third and fifth transistors 7 and 10 to be delayed as shown by dotted lines in FIG. let The waveform delay occurs when the first and second output signals switch from "H" to "L", and visually it appears as if the "H" period has been extended. Thus, the two input terminals of the AND gate 12 are connected to the third and fifth transistors 7 and 10, respectively.
, the first waveform with the delayed portion shown in Figure 2 A and B above.
When the second output signal is present, a pulse as shown in FIG. The pulse or inverted pulse corresponds to the rising edge and falling edge of the input signal, and by detecting the pulse or inverted pulse, the rising edge and falling edge of the input signal can be detected. Furthermore, by checking the generation interval of the pulse or inverted pulse, the frequency of the input signal can be detected. The storage time of the first amplifier circuit 6 consisting of the third and fourth transistors 7 and 8 and the storage time of the fifth and sixth transistors
The storage time of the second amplifier circuit 9 consisting of transistors 10 and 11 is determined depending on the area of each transistor and the amount of carriers injected into the base, and the width of the output pulse of the AND gate 12 is determined according to the area of each transistor and the amount of carriers injected into the base. It is determined by the time and the threshold level of the AND gate 12, so by adjusting them appropriately,
A pulse having an arbitrary width is passed through the AND gate 12.
It can be generated at the output terminal of. By the way,
As shown in FIG. 1, the third and fourth transistors 7
and 8 are connected in a Darlington manner, and the areas of the respective transistors are set to 2000 μm ² and 200000 μm ² , it is possible to generate a pulse having a pulse width of 5 to 10 μsec. The pulse generation circuit according to the present invention can be used, for example, as a lock detection circuit for a two-phase DC motor. For example, if a Hall IC (an IC incorporating a Hall element and a comparison circuit) is connected to the input terminal 2, and motor windings are connected as loads for the first and second amplifier circuits 6 and 9 , the motor will rotate. A pulse is generated from the AND gate 12 in response to the motor lock, and the pulse is not generated when the motor is locked. Therefore, the pulse can be used to detect whether or not the motor is locked, and the pulse can also be used to protect the motor when it is locked. In the embodiment, the first and second amplifier circuits 6 and 9 are arranged to generate pulses in response to the falling of the first and second output signals, but at least the first output signal If it is sufficient to generate a pulse only at the falling edge of the signal, the second amplifier circuit may be omitted. In the embodiment shown in FIG. 1, the third and fourth transistors 7 and 8 are connected in Darlington, but the collector of the third transistor 7 is connected to the power supply (+Vc.c. ₁ ) through a resistor. It is also possible to have a configuration in which (G) Effects of the Invention As described above, according to the present invention, it is possible to generate a pulse corresponding to the falling edge of a pulse train of an input signal without using a capacitor.
We can provide a pulse generation circuit suitable for IC implementation. In addition, by utilizing the carrier accumulation effect of transistors,
Since pulses are generated in accordance with the falling edge of the pulse train, it is possible to provide a pulse generating circuit with an extremely simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2A to 2D are characteristic diagrams showing waveforms at various parts in FIG. Explanation of main drawing numbers, 3 ...Differential amplifier circuit, 6 ...
1st amplifier circuit, 9 ...2nd amplifier circuit, 12...AND gate.

Claims (1)

[Claims] 1 are differentially connected, both collectors are set to high impedance, a rotation detection signal indicating the rotation of the motor is applied to one base, and first and second output signals consisting of pulse trains of opposite phases to each other are output. first and second transistors forming a differential amplifier obtained from both collectors;
and a third transistor having a large resistance value connected to the collector of the second transistor; a third transistor to which the first output signal is applied to the base; a fourth transistor connected in cascade with the base-emitter of the transistor No. 3; a fifth transistor to which the second output signal is applied to the base;
a sixth transistor whose emitter is cascade-connected to the base and emitter of the fifth transistor and whose collector is connected to the motor between the collector of the fourth transistor; and the first and second outputs. an AND gate that performs an AND operation of signals, and delays the fall of the first and second output signals by the carrier accumulation effect of the third and fifth transistors, and from the AND gate. A pulse generation circuit characterized in that it generates a pulse corresponding to the fall of the first and second output signals, and detects a lock of the motor based on the pulse.