JPH057159A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To use one kind of D/A converter in various ways by controlling a parameter setting means with a setting control means and setting processing circuit parameter to decide an output state of an analog output voltage. CONSTITUTION:A parameter setting means consists of analog switches Sl11-S14, S21-S24 and a voltage division ladder resistance circuit 26 and an output voltage range of a ladder resistance circuit 17 is set optionally. A 2-bit switching signal is externally set to registers R11, R12 as setting control means respectively to make any of the switches S11-S14, S21-S24 closed. Furthermore, a 3rd voltage follower type operational amplifier 27 or the circuit 17 is connected to a signal terminal based on the switching signal of the register 13 as the setting control means and registers R21-R23, R31-R33, R41-R43 as control means are provided corresponding to D/A converters 12 14. Thus, the circuit parameter is optionally set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-analog converter (hereinafter referred to as a D / A converter). In mass production of electronic circuits and systems in recent years, reduction of the number of parts,
It is required to improve the performance, reduce the cost, and improve the productivity while reducing the kinds of parts.

Therefore, the D / A converter is also required to have general versatility, and it is necessary to enable various uses by one device.

[0003]

2. Description of the Related Art Conventional D / A converters can only be used in a uniform manner because the circuit parameters that determine the output state of the analog output voltage are not variable. That is, for example, D
When the high-potential-side and low-potential-side reference voltages applied to the / A converter are set, D / A conversion can be performed only within the range of both reference voltages. Therefore, in order to use a plurality of D / A converters with various reference voltages, the reference voltages had to be generated externally. Further, various circuit parameters, such as the presence / absence of use of the operational amplifier in the D / A converter including the voltage follower type operational amplifier, the D / A conversion time, and the current driving capability of the operational amplifier cannot be set. Had to prepare many kinds of D / A converters in order to obtain the output voltage.

[0004]

Therefore, a plurality of D /
When trying to use the A converter with various reference voltages, it is necessary to provide an external circuit to generate the voltage externally, which leads to an increase in the number of parts and an increase in cost. In addition, since various circuit parameters cannot be set, when the parts are optimized, the types of the parts are increased and the production management becomes complicated. On the other hand, when a voltage follower type operational amplifier is provided in order to cover all with one type of D / A converter, the voltage follower type operational amplifier may have excessive performance, and the power consumption increases due to the operational amplifier. was there.

The present invention has been made to solve the above-mentioned problems and is capable of setting various circuit parameters that determine the output state of an analog output voltage, and is one type of D / A converter. The purpose is to be able to use in various ways.

[0006]

FIG. 1 is a diagram for explaining the principle of the present invention.

The parameter setting means 1 is capable of setting a plurality of circuit parameters for predetermined circuit parameters for determining the output state of the analog output voltage AV, and the setting control means 2 is a parameter based on a control signal. The setting means 1 is controlled to set desired circuit parameters.

Further, the parameter setting means is controlled by the voltage dividing ladder resistance circuit having the high potential side reference voltage Vref + applied to one end and the low potential side reference Vref− applied to the other end, and the setting control means. A switch circuit for selecting two different nodes from the nodes of each stage of the voltage dividing ladder resistance circuit and setting the upper and lower limit voltages to be supplied to the ladder resistance circuit.

Further, the parameter setting means includes a voltage follower type operational amplifier connected to the ladder resistance circuit and a switch circuit controlled by the setting control means to connect the voltage follower type operational amplifier or the ladder resistance circuit to the output terminal. Configured. Whether to use the voltage follower type operational amplifier is set.

Further, in the voltage follower type operational amplifier including the differential circuit section for differentially amplifying the output voltage of the ladder type resistance circuit and the output buffer circuit section, the parameter setting means is provided.
A plurality of voltage setting resistors provided in parallel with the power source and having different resistance values, and one of these voltage setting resistors controlled by the setting control means is connected to the gate terminal of the low current transistor of the differential circuit section. And a switch circuit to connect to.

In the voltage follower type operational amplifier having the differential circuit section for differentially amplifying the output voltage of the ladder resistance circuit and the output buffer circuit section, the parameter setting means is provided in parallel with the power supply. It is composed of a plurality of voltage setting resistors having different resistance values and a switch circuit which is controlled by the setting control means and connects one of these voltage setting resistors to the gate terminal of the constant current transistor of the output buffer circuit section. .

[0012]

Therefore, according to the first invention, the setting control means 2
Since the parameter setting means 1 can be controlled to set a predetermined circuit parameter for determining the output state of the analog output voltage AV, one type of digital-analog converter can be used in various ways.

That is, the parameter setting means is controlled by the voltage dividing ladder resistance circuit to which the high potential side reference voltage Vref + is applied to one end and the low potential side reference voltage Vref- is applied to the other end, and the setting control means. By selecting two different nodes from among the nodes of each stage of the voltage dividing ladder resistance circuit and setting the upper limit voltage and the lower limit voltage supplied to the ladder resistance circuit,
The output voltage range of the digital-analog converter can be changed.

Further, the parameter setting means includes a voltage follower type operational amplifier connected to the ladder resistance circuit and a switch circuit which is controlled by the setting control means and connects the voltage follower type operational amplifier or the ladder resistance circuit to the output terminal. With the configuration, it is possible to set whether or not the voltage follower type operational amplifier is used.

Further, in the voltage follower type operational amplifier having the differential circuit section for differentially amplifying the output voltage of the ladder type resistance circuit and the output buffer circuit section, the parameter setting means is provided.
A plurality of voltage setting resistors provided in parallel with the power source and having different resistance values, and one of these voltage setting resistors controlled by the setting control means is connected to the gate terminal of the low current transistor of the differential circuit section. With the switch circuit connected to, it is possible to set the current value of the differential circuit section, that is, the D / A conversion time.

In the voltage follower type operational amplifier having the differential circuit section for differentially amplifying the output voltage of the ladder resistance circuit and the output buffer circuit section, the parameter setting means is provided in parallel with the power supply. It is composed of a plurality of voltage setting resistors having different resistance values and a switch circuit which is controlled by the setting control means and connects one of these voltage setting resistors to the gate terminal of the constant current transistor of the output buffer circuit section. As a result, the current value of the output buffer circuit section can be set, that is, the current driving capability of the operational amplifier can be set.

[0017]

An embodiment embodying the present invention will be described below with reference to FIG.

FIG. 2 shows a semiconductor integrated circuit device in which the D / A converters 11 to 14 of the first to fourth channels are formed on the chip 100, and the power supply terminals 15 and 16 have a high potential side and a low potential side. Reference voltages Vref + and Vref- are applied.

Next, each of the D / A converters 11 to 14 will be described. Since the D / A converters 11 to 14 have the same structure, the D / A converter 11 will be described and the other D / A converters will be described. A
The description of the converters 12 to 14 will be omitted.

The D / A converter 11 is an 8-bit D / A converter, and the R-2R ladder resistance circuit 17 uses a resistor 18 having a resistance value R and a weighting resistor 19 having a resistance value 2R to generate a digital input signal. The number of bits is 8 stages. Each weighting resistor 19 is connected between the pMOS and nMOS transistors of each switch circuit 21 constituting the selection circuit 20. The pMOS transistor of each switch circuit 21 is connected to the first voltage follower type operational amplifier 22, and the nMOS transistor is connected to the second voltage follower type operational amplifier 23.
1 is a first or second voltage follower type operational amplifier 22, which is a voltage to be connected to the weighting resistor 19 of each corresponding stage of the ladder type resistor circuit 17 based on the value of each bit D0 to D7 of the digital input signal. Switch to the output voltage of 23.
A resistor 24 is connected to the node X of the stage corresponding to the least significant bit D0 of the digital input signal of the ladder resistor circuit 17, and the resistor 24 is the first voltage follower operational amplifier 22.
Is connected to the output terminal of.

Between the power supply terminals 15 and 16, there is provided a voltage dividing ladder type resistance circuit 26 consisting of four stages of resistances 25 having the same resistance value, and the voltage between the power supply terminals 15 and 16 is 4 etc. by each resistance 25. You can share. On the other hand, the first
Of the voltage follower type operational amplifier 22 of FIG.
2, S13, S14 are connected, and analog switches S21, S22, S23, S as switch circuits are connected to the non-inverting input terminal of the second voltage follower operational amplifier 23.
24 is connected.

In this embodiment, each of the analog switches S1
1 to S14, S21 to S24 and the voltage dividing ladder resistance circuit 26 constitute a parameter setting means, and the R-2
The output voltage range of the R ladder resistance circuit 17 can be set arbitrarily. That is, each analog switch S11, S1
By closing any one of S2, S13, and S14, the input voltage of the first voltage follower operational amplifier 22,
That is, the upper limit voltage supplied to the ladder resistance circuit 17 via each switch circuit 21 of the selection circuit 20 can be arbitrarily set, and each analog switch S21, S22, S
By closing one of S23 and S24, the second
The input voltage of the voltage follower operational amplifier 23, that is, the lower limit voltage supplied to the ladder resistance circuit 17 via each switch circuit 21 of the selection circuit 20 can be arbitrarily set.

Registers R11 and R as setting control means
A switching signal of 2 bits is set from the outside by 12 respectively, and a register R11 causes the analog switches S11, S12,
Only one of S13 and S14 is closed, and the register R12 similarly closes only one of the analog switches S21, S22, S23 and S24 based on the switching signal.

Further, a third voltage follower type operational amplifier 27 is connected to the node Y of the stage corresponding to the most significant bit D7 of the digital input signal of the ladder resistance circuit 17.
On the other hand, a switch circuit 29 is connected to the output terminal 28, and the third voltage follower operational amplifier 27 or the ladder resistance circuit 17 can be connected to the output terminal 28 based on the switching signal of the register R13 as setting control means. That is,
The switch circuit 29 can be used to set whether or not the third voltage follower type operational amplifier 27 is used. A 1-bit switching signal is externally set in the register R13.

Registers R21 to R23, R as setting control means corresponding to the respective D / A converters 12 to 14 are also provided.
31 to R33 and R41 to R43 are provided.

In the above-described first embodiment of the present invention, the voltage follower type operational amplifier 2 for each of the channels CH1 to CH4.
The seven parameters can be changed.

FIG. 3 is a circuit diagram showing the configuration of the voltage follower type operational amplifier 27 in this case.

The voltage follower type operational amplifier 27 comprises a differential circuit section 30 and an output buffer circuit section 31. The differential circuit unit 30 includes pMOS transistors 32 and 33 whose gate terminals are commonly connected and respective pMOS transistors 32 and 33.
NMOS transistors 34 and 35 connected to the
A constant current transistor 36 commonly connected to the MOS transistors 34 and 35, and the gate terminal of the nMOS transistor 34 is connected to the node Y. The output buffer circuit unit 31 is a pMOS connected to the power supply VCC.
It is composed of a transistor 37 and a constant current transistor 38 composed of an nMOS transistor, and the gate terminal of the pMOS transistor 37 is connected to a connection point Z between the pMOS transistor 32 and the nMOS transistor 34.

The gate terminal of the constant current transistor 36 is connected to a conversion time setting circuit 39 as a parameter setting means, and the gate terminal of the constant current transistor 38 is connected to a current drivability setting circuit 40 as a parameter setting means. ing.

The conversion time setting circuit 39 includes voltage setting resistors 41 to 43 connected in parallel to the power source VCC and having different resistance values.
And an nMOS transistor 47 commonly connected to the analog switches 44 to 46 as a switch circuit, and one of the analog switches 44 to 46 is selected based on the switching signal of the register R50 as the setting control means.
By closing one of them, the voltage value applied to the gate terminal of the constant current transistor 36 of the differential circuit section 30 can be changed to change the current value of the differential circuit section 30, and the D / A conversion time can be reduced. Can be changed.

Further, the current drive capacity setting circuit 40 uses the power source VC
A voltage setting resistor 48 connected in parallel with C and having a different resistance value
To 50 and an analog switch 51 as a switch circuit
To the output buffer circuit by closing any one of the analog switches 51 to 53 based on the switching signal of the register R60 as the setting control means. The voltage value applied to the gate terminal of the constant current transistor 38 of the unit 31 can be changed to change the current value of the output buffer circuit unit 31, and the current drive capability of the third voltage follower operational amplifier 27 can be changed. .

A 2-bit switching signal is externally set to each of the registers R50 and R60.

The switch 55 is connected between the transistor 38 and ground and is controlled by the 1-bit switching signal stored in the register R70. The switch 2a in FIG.
The switch 55 is closed while selecting. As a result, the voltage follower type operational amplifier is held in the non-operating state, and the energy consumed here can be reduced.

FIG. 4 is a circuit diagram of the switches S11 to S14 shown in FIG. As shown, switches S11-S1
4 is pMOS transistors Tr1 and Tr2, nMOS transistors Tr3 and Tr4, and NAND gates 61 to 64.
And inverters 65 to 69. The register R60 has two 1-bit storage areas R111 and R112.
Is divided into The NAND gates 62 to 64 and the inverters 65 to 67 turn on any one of the transistors Tr1 to Tr4.

FIG. 5 is a diagram showing a register group formed on the chip 100. Five register groups 70 to 74 are formed on the chip 100. The serial data composed of the bits D0 to D19 generated and output by the COU 150 is the shift clock C generated by the CPU 150.
The data is transferred to the register group 70 in synchronization with LK and written therein. The data D0 to D7 are digital input signals to be converted into analog signals. The data D8 is shown in FIG.
Is used to control the switch 29 shown in FIG.
The data D9 and D10 are used to select one of the switches S21 to S24. The data D11 and D12 are used to select one of the switches S11 to S14. The data D13 is used to control the switch 55 in FIG. The data D14 and D15 are stored in the switch S.
Used to select one of 51 to S53. The data D16 and D17 are used to select one of the switches 44-46. The data D18 and D19 are used to select one of the register groups 71 to 74.
The data D18 and D19 are input to the address decoder 75 and decoded in response to the load signal LD from the CPU 150.

The address decoder 75 uses the data D18 and D
When 19 is decoded and the register group 71 is selected, the data D0 to D7 are written in the corresponding 8-bit register area, the data D8 is written in the register R13, and the data D9 and D10 are written in the 2-bit register R12. The data D11 and D12 are written in the 2-bit register R11. Further, the data D13 is written in the register 70,
The data D14 and D15 are written in the register R60, and the data D16 and D17 are written in the register R50.

FIG. 6 is a diagram showing the supply voltage applied to the chip 100. As shown, 4 power supplies VDD, V
SS, VCC and GND are used.

The operational amplifiers 22, 23 and 27 are VCC, G
It operates in ND and the reference voltage setting circuit (S11-S
24) operates with VDD and VSS. The digital input signal has two values of VCC and GND.

4 power supplies (VDD, VSS, VCC, GN
The relationship between D) and the register setting will be described below.

When VDD = VCC and VSS = GND, the power supply voltage supplied from the outside requires only two types. In this case, VDD terminal and VCC
The terminals may be short-circuited, and the VSS terminal and the GND terminal may be short-circuited. The switches (S11 to S24) perform control to limit the data set in the register so that the selection circuit 20 can perform a switching operation (a voltage difference of the sum of the threshold values of the P and N channel transistors is required). You may.

When VDD> VCC and VSS <GND, four power supply voltages are required. In this case, the switches (S11 to S24) are limited to the data set in the register so that VDD <= VCC, VSS> = GND.
It should be so.

When VDD <VCC, VSS> GND, four power supply voltages are required. Switch (S11-S
24) may be controlled so that the data set in the register is limited so that the selection circuit 20 is in the range in which the switching operation can be performed (the voltage difference of the sum of the threshold values of the P and N channel transistors is required). .

Next, the configuration of the operational amplifiers 22 and 23 will be described.

Transistor 3 of the differential amplifier 30 of FIG.
When the transistors of the operational amplifiers 22 and 23 corresponding to 4 and 35 are enhancement type transistors, the output voltage is within the range in which the linearity of the operational amplifiers 22, 23 and 27 can be ensured even if the VCC to GND voltage is input to the input +. VC
Enhancement transistor 3 from C to GND potential
Only the voltage increased by the threshold value of 4 is output. Therefore, only the voltage range output from the operational amplifiers 22 and 23 is output to the output Y, and the GND voltage cannot be output.

On the other hand, when the transistors of the operational amplifiers 22 and 23 corresponding to the transistors 34 and 35 of the differential amplifier 30 of FIG. 3 are depletion type transistors, the range where the linearity of the operational amplifiers 22, 23 and 27 can be secured is the input + Even if the VCC to GND voltage is input to the
Only the voltage dropped from the CC potential by the threshold value of the transistor 34 to GND is output. Therefore, output Y
Output only the voltage range output from the operational amplifiers 22 and 23, and cannot output the VCC voltage.

Further, when the operational amplifier 22 is an enhancement type and the operational amplifier 23 is a depletion type, the output Y
Is a voltage range V output from the operational amplifiers 22 and 23.
It is possible to output CC to GND voltage. Therefore, it is preferable that the operational amplifier 22 is an enhancement type and the operational amplifier 23 is a depletion type.

Next, refer to FIG. 7 for the second embodiment of the present invention.
And explain. FIG. 7 shows 12 8-bit D / A converters.
81₁~ 81₁₂Is provided on the D / A converter chip 200.
The configuration is shown. The 12-bit shift register 82 is
12-bit serial data SD1 from CPU 150
To receive. This serial data SD1 is an 8-bit data
Digital input signals D0 to D7 and D / A converter 81₁~ 81
₁₂4 bits D8 to D11 for selecting one of
It Bits D0 to D7 of the digital input signal are 12
18-bit latch circuit 85₁~ 85₁₂Is input to D /
A converter 81₁~ 81₁₂Given to. 10 bit shift
The register 83 is a 10-bit serial from the CPU 150.
Receive the SDLE data SD2. This serial data SD2
Are the bits corresponding to the above-mentioned bits D8 to D17, respectively.
To D12 to D21. Bits D12 to D21 are
Circuit 85₁~ 85₁₂D / A conversion after being latched by
Vessel 81₁~ 81₁₂And switch 29 (Lie connected here
Are omitted for convenience). A / D converter
81₁~ 81₁₂The analog output signals output by
The switch 29 corresponding to this is entered. Each switch 29 is other
One receives the output signal of the corresponding operational amplifier 28
It The output signal selected by the switch 29 is AO01 to A
This is indicated by O12. VCC and GND lines 87,8
8 is wired as shown. For convenience, VC
Each power supply voltage of C and GND is supplied through the same line,
It is illustrated as such. Power supply voltage VDD and VEE are D / A change
Exchange 81 ₁~ 81₁₂Is given to.

The shift registers 82 and 83 may be provided for each of the D / A converters 81 _{1 to} 81 ₁₂ . In this case, the decoder 84 becomes unnecessary. Further, the shift registers 82 and 83 and the latch circuits 83 _{1 to} 83 ₁₂ may be replaced with the configuration shown in FIG.

In this embodiment, the D / A converters 11 to 14 having the R-2R ladder resistance circuit 17 are used.
^It may be implemented in a D / A converter having an ⁿ R ladder resistance circuit.

Further, although the present embodiment is embodied as a D / A converter that handles an 8-bit digital input signal, it may be embodied as a D / A converter that handles a digital input signal of an arbitrary number of bits.

Further, in the present embodiment, the four resistors 25 of the voltage dividing ladder type resistor circuit 26 have the same resistance value, but for example, 3
One resistance may be the same as the resistance value, and the resistance value of one resistance may be different from the resistance values of the other three resistances.

Further, the current value may be set in the differential circuit section or the output buffer circuit section in the first and second voltage follower type operational amplifiers 22 and 23.

[0053]

As described above in detail, according to the first aspect of the invention, the circuit parameter for determining the output state of the analog output voltage can be arbitrarily set, so that one type of digital-analog converter can be used for various purposes. Can be used

According to the invention of claim 2, the output voltage range of the digital-analog converter can be changed.

According to the third aspect of the invention, it is possible to set whether or not the voltage follower operational amplifier is used.

According to the invention of claim 4, the D / A conversion time can be arbitrarily set by changing the current value of the differential circuit portion in the voltage follower operational amplifier.

Further, according to the invention of claim 5, by changing the current value of the output buffer circuit section in the voltage follower type operational amplifier, the current driving capability of the operational amplifier can be arbitrarily set.

According to the sixth aspect of the invention, the characteristics of the plurality of D / A converters formed on one chip can be individually set.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram of the voltage follower type operational amplifier shown in FIG.

FIG. 4 is a circuit diagram of a switch provided on the input side of a voltage follower operational amplifier that outputs a reference voltage.

FIG. 5 is a block diagram showing a register used in the first embodiment of the present invention.

FIG. 6 is a diagram showing a power supply voltage used in the first embodiment of the present invention.

FIG. 7 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

1 Parameter setting means 2 Setting control means AV Analog output voltages D0 to Dn-1 Digital input signals Vref + and Vref- are high-potential side and low-potential side reference voltages, respectively.

Claims (6)

[Claims] 1. A high-potential-side and low-potential-side reference voltage (Vref +, V) comprising a ladder resistance circuit and a selection circuit.
ref-) is applied and the analog output voltage (A) corresponding to the n-bit digital input signal (D0 to Dn-1) is applied.
In the digital-analog converter that outputs V), the parameter setting means (1) capable of setting a plurality of circuit parameters for predetermined circuit parameters for determining the output state of the analog output voltage (AV), and the control signal And a setting control means (2) for controlling the parameter setting means (1) to set desired circuit parameters based on the digital-analog converter. 2. The circuit parameter is an output voltage range of the digital-analog converter, and the parameter setting means applies a high-potential-side reference voltage input to the digital-analog converter to one end thereof, and a low-potential side. A ladder type resistor circuit for voltage division with the reference voltage applied to the other end,
And a switch circuit which is controlled by the setting control means to select two different nodes from among the nodes of each stage of the voltage dividing ladder resistance circuit to set upper and lower limit voltages to be supplied to the ladder resistance circuit. The digital-analog converter according to claim 1, characterized in that: 3. The circuit parameter is presence / absence of use of a voltage follower type operational amplifier, the parameter setting means is a voltage follower type operational amplifier connected to a ladder resistance circuit, and the voltage follower type is controlled by the setting control means. An operational amplifier or a switch circuit for connecting the ladder resistance circuit to an output terminal.
The described digital-to-analog converter. 4. The voltage follower type operational amplifier includes a differential circuit section for differentially amplifying an output voltage of the ladder resistance circuit and an output buffer circuit section, and the circuit parameter is a current value of the differential circuit section. The parameter setting means is provided with a plurality of voltage setting resistors having different resistance values provided in parallel with the power source, and one of these voltage setting resistors controlled by the setting control means is differential. 4. A digital circuit according to claim 3, further comprising a switch circuit connected to the gate terminal of the low current transistor of the circuit section.
Analog converter. 5. The voltage follower operational amplifier includes a differential circuit section for differentially amplifying an output voltage of the ladder resistance circuit and an output buffer circuit section, and the circuit parameter is a current value of the output buffer circuit section. The parameter setting means includes a plurality of voltage setting resistors provided in parallel with the power source and having different resistance values, and one of the voltage setting resistors controlled by the setting control means of the output buffer. 4. The digital-analog converter according to claim 3, comprising a switch circuit connected to the gate terminal of the constant current transistor. 6. A chip, and a plurality of digital-analog converters provided on the chip, each digital-analog converter
The analog converter includes a ladder resistance circuit and a selection circuit, and has a high-potential-side and low-potential-side reference voltage (Vref).
A digital-analog converter that outputs an analog output voltage (AV) corresponding to an n-bit digital input signal (D0 to Dn-1) when +, Vref-) is applied. Parameter setting means (1) capable of setting a plurality of circuit parameters for a predetermined circuit parameter for determining the output state, and setting the desired circuit parameter by controlling the parameter setting means (1) based on a control signal. And a setting control means (2) for controlling the digital-analog converter.