JPH056954A - Semiconductor integrated circuit package - Google Patents

Semiconductor integrated circuit package

Info

Publication number
JPH056954A
JPH056954A JP15730391A JP15730391A JPH056954A JP H056954 A JPH056954 A JP H056954A JP 15730391 A JP15730391 A JP 15730391A JP 15730391 A JP15730391 A JP 15730391A JP H056954 A JPH056954 A JP H056954A
Authority
JP
Japan
Prior art keywords
ground
package
terminal
wiring board
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15730391A
Other languages
Japanese (ja)
Inventor
Hitoshi Ishizuki
仁 石附
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15730391A priority Critical patent/JPH056954A/en
Publication of JPH056954A publication Critical patent/JPH056954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To suppress a generation of noise and uniformize characteristic impedance of signal patterns by a method wherein a ground terminal is connected to a ground layer of an IC package and the ground layer plane is plane- connected to a ground conductive pad provided on the surface of a printed wiring board. CONSTITUTION:Each terminal of a power supply excluding a signal and a ground of an IC chip 2 is connected to a pad 9 on the surface of a printed wiring board 8 through a connecting line 3 between IC packages, an internal conductive pattern 5, and an external lead line 6. Further, each terminal is connected to the other signal terminal and a power supply layer through a conductive pattern 10 within the printed wiring board, respectively. Also, a ground terminal of the IC chip 2 is connected to a package ground layer 1 through the connecting line 3 between the IC packages and an internal ground connecting pattern 11. Thus, it becomes possible to rise a ground potential by a portion of a resistance and inductance exsisting in the external lead line and to suppress a generation of operating noise.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体集積回路パッケー
ジ、特に、多ピン表面実装用半導体集積回路パッケージ
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit package, and more particularly to a multi-pin surface mount semiconductor integrated circuit package.

【０００２】[0002]

【従来の技術】従来、この種の半導体集積回路パッケー
ジでは信号電位の基準となるグランド端子の外部リード
線は入出力信号端子や電源端子と同様の形状をしてお
り、プリント配線板に、信号端子と同様に、半田付等に
より各端子が接続されている。2. Description of the Related Art Conventionally, in this type of semiconductor integrated circuit package, the external lead wire of the ground terminal, which serves as a reference for the signal potential, has the same shape as the input / output signal terminal and the power supply terminal. Similar to the terminals, the terminals are connected by soldering or the like.

【０００３】[0003]

【発明が解決しようとする課題】上述した従来の半導体
集積回路パッケージでは、内部に収納する半導体集積回
路の信号多ピン化、高集積化がすすむと、同時動作によ
るノイズが発生し、信号電位の基準となるグランド端子
にノイズがのり、誤動作をおこす可能性が高くなる。ま
た高集積化により消費電流の増加は、パッケージリード
線自身の抵抗により、パッケージのグランド層の電位上
昇を引きおこし、これも誤動作の原因となる欠点があ
る。In the above-described conventional semiconductor integrated circuit package, when the number of pins of the semiconductor integrated circuit housed inside is increased and the degree of integration is increased, noise is generated due to the simultaneous operation and the signal potential of the There is a high possibility that noise will be applied to the reference ground terminal and cause a malfunction. Further, the increase in current consumption due to high integration causes a rise in the potential of the ground layer of the package due to the resistance of the package lead wire itself, which also causes a malfunction.

【０００４】またパッケージの大型化を抑えようと、グ
ランド端子を増やさずに信号端子のみを増やそうとする
と、上記で説明したノイズによる影響がでやすくなり、
回路動作の信頼性が悪化する欠点がある。特に集積回路
を高速で動作させると信頼性の悪化は顕著に現れる。Further, if the number of signal terminals is increased without increasing the number of ground terminals in order to prevent the package from increasing in size, the above-mentioned noise is apt to cause the influence.
There is a drawback that the reliability of circuit operation deteriorates. In particular, when the integrated circuit is operated at high speed, the reliability is significantly deteriorated.

【０００５】[0005]

【課題を解決するための手段】本発明の集積回路パッケ
ージは、ＩＣチップのグランド端子が接続されているＩ
Ｃパッケージ内グランド導体と電気的接続をもつよう、
ＩＣパッケージ表面に設けられた導体層を有し、前記表
面導体層はＩＣパッケージがプリント板の実装される時
には、プリント配線板と向かい合う方向で実装される構
造を有している。In the integrated circuit package of the present invention, the ground terminal of the IC chip is connected to I
In order to have an electrical connection with the ground conductor in the C package,
There is a conductor layer provided on the surface of the IC package, and the surface conductor layer has a structure in which when the IC package is mounted on a printed board, the surface conductor layer is mounted in a direction facing the printed wiring board.

【０００６】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例の縦断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a vertical sectional view of an embodiment of the present invention.

【０００７】ＩＣチップ２の信号，電源（グランドを除
く）の各端子はＩＣパッケージ間接続線３、内部導体パ
ターン５，外部リード線６を介してプリント配線基板８
表面のパッド９と接続され、さらにプリント配線板内導
体パターン１０を介して、それぞれ他信号端子，電源層
に接続されている。Each signal and power (excluding ground) terminal of the IC chip 2 is connected to the printed wiring board 8 via the IC package connecting line 3, the internal conductor pattern 5, and the external lead wire 6.
It is connected to the pad 9 on the front surface, and is further connected to other signal terminals and the power supply layer via the conductor pattern 10 in the printed wiring board.

【０００８】ＩＣチップ２のグランド端子は、ＩＣパッ
ケージ間接続線３，内部グランド接続パターン１１を介
して、パッケージグランド層１と接続がなされている。
パッケージグランド層１はパッケージがプリント板に実
装された時に、プリント板に近い方の面の表面に構成さ
れ、プリント板の半田等により面接続され、ＩＣパッケ
ージ４とプリント配線板８の電気的グランド接続がされ
る。The ground terminal of the IC chip 2 is connected to the package ground layer 1 via the inter-IC-package connection line 3 and the internal ground connection pattern 11.
The package ground layer 1 is formed on the surface of the side closer to the printed board when the package is mounted on the printed board, and is surface-connected by solder or the like of the printed board, and the electrical ground of the IC package 4 and the printed wiring board 8 is formed. The connection is made.

【０００９】[0009]

【発明の効果】以上説明したように本発明はＩＣチップ
の信号電位の基準となるグランド端子を入出力信号端子
とは別にＩＣパッケージのグランド層と接続し、そのグ
ランド層をＩＣパッケージ表面に構成させ、そのグラン
ド層面をプリント配線板表面に用意されたグランド導体
パッドと面接触させることにより、ＩＣパッケージとプ
リント板とのグランドの接触面積がリード線による接触
時より大きくなり、外部リード線が有する抵抗およびイ
ンダクタンス分によるグランド電位の上昇と動作ノイズ
の発生を抑えることが可能となる。As described above, according to the present invention, the ground terminal serving as the reference of the signal potential of the IC chip is connected to the ground layer of the IC package separately from the input / output signal terminal, and the ground layer is formed on the surface of the IC package. Then, the ground layer surface is brought into surface contact with the ground conductor pad prepared on the surface of the printed wiring board, so that the contact area of the ground between the IC package and the printed board becomes larger than that at the time of contact by the lead wire, and the external lead wire has it. It is possible to suppress the rise of the ground potential and the generation of operating noise due to the resistance and the inductance.

【００１０】また全信号導体パターンはパッケージ内部
において常にグランド層と近接できるため特性インピー
ダンスを均一化でき、電気的特性の改善につながる効果
がある。また、パッケージグランドとプリント配線板と
の接触面積は十分大きいため、信号ピンが増加した場合
でも、グランド端子を増加させる必要が無いため、高密
度実装に適する効果がある。Further, since all the signal conductor patterns can always be close to the ground layer inside the package, the characteristic impedance can be made uniform, and the electrical characteristics can be improved. Further, since the contact area between the package ground and the printed wiring board is sufficiently large, it is not necessary to increase the number of ground terminals even if the number of signal pins is increased, which is suitable for high-density mounting.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す縦断面図である。FIG. 1 is a vertical sectional view showing an embodiment of the present invention.

【図２】従来の一例を示す縦断面図である。FIG. 2 is a vertical cross-sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

１ グランド層 ２ チップ ３ 接続線 ４ パッケージ ５ 内部導体パターン ６ 外部リード線 ７ グランド層 ８ プリント配線板 ９ 板表面パッド １０ 導体パターン １１ グランド接続パターン 1 Ground Layer 2 Chip 3 Connection Line 4 Package 5 Internal Conductor Pattern 6 External Lead Wire 7 Ground Layer 8 Printed Wiring Board 9 Board Surface Pad 10 Conductor Pattern 11 Ground Connection Pattern

Claims (1)

【特許請求の範囲】 【請求項１】 高密度表面実装用半導体集積回路（以下
ＩＣと呼ぶ）パッケージにおいて、導体でできたグラン
ド層をパッケージ表面に構成させ、表面導体をプリント
板のグランドパッドと面接続することにより、ＩＣチッ
プのグランド端子と電気的に接続されているＩＣパッケ
ージのグランド層プリント板のグランド層の電気的接続
を行なうことを特徴とする半導体集積回路パッケージ。Claim: What is claimed is: 1. In a semiconductor integrated circuit (hereinafter referred to as IC) package for high density surface mounting, a ground layer made of a conductor is formed on the package surface, and the surface conductor serves as a ground pad of a printed board. A semiconductor integrated circuit package characterized in that a ground layer of a printed circuit board of an IC package electrically connected to a ground terminal of an IC chip is electrically connected by surface connection.
JP15730391A 1991-06-28 1991-06-28 Semiconductor integrated circuit package Pending JPH056954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15730391A JPH056954A (en) 1991-06-28 1991-06-28 Semiconductor integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15730391A JPH056954A (en) 1991-06-28 1991-06-28 Semiconductor integrated circuit package

Publications (1)

Publication Number Publication Date
JPH056954A true JPH056954A (en) 1993-01-14

Family

ID=15646718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15730391A Pending JPH056954A (en) 1991-06-28 1991-06-28 Semiconductor integrated circuit package

Country Status (1)

Country Link
JP (1) JPH056954A (en)

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