JPH056896A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve high speed operating characteristics in a bipolar transistor having features in an interelement isolating region and a collector region and a method for manufacturing the same. CONSTITUTION:A LOCOS oxide film 4 is formed on a semiconductor substrate 1, a recess so retaining the film 4 on a periphery as to be larger than a region of the substrate 1 in which the film 4 is not formed, a metal silicide film 6 is formed on the surface of the substrate 1 exposed in the recess, and a polycrystalline semiconductor layer 7 is formed thereon. The layer 7 remains only in the recess to be flattened, an impurity is implanted to reduce its resistance, and an insulating film 8 is formed on the flattened layer 7. A supporting substrate 9 is adhered to the film 8, the back surface of the substrate 1 is polished until the film 4 is exposed, the substrate 1 remaining in the polishing step is used as a collector region, and the metal silicide film is so formed as to lead it as a collector leading region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor having a device isolation region and a collector region, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 is a diagram for explaining the structure of a conventional bipolar transistor. In this figure, 31 is a p-type semiconductor substrate, 32 is an n ⁺ -type buried layer, 33 is an n-type collector region, 34 is a p ⁺ -type region, 35 is a p-type base region, and 36.
Is an n ⁺ type emitter region, 37 is ap ⁺ type base extraction region, 38 is an n ⁺ type collector extraction region, 39 is a base electrode, 40 is an emitter electrode, and 41 is a collector electrode.

As shown in FIG. 4, in the conventional bipolar transistor, the bottom surface and the side surface of the collector region are separated from other regions by a pn junction. Since it can be added from one side of the substrate, it was easy to integrate a plurality of bipolar transistors.

[0004]

However, since the above-mentioned conventional bipolar transistor is separated from other regions by the pn junction, its parasitic capacitance cannot be ignored, and due to its structure. Since the collector region and the collector extraction region, which are extended for a long time, are formed by diffusion of impurities, the extraction resistance cannot be ignored, and there is a problem in increasing the speed of a circuit incorporating the same.

[0005]

In the bipolar transistor according to the present invention, in order to solve the above-mentioned problems, the bottom surface and side surfaces of the collector region are surrounded by an insulating film, and the extraction region from the collector region is made of metal. A structure that is a silicide film is adopted.

Further, in the method for manufacturing a bipolar transistor according to the present invention, a step of forming a LOCOS oxide film for element isolation on a semiconductor substrate, and a semiconductor substrate on which the LOCOS oxide film is not formed A region having a larger opening than the above region and having an opening left for leaving the LOCOS oxide film, a step of etching away the LOCOS oxide film using the resist film as a mask to form a recess, and a step of forming a recess in the recess. A step of forming a metal silicide film on the exposed surface of the semiconductor substrate, a step of depositing a polycrystalline semiconductor layer on the entire surface of the semiconductor substrate, and a step of flattening the polycrystalline semiconductor layer leaving the polycrystalline semiconductor layer only in the concave portions. A step, a step of introducing a high concentration impurity into the polycrystalline semiconductor layer, and a step of forming an insulating film on the planarized polycrystalline semiconductor layer A step of adhering a supporting substrate to the insulating film, a step of polishing the back surface of the semiconductor substrate until the LOCOS oxide film is exposed, and a semiconductor substrate left by the polishing step as a collector region, and a metal silicide film A structure including a step of pulling out as a collector lead-out area is adopted.

In another method of manufacturing a bipolar transistor according to the present invention, the step of forming a LOCOS oxide film for element isolation on the semiconductor substrate and the step of not forming the LOCOS oxide film on the semiconductor substrate. A step of forming a resist film having an opening larger than a region of the semiconductor substrate and having an opening for leaving the LOCOS oxide film around, a step of etching and removing the LOCOS oxide film using the resist film as a mask to form a concave part; A step of forming a metal silicide film on the exposed surface of the semiconductor substrate, a step of depositing an insulating film on the entire surface of the semiconductor substrate, a step of flattening the surface of the insulating film, and a step of forming the flattened insulating film. The step of attaching the support substrate on top and the rear surface of the semiconductor substrate
A step of polishing until the OCOS oxide film is exposed, and the semiconductor substrate left by the polishing step is used as a collector region,
A structure including a step of drawing out the metal silicide film as a collector extraction region is adopted.

[0008]

By adopting the structure of the present invention, that is, since the bipolar transistor is separated from the other regions by the insulating film, the parasitic capacitance can be reduced, and
Since the extraction region from the collector region is extracted by the metal silicide film, the collector resistance is reduced, and as a result, the high speed operation characteristics of the bipolar transistor can be improved. Further, by adopting the manufacturing method of the present invention, the bipolar transistor described above can be manufactured efficiently and with high yield.

[0009]

EXAMPLES Examples of the present invention will be described below. (First Embodiment) FIGS. 1A to 1D and 2E to
(G) is a manufacturing process explanatory view of the first embodiment of the present invention.

In this figure, 1 is a Si substrate, 2 is a pad oxide film, 3 is a CVD nitride film, 4 is a LOCOS oxide film,
5 is a resist pattern, 6 is a TiSi ₂ film, 7 is a polycrystalline Si layer, 8 is an oxide film, 9 is a silicon support substrate, and 10 is n.
⁺ Region, 11 is an oxide film, 12 is a base region, 13 is an emitter region, 14 is an oxide film, 15 is a base electrode, 16 is a polycrystalline Si layer, 17 is an emitter electrode, and 18 is a collector electrode 18. The manufacturing process of the first embodiment will be sequentially described with reference to this drawing.

First step (see FIG. 1A) After a pad oxide film 2 having a thickness of 20 nm and a CVD nitride film 3 having a thickness of 150 nm are formed on the entire surface of an n-type Si substrate 1, these two layers are formed. Applying photolithography technology to
Patterning is performed to define a bipolar transistor formation region, and the Si substrate 1 is thermally oxidized using this as a mask to form a LOCOS oxide film 4 having a thickness of 800 nm.

Second step (see FIG. 1B) The pad oxide film 2 and the CVD nitride film 3 left in the previous step are removed and a photolithography technique is used to
A resist pattern 5 is formed which is larger than the region of the Si substrate where the LOCOS oxide film is not formed and has an opening around which the LOCOS oxide film is left. Then, the exposed LOCOS oxide film 4 is removed by etching using the resist pattern 5 as a mask to form a recess.

Third step (see FIG. 1C) A TiSi ₂ film 6 having a thickness of 100 nm is formed on the entire upper surface by a sputtering method, and is patterned by using a photolithography technique to form a plateau portion in the recess. T around it
The iSi film 6 is left. This metal silicide is Ti
Not only Si ₂ but also other metal silicides such as TaSi ₂ and MoSi ₂ can be used.

Fourth Step (see FIG. 1D) After depositing a polycrystalline Si layer 7 having a thickness of 800 nm by the CVD method, the polycrystalline Si layer 7 is polished and flattened. During this polishing, the upper edge of the LOCOS oxide film 4 acts as a polishing stopper. Next, polycrystalline Si
The layer 7 is doped with arsenic (As) by the ion implantation method to reduce the resistance of the collector region formed later.

Fifth step (see FIG. 2 (E)) An oxide film (SiO ₂ ) or BPSG 8 having a thickness of about 1 μm is deposited thereon by a CVD method, and 1 is formed thereon.
The silicon support substrate 9 is attached at a temperature of about 000 ° C. By the heat treatment of this bonding step, polycrystalline Si
As in the layer 7 is diffused into the Si substrate 1 to form the n ⁺ region 10.

Step 6 (see FIG. 2F) The Si substrate 1 is polished and removed until the surface of the LOCOS oxide film 4 is exposed. In this polishing process, LOCOS
The oxide film 4 serves as a stopper.

Step 7 (see FIG. 2G) An oxide film 11 having an opening is formed on the remaining Si substrate 1 which will be a collector region, and p-type Si is epitaxially grown on the oxide film 11 to form a base region 12. To do. By this epitaxial growth, a single crystal grows on the single crystal Si substrate 1, but polycrystalline Si grows on the oxide film 11.

An n-type emitter region 13 is formed thereon by a mask diffusion method. An oxide film 14 is formed thereon, and a base electrode 15 is extended to the base region 12, an emitter extraction region 16 and an emitter electrode 17 made of a polycrystalline Si layer are extended to the emitter region 13, and the bottom of the collector region 1 is extended. A collector electrode 18 is formed on the TiSi ₂ film 6.

(Second Embodiment) FIGS. 3A to 3D are explanatory views of a manufacturing process of a second embodiment of the present invention. In this figure, 21 is a Si substrate, 22 is a pad oxide film, and 23 is C.
VD nitride film, 24 LOCOS oxide film, 25 TiSi
_{2 is a} film, 26 is As, 27 is an n ⁺ region, and 28 is a SiO ₂ film. The manufacturing process of the second embodiment will be described with reference to this drawing.

First step (see FIG. 3A) A pad oxide film 22 having a thickness of 20 nm and a CVD nitride film 23 having a thickness of 150 nm are formed on a part of the n-type Si substrate 21 and used as a mask. Then, the surface of the Si substrate 21 is thermally oxidized to form an LOCOS oxide film 24 having a thickness of 800 nm.

Second step (see FIG. 3B) Pad oxide film 22 used as a mask in the previous step
And the CVD nitride film 23 are removed, and a LOCOS oxide film is not formed on the Si by using the photolithography technique.
A resist pattern having an opening larger than the substrate region and having a LOCOS oxide film around it is formed, and the exposed LOCOS oxide film 24 is removed by etching to form a recess.

TiSi having a thickness of 100 nm is formed on the entire upper surface thereof.
₂ film is formed and patterned by using photolithography technology.
The Si film 25 is left and the TiSi film in other regions is removed.
From above, As 26 is ion-implanted at a dose of about 5 × 10 ¹⁵ / cm ⁻² to form an n ⁺ region 27.

Third step (see FIG. 3C) SiO _{2 having} a thickness of about 1 μm is formed thereon by the CVD method.
The film 28 is deposited.

Fourth Step (see FIG. 3D) The surface of the SiO ₂ film 28 deposited in the previous step is polished and flattened. After the step of adhering the support substrate to the flattened surface of the SiO ₂ film 28, the steps are substantially the same as the steps described after the fifth step (FIG. 2E) of the first embodiment. This second embodiment is different from the first embodiment in that the polycrystalline Si layer 7 is
This corresponds to the one in which the step of depositing (see FIG. 1D) is omitted, and the number of manufacturing steps can be reduced accordingly.

In the first and second embodiments described above,
Although an npn-type transistor has been illustrated, the present invention is not limited to pn.
The same applies to p-type transistors. Further, not only Si but also other semiconductor materials can be appropriately adopted.

[0026]

As described above, according to the present invention,
Since the periphery of the collector region of the bipolar transistor can be surrounded by an insulating film, the parasitic capacitance can be reduced. Furthermore, since the collector extraction electrode is made of metal silicide, the collector resistance can be reduced. As a result, the high speed operation characteristics of the bipolar transistor can be reduced. It is possible to make a great contribution to the technical fields of computers, communication, control, etc., where the improvement of high speed operation characteristics is strongly required. Also,
According to the manufacturing method of the present invention, the bipolar transistor described above can be manufactured efficiently and with high yield.

[Brief description of drawings]

1A to 1D are explanatory views (1) of a manufacturing process of a first embodiment of the present invention.

2 (E) to (G) are explanatory views (2) of the manufacturing process of the first embodiment of the present invention.

FIG. 3 is a drawing explaining the manufacturing process of the second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a configuration of a conventional bipolar transistor.

[Explanation of symbols]

1 Si substrate 2 Pad oxide film 3 CVD nitride film 4 LOCOS oxide film 5 Resist pattern 6 TiSi ₂ film 7 Polycrystalline Si layer 8 Oxide film 9 Silicon support substrate 10 Arsenic 11 Oxide film 12 Base region 13 Emitter region 14 Oxide film 15 base Electrode 16 Polycrystalline Si layer 17 Emitter electrode 18 Collector electrode

Claims (3)

[Claims] 1. A bipolar transistor, wherein a bottom surface and a side surface of a collector region are surrounded by an insulating film, and a region extracted from the collector region is a metal silicide film. 2. A LOCOS for element isolation on a semiconductor substrate
Forming an oxide film, and forming the LOC on the semiconductor substrate.
A step of forming a resist film having an opening larger than a region of the semiconductor substrate where the OS oxide film is not formed and having an opening for leaving the LOCOS oxide film in the periphery; and etching and removing the LOCOS oxide film using the resist film as a mask to form a recess Forming a metal silicide film on the surface of the semiconductor substrate exposed in the recess, depositing a polycrystalline semiconductor layer over the entire surface of the semiconductor substrate, and leaving the polycrystalline semiconductor layer only in the recess. Planarizing the polycrystalline semiconductor layer, introducing a high concentration impurity into the polycrystalline semiconductor layer, forming an insulating film on the planarized polycrystalline semiconductor layer, A step of adhering a supporting substrate to the insulating film; a step of polishing the back surface of the semiconductor substrate until the LOCOS oxide film is exposed; And method for producing a bipolar transistor which comprises a step of pulling out said metal silicide film as the collector lead-out region. 3. A LOCOS for element isolation on a semiconductor substrate
Forming an oxide film, and forming the LOC on the semiconductor substrate.
A step of forming a resist film having an opening larger than a region of the semiconductor substrate where the OS oxide film is not formed and having an opening for leaving the LOCOS oxide film in the periphery; and etching and removing the LOCOS oxide film using the resist film as a mask to form a recess A step of forming a metal silicide film on the surface of the semiconductor substrate exposed in the recess, a step of depositing an insulating film on the entire surface of the semiconductor substrate, and a step of flattening the surface of the insulating film. Bonding a support substrate on the planarized insulating film, polishing the back surface of the semiconductor substrate until the LOCOS oxide film is exposed, and using the semiconductor substrate left by the polishing process as a collector region, A method of manufacturing a bipolar transistor, comprising the step of drawing out the metal silicide film as a collector extraction region.