JPH0567978B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is based on the same basic computing elements (hereinafter referred to as PE
(abbreviated as ) are connected to each other, and these
The present invention relates to a parallel data processing device in which PEs are operated simultaneously by the same control signal from one control unit, and particularly relates to speeding up shift operations in the device.

[Conventional technology]

Figures 3 and 4 are for example Paul A. Gilmore,
“The massively parallel processor (MPP):
a large scale SIMD Processor”,
PROCEEDINGS of SPIE The International
Society for Optical Engineering,
This is a block diagram of a conventional parallel data processing device based on the content shown in vol. 431 August 23-25, 1983, PP 166-174.

FIG. 3 shows the overall configuration of a conventional parallel data processing device. In the figure, 1 is a PE which is a basic calculation element, 2 is a calculation unit consisting of a plurality of PEs 1 with adjacent PMs connected, 3 is each of the calculation unit 2
A controller 5 controls the PE 1 using the same control signal 4 composed of various clocks, etc., and an external memory 5 stores instructions and data input to and output from the arithmetic unit 2 and the controller 3.

FIG. 4 is an internal configuration diagram of each PE 1, and in the figure, 6 is a computing unit constituting computing means;
Its output side is connected to internal data bus B. 7 is a selector that selects data from adjacent PEs; 8 is a local memory connected to internal data bus B and constitutes a data storage means; 9 is a selector for each PE;
This is a mask register for individually specifying execution or non-execution, and is connected to internal data bus B and
The write clock is one of the control signals 4 from
Writing is controlled by WCLK1, and the written content (“0” or “1”) is output as a mask signal MASK to each part within the PE. 10 is a shift register of a predetermined number of bits connected to the internal data bus B and the arithmetic unit 6; the output of the logic circuit 11 receives the write clock WCLK2 from the control unit 3 and the mask signal MASK from the mask register 9; The writing is controlled by the control section 3, and the shift operation is controlled by the output of the logic circuit 12 which receives the shift register SCLK from the control section 3 and the mask signal MASK. 13 is a register connected to the PE adjacent to the selector 7, internal data bus B, and arithmetic unit 6;
Writing is controlled by the output of a logic circuit 14 which receives WCLK3 and a mask signal MASK as inputs.

Next, the operation will be explained. When the control signal 4 from the control unit 3 is given to each PE 1 in common and at the same time, a mask register 9 that specifies whether or not to execute
Only the PE whose content is "0" performs the operation according to the control signal 4 simultaneously in parallel with each PE.

For example, when data read from the local memory 8 and stored in the shift register 10 is to be shifted by the same number of bits to all PEs, the control unit 3 supplies the shift clock SCLK to all PEs in common by the number of shifts. At this time, no shift operation is performed for PEs whose contents in the mask register 9 are "1".

On the other hand, if it is desired to shift a different number of bits in each PE, first the shift number is stored in the register 13 from the local memory 8, and the contents of the register 13 are decreased by 1 by the arithmetic unit 6. At the same time,
Shift the contents of shift register 10 by 1 bit. As mentioned above, at this time mask register 9
A shift is not performed in a PE whose content is "1". Next, the register 13 is
and zero, and write the result to the mask register 9. As a result of this operation, "1" is written to the mask register 9 of the PE whose register 13 has zero content, and the shift register 10 of that PE will not be shifted thereafter. Shift register 1 performs this kind of operation.
By performing the shift operation for the number of 0 bits, it is possible to perform a shift operation with a different number of shifts for each PE.

[Problem that the invention seeks to solve]

Conventional parallel data processing devices are configured as described above, so when performing a shift operation with a different number of bits for each PE based on the data stored in each PE, the number of shifts in all PEs is If the maximum value of is smaller than the number of bits in the shift register in PE, it requires clock cycles to shift by the number of bits in the shift register.
There was a problem in that the difference between the number of bits in the shift register and the maximum value of the number of shifts in all PEs caused waste, and the shift operation could not be performed at high speed.

This invention was made to solve the above-mentioned problems. When performing a shift operation with a different number of bits for each PE based on the data stored in each PE, the number of shifts in all PEs is The object of the present invention is to provide a parallel data processing device that can perform a high-speed shift operation using only the maximum number of clock cycles.

[Means for solving problems]

In the parallel data processing device according to the present invention, each basic operation element (PE) of the operation unit includes a shift counter in which the number of shifts of data to be stored in a shift register is stored and is decremented for each shift, and the contents of the shift counter. The controller is provided with a zero detection means for detecting whether the zero detection means of each basic arithmetic element (PE) has become zero, and an AND circuit that takes the AND of the detection signals output from the zero detection means of each basic arithmetic element (PE); A control means for terminating the shift operation in response to an output signal from the product circuit is provided.

[Effect]

The parallel data processing device according to the present invention decrements the value set in advance in the shift counter in each PE simultaneously with the shift operation using a common control signal from the control section. When the value of the shift counter becomes zero, the zero detection means detects it and each
The logical product of the detection signals output from the zero detection means in the PE is determined by the logical product circuit in the control section, and the output signal is input to the control means for terminating the shift operation. As a result, the shift operation ends when the contents of the shift counters of all PEs become zero.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Note that the same reference numerals are used for the same or corresponding parts as in the conventional example described above, and the explanation thereof will be omitted.

FIG. 1 is an internal configuration diagram of each PE (basic calculation element) 1 constituting the calculation unit 2. In the figure, 15 is connected to the internal data bus B, and the number of shifts of data stored in the shift register 10 is stored, 1
A shift counter 16 is decremented each time a bit is shifted, and 16 is a zero detection circuit constituting the zero detection means of the present application that detects whether the contents of the shift counter 15 have become zero. This detection signal 17 is sent to the control section 3 and is configured to be input to the logic circuit 12a that controls the shift operation of the shift register 10. That is, the shift register 10 performs a shift operation based on the shift clock from the control unit 3.
Mask signal from SCLK and mask register 9
MASK and detection signal 17 from zero detection circuit 16
Controlled by In addition, the mask signal MASK
is “1”, the detection signal 1 of the zero detection circuit 16
7 and is always set to "1".

FIG. 2 is an overall configuration diagram of the embodiment, and in the figure, 20 is located in the control unit 3, and 21 is an AND circuit that takes the AND of the detection signals 17 sent out from the zero detection circuit 16 of each PE 1. Also in the control unit 3, the output signal 22 of the AND circuit 20 is “1”
In this case, that is, when the contents of the shift counters 15 of all PEs are zero, this is a control circuit that generates a control signal 4 that terminates the shift operation and instructs the next operation, and corresponds to the control means in the present application.

Next, based on the configuration of the embodiment shown in FIGS. 1 and 2, we will explain the effect when shifting a different number of bits for each PE based on the data stored in each PE. do.

First, the shift number stored in the local memory 8 is stored in the shift counter 15 as the maximum value of the number of bits in the shift register 10. Next, 1
For each clock, a shift clock SCLK common to all PEs is applied to the shift register 10, and the value of the shift counter 15 is decremented by one. At this time, in the PE where the contents of the mask register 9 are "1", the shift register 10 is not shifted and the shift counter 15 is not decremented, and the detection signal 17 of the zero detection circuit 16 is always "1". There is. on the other hand,
The detection signal 17 of the zero detection circuit 16 of the PE whose shift counter 15 has become zero becomes "1" and is sent to the control section 3 and the AND circuit 12a, and is thereafter
No shift operation is performed in PE. When the detection signal 17 of the zero detection circuit 16 of all PEs becomes "1", the output signal 22 of the AND circuit 20 in the control section 3
becomes “1”, and upon receiving this signal, the control circuit 21
stops generation of the shift clock SCLK and generates a control signal 4 instructing the next operation.

Therefore, for example, if the number of bits of the shift register 10 is 16, and the arithmetic unit Z2 is composed of four PE1s, the number of shifts stored in the shift counter 15 of each PE1 is "1" and "2", respectively. ”, “3”,
Assuming "4", in the conventional parallel data processing device, the number of shifts for all PEs 1 is not known in the control unit 3, so 16 clocks are required for the shift operation, whereas in the parallel data processing device according to the present invention, 16 clocks are required for the shift operation.
A shift operation can be performed with four clocks, which is the maximum number of shifts.

〔Effect of the invention〕

As described above, according to the present invention, each basic arithmetic element (PE) of the arithmetic unit includes a shift counter that stores the number of shifts of data to be stored in a shift register and is decremented for each shift; The controller is provided with a zero detection means for detecting whether the content of has become zero, and an AND circuit that takes the logical product of the detection signals output from the zero detection means of each basic arithmetic element (PE). , and control means for terminating the shift operation by the output signal of this AND circuit, and when performing a shift operation with a different number of bits for each PE based on the data stored in each PE, all PEs Since the shift operation is configured so that the shift operation can be performed with the maximum number of clocks among the shift numbers specified in the above, there is an effect that the shift operation can be performed at high speed with simple control.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the internal configuration of each PE in a parallel data processing device according to an embodiment of the present invention, FIG. 2 is an overall configuration diagram of a parallel data processing device according to an embodiment of the present invention, and FIG. The overall configuration of the data processing device, Figure 4 shows each of the conventional parallel data processing devices.
It is a block diagram inside PE. In the figure, 1 is PE (basic calculation element), 2 is calculation unit,
3 is a control unit, 4 is a control signal, 5 is an external memory, 6
is an arithmetic unit (arithmetic means), 7 is a selector, 8 is a local memory (data storage means), 9 is a mask register, 10 is a shift register, 11, 12a, 1
4 is a logic circuit, 13 is a register, 15 is a shift counter, 16 is a zero detection circuit (zero detection means),
17 is a detection signal, 20 is an AND circuit, and 21 is a control circuit (control means). In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. An arithmetic section formed by connecting a plurality of basic arithmetic elements having arithmetic means for performing arithmetic operations on data in registers including shift registers, and data storage means for accumulating data to be stored in the registers, etc., and this arithmetic section. and a control section that controls each basic operation element of the above operation section using the same control signal, the number of shifts of data to be stored in the shift register is stored in each basic operation element of the operation section. A shift counter that is decremented every time a shift is provided, and a zero detection means that detects whether the contents of this shift counter become zero are provided. 1. A parallel data processing device comprising: an AND circuit that takes an AND of detection signals; and a control means that terminates a shift operation based on an output signal of the AND circuit.