JPH0567619A - Semiconductor with bump formation region - Google Patents

Abstract

PURPOSE:To constitute a semiconductor device on which a highly reliable bump electrode can be formed easily and quickly. CONSTITUTION:N-type wells 2 and P-type diffusion layers 4 are provided on the part directly below each bump forming region 11 of a signal input part 13 and the bump forming region 14 for substrate contact of a semiconductor substrate 1. An electrically reverse-directioned P-N junction, which is formed by N-type wells 2 and the semiconductor substrate 1, is brought into a conductive state by application of a light beam, and highly reliable bump electrodes can be formed easily and quickly on all the bump forming regions 11 on the semiconductor device simultaneously by supplying a plating current. After the bump electrodes have been formed the bump forming part 14 for substrate contact and the bonding region 12 of a substrate contact part 15 are connected by bonding, and the bump electrode for substrate contact is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bump forming region.

[0002]

2. Description of the Related Art For example, a hybrid infrared sensor is
It is manufactured by combining a photoelectric conversion semiconductor chip in which an infrared detecting element is arranged on a semiconductor substrate and a silicon IC semiconductor chip in which a signal processing circuit for processing an output signal of the photoelectric conversion semiconductor chip is formed. When connecting such semiconductor chips electrically and mechanically, usually, bump electrodes made of a soft metal such as indium are formed on both semiconductor chips, and the bump electrodes are aligned with each other. There is a method of thermocompression bonding.

FIG. 2 is a side sectional view of a semiconductor device having a conventional bump formation region. In the figure, the signal input unit 1
3 is connected to the signal input electrode 6 provided on the n ⁺ diffusion layer 3, and the bump formation region 11 of the substrate contact portion 15 is a substrate contact electrode provided on the P ⁺ diffusion layer 4. 8 is connected.

The following two methods are generally used to form bump electrodes in the bump forming region 11. First, a plating base metal is provided on the surface of the semiconductor device by a vacuum vapor deposition method, a photoresist film having an opening is formed in a region including the bump forming region 11, and a plating current is supplied from the plating base metal to form an inside of the opening. After forming a soft metal such as indium as a bump electrode on the above metal film, the plating base metal film is selectively removed by etching using the bump electrode as a mask to electrically separate each element and form the bump electrode. Is the way to do it. Second, first, a photoresist film having an opening is formed in a region including a bump formation region of a substrate contact portion, a plating base metal is vacuum-deposited, and then the photoresist film is removed. Next, a photoresist film having an opening in a region on the plating base metal was formed, a plating current was supplied from the substrate connector electrode, and a soft metal such as indium was laminated as a bump electrode on the opening on the plating base metal. After that, the photoresist is removed. The same steps as those performed on the substrate contact portion are performed on the signal input portion to form bump electrodes in the bump formation region of the signal input portion. However, the plating current is supplied from the substrate connector electrode through the semiconductor substrate, but since the Pn junction of the signal input portion is configured in the electrically non-conducting direction, light is emitted from the outside so that the current flows. There is a need to.

[0005]

However, the bump formation of the semiconductor device having the conventional bump formation region described above has the following problems.

In the above-described first bump electrode forming method, when the plating base metal is etched, the bump electrode itself is also etched, and the plating base metal film immediately below the bump electrode is corroded from its surroundings to connect the bump electrodes. Strength is reduced. Further, the surface protective film is also slightly etched, which deteriorates the element characteristics of the semiconductor device.

Further, in the above-mentioned second bump electrode forming method, it is necessary to form the bumps of the signal input portion and the substrate contact portion in separate steps, which takes time, and the signal input portion and the substrate contact portion are formed. It is extremely difficult to form bump electrodes having the same height and the same shape.

As described above, when the bump electrode is formed on the conventional semiconductor device, there are problems that the process becomes complicated, the process takes time, and the reliability is lowered.

The object of the present invention is to eliminate such problems,
It is an object of the present invention to provide a semiconductor device having a bump forming region in which a bump forming process can be simplified and a bump electrode having higher reliability and higher reliability than before can be formed.

[0010]

The semiconductor device of the present invention comprises:
On a semiconductor substrate on which an integrated circuit is formed, a first bump formation region connected to a signal input electrode of a signal input unit and provided on a P ⁺ diffusion layer of an N-type well, and a substrate for a bump formation unit for substrate contact A second bump forming region connected to the contact bump electrode and provided on the N-type well P ⁺ diffusion layer, a first bonding region connected to the substrate contact bump electrode, and a P ⁺ diffusion region of the substrate contact portion. A second bonding region connected to the substrate contact electrode provided on the layer.

[0011]

1 is a side sectional view of an embodiment of the present invention.
In the figure, on the semiconductor substrate 1, the bump formation region 11 and the n ⁺ diffusion layer 3 which are connected to the signal input electrode 6 and are provided on the P ⁺ diffusion layer 4 of the N-type well 2 and the gate electrode 9 are formed. Signal input portion 13, a bump formation region 11 connected to the substrate contact bump electrode 7 and provided on the P ⁺ diffusion layer 4 of the N-type well 2, and a bonding region 12 connected to the substrate contact bump electrode 7. A bump forming portion 14 for substrate contact, and P ⁺ on the semiconductor substrate 1.
Substrate contact portion 1 having bonding region 12 connected to substrate contact electrode 8 provided on diffusion layer 4
And 5 are formed.

With this structure, a photoresist film having an opening is formed in a region including the bump forming region 11 of the signal input unit 13 and the substrate contact bump forming unit 14, and the plating base metal is vacuum-deposited. After that, the photoresist is removed, a photoresist film having an opening is formed in a region on the plating base metal remaining on the bump forming region 11, and the substrate connector electrode 8 and the semiconductor substrate 1 and N are formed.
The Pn junction in the electrically opposite direction formed with the mold well 2 is irradiated with light to bring it into a conductive state to supply a plating current, and a soft metal such as indium is bumped into the opening on the plating base metal film on the bump formation region 11. After being laminated as an electrode, the photoresist can be removed, and the bump electrode can be simultaneously formed in the bump formation region 11 of the signal input portion 13 and the substrate contact bump formation portion 14. As a result, the bump forming process can be simplified and the bump electrode can be formed more quickly and more reliably than before.

Further, by making the bump forming region 11 of the signal input portion 11 and the bump forming portion 14 for the substrate contact and the N-type well 2 have the same shape and size, all the bump electrodes formed on the semiconductor device can be formed. It can be easily formed with the same height and the same shape.

After forming the bump electrodes in this manner, the bump electrodes for the substrate contact are completed by joining the bonding region 12 of the bump forming portion for the substrate contact by bonding.

[0015]

As described above, according to the present invention, an N-type well and a P ⁺ diffusion layer are provided immediately below the bump forming regions of the signal input portion and the substrate contact bump forming portion to connect to the semiconductor substrate. All the bumps on the semiconductor device are formed by irradiating the Pn junction in the electrically opposite direction formed by the N-type well and the semiconductor substrate with light to bring it into a conductive state and supplying a plating current from the substrate contact electrode. A highly reliable bump electrode can be easily and quickly formed in the region.

Further, if the bump forming region and the N-type well have the same shape and size, the bump electrode formed on the semiconductor device can have a uniform height and shape and high reliability. it can.

[Brief description of drawings]

FIG. 1 is a side sectional view of an embodiment of the present invention.

FIG. 2 is a side sectional view of a conventional semiconductor device having a bump formation region.

[Explanation of symbols]

1 semiconductor substrate 2 N-type well 3 n ⁺ diffusion layer 4 P ⁺ diffusion layer 5 insulating film 6 signal input electrode 7 gate electrode 8 substrate contact electrode 9 gate electrode 10 surface protective film 11 bump forming region 12 bonding region 13 signal input portion 14 Bump forming part for board contact 15 Board contact part

Claims (1)

[Claims] 1. A semiconductor substrate on which an integrated circuit is formed,
It is connected to the signal input electrode of the signal input section and is P ^{+ of the} N-type well
A first bump formation region provided on the diffusion layer, a second bump formation region provided on the N type well P ⁺ diffusion layer connected to the substrate contact bump electrode of the substrate contact bump formation portion, and A first bonding region connected to the substrate contact bump electrode and a second bonding region connected to the substrate contact electrode provided on the P ⁺ diffusion layer of the substrate contact portion are formed. And a semiconductor device having a bump formation region.