JPH0567395A - Memory circuit - Google Patents

Abstract

PURPOSE:To suppress memory capacity, that is, a hardware quantity to the irreducible minimum and to read a data with a different bit width at a high speed by one time of a memory access since the memory area of respective coefficient memory are utilized efficiently and effectively. CONSTITUTION:The coefficient memory 1a-1d reading the data in 8 bits from an address specified by address signals ADa, ADb are provided. Multiplexers 2a-2d selecting the output of the coefficient memory 1a-1d by selective signals SSa-SSd are provided. A selective control circuit 4 outputting the selective signals SSa-SSd selecting the output of the coefficient memory 1a-1d so as to coincide to the effective bit number of an output data OUT in accordance with a mode signal MOD, and to uniformize a selected the number of times is provided. An address control circuit 5 outputting the address signals ADa, ADd updating the address in accordance with the reading of the data of the coefficient memory 1a-1d is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to a memory circuit used for digital audio data signal processing or the like for storing and reading data having different bit widths.

[0002]

2. Description of the Related Art Conventionally, in a memory circuit of this type, for example, a coefficient memory used for digital audio data signal processing, when reading data from this coefficient memory, a plurality of data are read in order to read one data. A method of accessing the memory once or reading one piece of data in one memory access by using a part of the memory as an empty area has been adopted.

Digital audio data, eg CD
The data recorded on (Compact Disc) etc.
Normally, audio data in a band of about 20 Hz to 20 KHz is digitally recorded. For data processing during audio reproduction, data read from a CD or the like is generally band-divided through a plurality of band-pass filters, and this division is performed. Filtering or the like is individually performed on each processed data.

As an example, as a filter for band-dividing the data read from the CD, the pass band is 250H.
z or less, 250 Hz to 500 Hz, 500 Hz to 1
KHz, 1KHz to 2KHz, 2KHz to 4KH
There are filters such as z, 4 KHz to 8 KHz, and 8 KHz or more.

The bit width of coefficient data when the filter operation is performed on the data after passing through these filters is generally different for each band, and a coefficient of about 32 bits is used for data of 500 Hz or less. , A coefficient of about 16 bits is used for data of 8 KHz or more. In addition, a coefficient of about 24 bits is often used for each band from 500 Hz to 8 KHz.

On the other hand, in the conventional audio signal processing device, as a memory for storing these coefficients, the bit width of the coefficient data read in one memory access is fixed, that is, the data length and the memory address. A RAM (Random Access Memory) etc. corresponding to one-to-one was used.

For example, in the case of a memory having a fixed bit width of 16 bits, a 16-bit coefficient is read by one memory access, but in order to read a 24-bit or 32-bit coefficient, the memory is read twice. Had to access. This causes a decrease in processing speed of the filter calculation using this coefficient.

Further, in the case of a memory having a fixed bit width of 32 bits, all the coefficients are read out by one memory access, but in the area where the 16-bit coefficient is stored in the memory, half or 24 bits of the coefficient are stored. 1/3 in the stored area
Was unused. This means an increase in the hardware amount of the memory circuit.

Further, the filtering process for the data passing through each band needs to be different for each application such as sound image localization and reflected sound synthesis. Therefore, the number of bits of the coefficient used for each band is generally determined by the application. Varies significantly.

[0010] As a document describing such a conventional technique, "A realization method of a DSP system and a thorough study of its utilization" 4
Pp. 13 (T-2338 Japan Industrial Technology Center 198
(November 9) etc.

[0011]

In the above-mentioned conventional memory circuit, the bit width of the data read by one memory access is fixed, and the data and the memory address correspond to each other on a one-to-one basis. When data with different bit widths are required, the required one data is accessed a plurality of times, or the bit width per data is increased to use only the required bits. Therefore, in the former case, there is a drawback that the processing speed is reduced, and in the latter case, there is a drawback that the amount of hardware increases because there is an unused memory area.

In the latter case, a memory for storing 64 bits of 16-bit data, 256 words of 24-bit data, and 32 words of 32-bit data is 32 bits ×
In the case of a RAM of (64 + 256 + 32) words, 32 * (64 + 256 + 32) -16 * 64-24 * 256-32 * 32 = 11264-8192 = 3072, that is, an extra memory area of 3072 bits is generated.

The above-mentioned 64 words, 256 words,
The number of words such as 32 words greatly differs depending on the application realized by the audio signal processing device. Therefore, conventionally, it has been inconvenient to limit the storage address in the memory by the bit width of the data.

An object of the present invention is to provide a memory circuit capable of reading data of different bit widths at high speed without increasing the amount of hardware.

[0015]

The memory circuit of the present invention comprises:
A plurality of memory units for reading out data in a predetermined bit unit from an address designated by a corresponding address signal, and a memory unit read out from the memory unit according to the contents of a corresponding selection signal provided corresponding to each memory unit. A plurality of multiplexers for selecting and outputting one of the data in a predetermined bit unit, and a plurality of data buses connected to corresponding bit output ends of the multiplexers and transmitting bit data of corresponding ranks. According to a mode signal that determines the number of effective bits of the output data, the data of a predetermined bit unit read from a predetermined memory unit of the plurality of memory units is made uniform in the number of times selected by each of the memory units. Data in a predetermined bit unit read sequentially from these selected memory units as described above. Of the selection signals having the contents determined so as to match the order of the effective bits of the force data, and the addresses of the respective memory units where the read data are selected by the multiplexer are sequentially updated. An address control circuit for outputting the address signal, and a selection circuit for outputting the data transmitted to the plurality of data buses according to the mode signal as output data of the effective bit number designated by the mode signal. There is.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, 4 of 384 words for reading 8-bit data from an address designated by corresponding 9-bit address signals ADa and ADb, respectively.
One RAM type coefficient memory 1a to 1d and each coefficient memory 1 according to the contents of the corresponding selection signals SSa to SSd provided corresponding to each of the coefficient memories 1a to 1d.
Four multiplexers 2a to 2a to select, input, and output one of 8-bit unit data read from a to 1d
2d and 32 coefficient data buses 3 connected to the bit output terminals of the multiplexers 2a to 2d, respectively, and transmitting the bit data of the corresponding order.
And the four coefficient memories 1a to 1 according to the mode signal MOD and the increment signal INCx which determine the number of effective bits of the output data OUT (coefficient data in this embodiment).
Data of 8-bit units read from a predetermined memory portion of d are sequentially selected so that the number of times of selection of each coefficient memory 1a to 1d is made uniform, and read from these selected coefficient memories. A selection circuit 4 that outputs each selection signal SSa to SSd having contents determined so that 8-bit unit data matches the order of valid bits of the output data OUT, a control circuit 51, and an address counter 5.
An address control circuit that includes the input signals 2 and 53, inputs the mode signal MOD and the increment signal INC, and outputs the address signals ADa and ADb for sequentially updating the addresses of the coefficient memories whose read data is selected by the multiplexers 2a to 2d. 5 and 32 according to the mode signal MOD
A selection circuit 6 for outputting the data transmitted to the coefficient data bus 3 of the book as data of an effective bit number designated by the mode signal MOD and 32-bit output data OUT (coefficient data) whose upper side is "0". And has a multiplier 1
The output data OUT is supplied to 0. The multiplier 10 calculates the product of the 24-bit digital audio data ADT and the output data OUT, and outputs it as 55-bit digital audio data ADTx. The address signal AD is used as the coefficient memories 1a to 1d.
Determine the initial address of.

The increment signal INC is supplied to the multiplier 10
It is a signal that outputs a pulse signal at each timing of updating the 32-bit coefficient data (OUT) input to.

The mode signal MOD is "01" when the number of effective digits (the number of effective bits) of the 32-bit coefficient data (OUT) input to the multiplier 10 is 16 bits (hereinafter referred to as 16-bit mode). "10" when the number of digits is 24 bits (hereinafter referred to as 24-bit mode), "1" when the number of effective digits is 32 bits (hereinafter referred to as 32-bit mode)
It is a 2-bit wide mode designating signal of 1 ″.

The multiplexers 2a to 2d have a selection signal S.
When the contents of Sa to SSd are "00", the data from the coefficient memory 1a is selectively output, and when "01", the coefficient memory 1b is output.
The data from 1 is selected and outputted, the data from the coefficient memory 1a is selected and inputted when "10", and the data from the coefficient memory 1d is selected and outputted when "11".

The address counters 52 and 53 use the value of the 9-bit address signal AD as an initial value, and each time a pulse is subsequently input by the address control signals ADC1 and ADC2, the value is incremented by 1 (incremented by 1) at the timing of its rising edge. ..

2A and 2B are timing charts for explaining an internal configuration example of the control circuit 51 and its operation.
Shown in.

In FIG. 2A, 511 is a 2-bit counter that counts the number of pulses of the increment signal INC, and multiplexers 512 and 513 select and output one of three inputs according to the contents of each mode signal MOD. In the 32-bit mode, the multiplexer selects the power supply voltage _VDD corresponding to "1", and in the 16-bit mode, selects the inverted signal of the increment signal INC1 of the lower bit output of the 2-bit counter 511. .. In the 24-bit mode, the multiplexer 51
3 selects the output of the NAND gate G2.

In the following, the increment signals INC1 and IN
When the content of C2 is “00”, the steps 0, “0
The state of "1" is called step 1, the state of "10" is called step 2, and the state of "11" is called step 3.

Select signal S for each step in each mode
FIG. 3 shows the relationship between the contents of Sa to SSd and the outputs of the coefficient memories 1a to 1d selected by the selection signals SSa to SSd.

As can be seen from FIG. 3, in the 16-bit mode, the outputs of the coefficient memories 1a and 1b are selected by the multiplexers 2c and 2d at the time of step 0, and the coefficient memories 1a and 1b are selected.
The data of b is formatted on the lower side, and the data of the coefficient memory 1a is formatted on the upper side.

In step 1, coefficient memories 1c and 1d
Is similarly selected by the multiplexers 2c and 2d so that the data in the coefficient memory 1d is in the lower side,
The data of c is formatted on the upper side. In steps 2 and 3, the operations of steps 0 and 1 described above are repeated.

In 24-bit mode, multiplexer 2
Outputs of three coefficient memories out of the four coefficient memories 1a to 1d are sequentially selected and formatted by b, 2c and 2d.

That is, in step 0, the coefficient memory 1
Outputs a, 1b and 1c are selected and formatted in this order from the higher order side. In step 1, coefficient memories 1d and 1c
Outputs a and 1b are selected and formatted in this order from the upper side. Omitted below.

In the case of 32 bits, all multiplexers 2a to 2d select output selections from all coefficient memories 1a to 1d, and formatting is performed in this order from the higher order side.

With the reading of data from the coefficient memories 1a to 1d and the selection of the data from the coefficient memories of the multiplexers 2a to 2d, it is necessary to update the addresses of the coefficient memories 1a to 1d. FIG. 4 shows the relationship between the coefficient memory whose output is selected and the coefficient memory whose address is updated in each mode and each step.

As described above, in this embodiment, all coefficient data of 16 bits, 24 bits, and 32 bits are set to 1
Since the data can be read with a single memory access, high speed operation can be maintained. In addition, since the number of times the output is selected is selected so as to be uniform for all the coefficient memories 1a to 1d, the memory area is not wasted and all areas are effectively used. That is, the amount of hardware can be minimized.

Since the 16-bit, 24-bit, and 32-bit data can be stored at any address in the coefficient memories 1a to 1d, even if the data amount of each bit width greatly differs depending on the application, the coefficient Obviously, all areas of the coefficient memory can be used for storing valid data without any restrictions on the allocation of each bit width of the memory to the data.

In the present embodiment, the bit width of the bus, the capacity of the memory, the counter. The bit width of the multiplexer, the bit configuration of the multiplier, etc. are not limited to the present embodiment,
It goes without saying that it can be realized by other suitable configurations.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

This embodiment differs from the first embodiment in the structure of the address control circuit.

The latch circuit 54 latches the content of the address signal ADa of 9-bit width at the timing of the rising edge of the increment signal INC and outputs the result in 9-bit width. That is, the latch circuit 54 delays and outputs the content of the address signal ADa.

The multiplexer 55 outputs the contents of the address signal ADa as the 9-bit width address signal ADb when the address control signal ADC3 is "0", and outputs the latch circuit 54 when the address control signal ADC3 is "1". The content of is directly output as the address signal ADb.

The control circuit 51a has the structure shown in FIG.

In FIG. 6, the multiplex 514 is used when the content of the mode signal MOD is "01" or "11", that is, in the 16-bit mode or the 32-bit mode.
The ground potential corresponding to "0" is output as the address control signal ADC, and when the content of the mode signal MOD is "10", that is, 24 bits, the output of the OR gate G5 is output as the address control signal ADC3.

In this embodiment, in the 16-bit mode or the 32-bit mode, since the contents of the address counter 52a are directly output as the address signal ADb, the read addresses of the coefficient memories 1a and 1b and the coefficient memories 1c and 1d are always read. Will be the same.

Even in step 0 of the 24-bit mode, the read addresses of the coefficient memories 1a and 1b and the coefficient memories 1c and 1d are the same. In steps 1, 2, and 3 of the 24-bit mode, the content of the address signal ADb becomes the same as the content of the address signal ADa in the immediately preceding step (steps 0, 1, and 2), respectively.

Therefore, the read addresses of the coefficient memories 1c and 1d are values obtained by subtracting "-1" (decrement) from the read addresses of the coefficient memories 1a and 1b.

Even with the configuration shown in the second embodiment, the data read from the coefficient memories 1a to 1d is the same as that in the first embodiment described above, and therefore the 9-bit address counter is different from that in the first embodiment. One 53 is unnecessary, and there is an advantage that the same effect can be obtained with a small amount of hardware.

[0046]

As described above, according to the present invention, a plurality of memory units for reading data in predetermined bit units are provided, and the data read from each of these memory units is converted into valid bits of output data according to the mode signal. The memory area of each memory unit is effectively used without waste by selecting and outputting so that the number of times matches the number of times and the number of times of selection is equalized. There is an effect that the amount can be suppressed to a necessary minimum and that data having different bit widths can be read at high speed by one memory access.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the control circuit of the embodiment shown in FIG. 1 and a timing waveform diagram of each part thereof.

FIG. 3 is an operation explanatory diagram for explaining the relationship between the content of a selection signal and the output of the selected coefficient memory in each step of each mode of the embodiment shown in FIG.

FIG. 4 is an operation explanatory diagram for explaining a relationship between a coefficient memory whose output is selected and a coefficient memory whose address is updated in the embodiment shown in FIG. 1;

FIG. 5 is a block diagram showing a second embodiment of the present invention.

6 is a circuit diagram showing a specific example of a control circuit of the embodiment shown in FIG.

[Explanation of symbols]

 1a to 1d Coefficient memory 2a to 2d Multiplexer 3 Coefficient data bus 4 Selection control circuit 5,5a Address control circuit 6 Selection circuit 10 Multiplier 51, 51a Control circuit 52, 53 Address counter 54 Latch circuit 55 Multiplexer 511 2-bit counter 512 to 1212 514 multiplexer G1, G2 NAND gate G3, G4 ADN gate G5 OR gate IV1 inverter

Claims (2)

[Claims] 1. A plurality of memory units for reading out data in a predetermined bit unit from an address designated by a corresponding address signal, and each of the memory units provided corresponding to each of the memory units according to the contents of a corresponding selection signal. A plurality of multiplexers for selecting and outputting one of the data of a predetermined bit unit read from the memory unit, and corresponding bit output terminals of these multiplexers are respectively connected and transmitted to transmit corresponding bit data. Data of a predetermined bit unit read from a predetermined memory unit of the plurality of memory units is selected in each of the memory units in accordance with a plurality of data buses and a mode signal that determines the number of effective bits of output data. A predetermined bit unit read sequentially from the selected memory unit so that the number of A selection circuit for outputting each of the selection signals having a content determined so that the data of the above-mentioned data matches the position of the effective bit of the output data, and each of the memory units in which the read data is selected by the multiplexer. An address control circuit that outputs the address signal that sequentially updates the address, and a selection circuit that outputs the data transmitted to the plurality of data buses according to the mode signal as output data of the effective bit number designated by the mode signal. A memory circuit having: 2. A plurality of memory units are composed of first to fourth memory units and read data in 8-bit units,
A plurality of multiplexers are configured by the first to fourth multiplexers, and the mode signal has a content that specifies a 16-bit mode, a 24-bit mode, and a 32-bit mode,
When the selection signal has the first to fourth steps for each mode of the mode signal and the mode signal specifies the 16-bit mode, the first step includes the first and second steps. Memory unit, the third and fourth memory units in the second step, the first and second memory units in the third step, and the third and fourth memory units in the fourth step The data read from the third,
When the content is selected by the fourth multiplexer and the mode signal specifies the 24-bit mode, the first, second, and third memory units are used in the first step, and the second memory is used in the second step. Fourth, first and second memory units, the third, fourth and first memory units in the third step, and the second, third and fourth memory units in the fourth step.
2. The memory circuit according to claim 1, wherein the data read from the memory section is selected by the second, third, and fourth multiplexers.