JPH0567217A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To shorten the execution time of a processing for obtaining the remainder of division. CONSTITUTION:A multiplicand is stored in a register 103 and a divisor is stored in a register 104. A difference between values outputted from 7 most significant bit position detectors 107 and 108 connected to the registers 103 and 104 is obtained by using a computing element 111. The value of the register 104 is barrel-shifted in the direction of a high-order by using a barrel shifter 112 with the result as shifting quantity. Thus, the number of the bits of the registers 103 and 104 can be arranged in a single processing. Then, a processing for shifting the value of the register 104 to the direction of a low-order by one bit and a processing for subtracting the value of the register 104 from the register 103 are repeated until the value of the register 104 returns to the original value. Thus, the value remaining in the register 103 becomes a remainder.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic device, and more particularly to a device for obtaining a remainder of division at high speed in image processing.

[0002]

2. Description of the Related Art In computer graphics, not only is a line drawing such as a straight line or an arc drawn, but an area having a wide area such as a rectangle, a circle or a polygon is filled.

At this time, there is a case where the image is painted with a specific one color to clear the screen, but image data having a width and a height as shown in FIG. In some cases, it is filled in so that it is lined up inside. By defining various patterns and using them, the graphic expression on the screen can be diversified.

Usually, the filling pattern is as shown in FIG.
It is repeated based on the origin of the screen as shown in. As a result, the pattern continuity is maintained when a plurality of overlapping figures are painted with the same pattern.

In order to draw the pattern in the filled area relative to the origin, it is necessary to find which part of the pattern should be referred to with respect to the drawing start point on the screen. This will be described with reference to FIGS. FIG. 8 (a),
In (b), the width of the pattern is W and the height is H. When the increasing direction of the Y width is upward, the pattern reference point corresponding to the point (X, Y) in FIG. 8A is from the left end of the pattern (X% W) as shown in FIG. 8B.
("%" Is an operator for calculating the remainder of division), and is located at (Y% H) from the lower end of the pattern.

The pattern is actually an array of bits as shown in FIG. 8C, and is normally stored continuously in the work area on the memory. (X% W), (Y%
Using the value of H), the address where the data to be used for filling is stored is obtained, the corresponding data is read, and drawing is performed at the (X, Y) position on the screen.

As described above, the filling process using the rectangular pattern includes a process of obtaining the remainder when the coordinate value is divided by the size of the pattern. At this time, it is not necessary to ask for a quotient.

Conventionally, the divisor is incremented by 1 after the process of comparing with the dividend is repeated while shifting the divisor by 1 bit to the left.
The remainder of the division was calculated using the method of subtracting from the dividend while shifting to the right by a bit. This method is shown in FIG.
This will be described using 6 and 7. As shown in FIG. 5, the conventional arithmetic unit includes a data bus 101 and a multiplexer 10.
2, registers 103 to 105, a register 106 storing a constant “1”, a register 107 storing a constant “−1”, multiplexers 109 and 110, and an arithmetic unit 1
11 and a barrel shifter 112.

The calculator 111 outputs a sine flag 212 and a zero flag 213. Barrel shifter 112
Performs a left shift when a negative value is input as a shift amount, and performs a right shift when a positive shift amount is input. The registers 103, 104 and 105 are each 16 bits long. The remainder obtained as a result is stored in the register 103.

The conventional processing flow will be described with reference to FIG. This figure is a diagram showing the flow of the remainder calculation processing in the conventional example. First, the dividend is loaded from the data bus 101 into the register 103 (S201), and the divisor is registered in the register 104.
(S202). Here, the dividend and the divisor are positive numbers. If either value is negative, normalize it to a positive value. The register 105 is initialized to zero (S203).

Next, from the value of register 103 to register 1
The value of 04 is subtracted (S204), and the dividend and the divisor are compared in size (S205). If the value in the register 103 is smaller, the process branches to S208. In other cases, the value “−1” in the register 118 is used as the shift amount and the register 104
The value of is shifted left by 1 bit (S206). Then, the value “1” of the register 16 is added to the value of the register 105 and the value is written back to the register 105. That is, register 105 is set to 1
Incremented only (S207). And S204
Return to. As described above, the divisor is left-shifted by 1 bit, that is, doubled, until the dividend becomes larger than the dividend S2.
The loop of 04 to S207 is repeated.

When the loop is exited in S205, the number of times the divisor is left-shifted is stored in the register 105.
This value, that is, the shift amount of the divisor, is d when the number of bits of the dividend is subtracted from the number of bits of the divisor, and when (dividend) <((divisor) << d), d, and (dividend) ≥ ( When (divisor) << d, it becomes d + 1. (<< is a left shift operator.) Then, the value of the register 105 is not calculated, and the calculator 1
11 is passed (S208), and it is determined by the zero flag 213 output at that time whether the value of the register 105 is zero (S209). If it was zero,
That is, when the original divisor is larger than the dividend, the dividend directly remains as the remainder, and the process ends. If the value of the register 105 is 1 or more, first, the value of the register 104 is shifted to the right by 1 bit with the value "1" of the register 106 as the shift amount (S210).
Then, the result of subtracting the value of the register 104 from the value of the register 103 is written back to the register 103 (S21
1). At this time, it is determined by the sign flag 212 output from the arithmetic unit 111 whether or not the value of the register 103 becomes negative (S212). If the value is negative, the value of the register 103 is added to the value of the register 104. It returns to the positive value before the subtraction (S213). Then, the value of the register 106 is subtracted from the value of the register 105. That is, the value of the register 105 is decremented by 1 (S214).

Then, returning to S209, if the value of the register 105 is not zero, the processing from S210 onward is repeated, and if the value of the register 105 is zero, the processing is ended. At this time, the value remaining in the register 103 is the remainder.

When the dividend “455” is stored in the register 103 and the divisor “10” is stored in the register 104, the remainder 103 is calculated by the above method.
A), 104 (REGB), and 105 (REGC) changes are shown in FIG. In this example, the first of S204 to S207
And the second loop of S209 to S214 are each repeated 6 times. In the first loop, REGB is shifted left by 1 bit, that is, doubled, until the value of REGB becomes larger than REGA. In the second loop, R
REGA while shifting the EGB value right by 1 bit
Subtract REGB from. When the subtraction result becomes negative, the value of REGB is added back to restore the value of REGA to the value before the subtraction. This process is repeated and finally REGA
The value left over, that is, the remainder is "5".

Assuming that the value of the register 105 (REGC) at the time of finishing the processing of the first loop is n, from the dividend, (divisor × 2 ⁿ ), (divisor × 2 ^n-1 ), ... (divisor × 2 ^0). )
The divisor is obtained by successively subtracting. However, make sure that the result does not become negative on the way.

[0016]

The above-mentioned method may have the following drawbacks.

In the division process for obtaining the remainder, the processing time depends on the difference between the number of bits of the dividend and the number of bits of the divisor. When the dividend and the divisor are close to each other, the shift amount of the divisor is small and the number of loop processes can be small. However, when the dividend is much larger than the divisor, the difference in the number of bits becomes large and the processing time increases.

In the conventional method, each of the first loop for obtaining the shift amount and the second loop for obtaining the remainder by subtraction must be repeated by the difference between the number of bits of the dividend and the divisor or the difference between the number of bits + 1. There wasn't.

In order to fill a region of an arbitrary shape, when filling is performed one after another using a coordinate value list in which the range to be filled is specified for each horizontal line, the pattern reference start point is obtained each time one horizontal line is filled. The remainder calculation of is required. To fill an area,
Remainder calculation must be performed in each of the X and Y directions by the number of lines. If the conventional remainder calculation method is used here, the remainder calculation becomes a bottleneck and it takes a very long time to fill the entire area.

[0020]

In order to solve the above-mentioned drawbacks, the present invention comprises a first register for storing a dividend for division, a second register for storing a divisor, an arithmetic unit and a barrel shifter. And a value output by the most significant bit position detector connected to the first register, the most significant bit position detector corresponding to each of the first register and the second register. When,
The difference between the values output by the most significant bit position detector connected to the second register is calculated by the arithmetic unit,
Using the result as a shift amount, after shifting the value of the second register in the upper direction using the barrel shifter,
A means for obtaining the remainder of division is configured by repeating the process of subtracting the value of the second register from the first register and the process of shifting the value of the second register by 1 bit in the lower direction. There is.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an arithmetic unit according to the first embodiment of the present invention. In this embodiment, a data bus 101 for exchanging data with the outside, a multiplexer 102 for multiplexing the data 201 sent from the outside and an output 211 from the arithmetic unit 111 or the barrel shifter 112, and a register 103 (REG).
A), 104 (REGB), 105 (REGC), a register 106 for storing a constant “1”, a most significant bit position detector (PE) 107, 108, and a computing unit 111.
Alternatively, the multiplexer 10 for selecting the first operand or the second operand input to the barrel shifter 112.
9, 110, arithmetic unit 111, barrel shifter 112
A data output 201 from the data bus 101, a data output 202 from the multiplexer 102, data outputs 203 to 206 from the registers 103 to 106, and data outputs 207 from the most significant bit position detectors 107 and 108, 208 and multiplexers 109 and 110
Data outputs 209 and 210, a calculation result output 211 from the arithmetic unit 111 or the barrel shifter 112, a sine flag 212 and a zero flag 213 output from the arithmetic unit 111. Further, as a control signal sent from an instruction execution unit (not shown), the registers 103 to 1
Selection signal 301 sent to the multiplexer 102 to select the input to the register 05 and control signals 302 to 30 for controlling the write timing to the registers 103 to 105.
4 and a selection signal 3 for selecting data to be input to the arithmetic unit 111 or the barrel shifter 112 as the first operand.
05 to the arithmetic unit 111 or the barrel shifter 112.
A selection signal 306 for selecting data to be input as an operand of.

In this embodiment, the registers 103 and 10 are used.
Each of 4 and 105 has a 16-bit length. The remainder obtained as a result of the division is stored in the register 103.

Most significant bit position detector 107, 10
8 inputs the values of the registers 103 and 104,
The position of the bit in which 1 is set first when viewed from the most significant bit direction is output as the number of bits from the most significant bit. This can be realized with a circuit called a priority encoder. An example of the output is shown in FIG. If the value of the register 103 is "455", the binary representation becomes REGA of FIG. 3A, and the output of the most significant bit position detector 107 is "7". Similarly, if the value of the register 104 is “10”, the binary representation becomes REGB of FIG. 3A, and the output of the most significant bit position detector 108 is “12”.

The arithmetic unit 111 has data 209 and data 2
Calculation is performed between the two values input from 10. In this embodiment, a process of subtracting the data 210 from the data 209 and a process of adding the data 209 and the data 210 are performed.
The sign bit resulting from the operation is output as the sign flag 212. The sign flag 212 is "0" when the result is positive and "1" when the result is negative. If the result of the calculation is zero, the zero flag 213 is set to "1", and if it is other than zero, it is set to "0".

The barrel shifter 112 can shift a plurality of bits in one cycle. The value shifted from the data 209 is input, the shift number is input from the data 210, and the result is output to the data 211. When the number of shifts is positive, the shift is made to the right (lower side), and "0" is input to the upper bit side. When the number of shifts is negative, shift to the left (upper side), and "0" is input to the lower bit side.

The operation of this embodiment will be described with reference to the flow chart shown in FIG. It is a figure which shows the flow of the remainder calculation process in a present Example. First, from the data bus 101,
The dividend is loaded into the register 103 through the data output 201 and the multiplexer 102 (S101), and the divisor is loaded into the register 104 (S102). The write timing is controlled by control signals 302 and 303, respectively. Here, the dividend and the divisor are positive numbers. If either value is negative, normalize it to a positive value beforehand.

Next, the most significant bit position data 207 of the register 103 is used as the first operand to the arithmetic unit 111, and the most significant bit position data 2 of the register 104 is used.
08 is subtracted as the second operand to the arithmetic unit 111, and the result is stored in the register 105 (S10).
3). Whether the result of the subtraction is positive or negative is determined by the sine flag 212 and the zero flag 213 from the arithmetic unit (S10).
4). When both the sign flag 212 and the zero flag 213 are “0” and it is determined that the subtraction result is larger than zero, the register 104 has a significant bit higher than the register 103. That is, since the divisor is larger than the dividend, the dividend becomes the remainder as it is, and the processing ends.

If the result is negative or zero, the value of the register 104 is input as the first operand of the barrel shifter 112 through the multiplexer 109, and the subtraction result stored in the register 105 is input to the multiplexer 110.
As the second operand through to perform barrel shift. At this time, since the second operand, that is, the shift number is negative, the shift to the left is performed. The shift result is written back to the register 104 (S10).
5).

After that, the shift number stored in the register 105 is used as a counter value.

Next, from the value of register 103 to register 1
The value of 04 is subtracted, and the result is written back to the register 103 (S106). The result is determined by the sign flag 212 (S107), and if negative, the register 10
The value of register 104 is added to the value of 3 and register 103
The value of is restored to the positive value before the subtraction (S108).

Then, the value of the register 106 is added to the value of the register 105 which is the shift amount counter (S10).
9). Since “1” is stored in the register 106, the value of the register 105 is incremented by 1. Here, the result is determined by the sine flag 212 and the zero flag 213 at the time of addition (S110), and when the result becomes larger than zero, the process ends there. If it is negative, the value of the register 104 is shifted using the value of the register 106 as the shift amount (S11).
1). Since "1" is stored in the register 106, the value of the register 104 is shifted to the right by 1 bit.
After the result is written back to the register 104, S10
Return to the process of 6.

The dividend “455” is stored in the register 103, the divisor “10” is stored in the register 104, and the register 103 when the remainder calculation is performed by the arithmetic unit of this embodiment.
(REGA), 104 (REGB), 105 (REG
The change in C) is shown in FIG.

The most significant bit position of the dividend is "7",
The most significant bit position of the divisor is "12". So S
The shift amount obtained in 103 is 7-12 = (-5), and the value in the register 104 is barrel-shifted to the left by 5 bits in S105. Then, in the subsequent loop processing, R
REGA while shifting the EGB value right by 1 bit
Subtract REGB from. When the subtraction result becomes negative, the value of REGB is added back to restore the value of REGA to the value before the subtraction. This process is repeated 6 times, and finally RE
The value remaining in the GA, that is, the remainder is "5".

Next, a second embodiment of the present invention will be described with reference to the drawings.

In the second embodiment, since the arithmetic unit, the barrel shifter, and the counter register are operated independently, the iterative process of subtraction for finding the remainder is performed once.
It differs from the first embodiment in that it can be executed in cycles.

FIG. 4 is a block diagram showing the configuration of the arithmetic unit according to the second embodiment of the present invention. In this embodiment, a data bus 101, a multiplexer 102, registers 103 (REGA) and 104 (REGB), a register 106 for storing a constant “1”, and a most significant bit position detector (PE) 107 and 108. , Multiplexers 109 and 110, arithmetic unit 111, and multiplexer 1
Output 202 from 02 and output 20 from register 103
3 is selected and input to the register 103, the multiplexer 113 is selected, and any one of the output 202 from the multiplexer 102 and the output 214 from the barrel shifter 116 is selected and input to the register 104. A counter register 115 having a function of incrementing a value, a barrel shifter 116 dedicated to shifting the value of the register 104, or an output 216 from the counter register 115 or an output 206 from the register 106 is selected, Barrel shifter 1
16 input to multiplexer 16 and data bus 1
01 data output 201 and multiplexer 102
Data output 202 from the registers 103, 104,
Data output from 105, 106 203, 204, 20
5, 206 and the most significant bit detectors 107, 108
Data outputs 207, 208 from the multiplexer 1
09 and 110, data outputs 209 and 210, a calculation result output 211 from the arithmetic unit 111, a sine flag 212 and a zero flag 213 output from the arithmetic unit 111.
And the data output 2 from the multiplexers 113 and 114
14, 215, a data output 216 from the counter register 115, a zero flag 217 indicating whether the value of the counter register 115 is zero, a data output 218 from the barrel shifter 116, and a multiplexer 11
7 and data output 219. From the instruction execution unit (not shown) as a control signal sent to the multiplexer 102, control signals 302 and 303 for controlling the writing timing to the registers 103 and 104, and to the arithmetic unit 111. Selection signal 305 for selecting data to be input as the first operand
A selection signal 306 for selecting data to be input as a second operand to the arithmetic unit 111, and the multiplexer 11
4 and the selection signal 307 sent to the counter register 1
A control signal 308 for controlling the timing of writing and incrementing to 15 and a selection signal 309 sent to the multiplexer 117 are provided.

The sine flag 212 output from the arithmetic unit 111 is input to the multiplexer 113 as a selection signal. The multiplexer 113 uses the sign flag 2
When 12 is “0”, the data output 202 is selected and written in the register 103. When the sign flag 212 is "1", the value 203 of the register 103 is selected and written in the register 103, so the value of the register 103 does not change.

The counter register 115 receives the control signal 3
08 has a function of incrementing its own value by 1. When the value of the counter register 115 becomes zero as a result of the increment, the zero flag 21
7 becomes active. Zero flag 2 when non-zero
17 is inactive.

The barrel shifter 116 is dedicated to shifting the value of the register 104. The output 204 from the register 104 is input as the first operand. The value input as the second operand is the counter register 1
05 data output 216 or register 106 data output 206 and is selected by multiplexer 117. The first operand is shifted using the second operand as the shift amount. The shift operation according to the shift value is the same as that of the barrel shifter 112 in the first embodiment. When the shift is performed, the multiplexer 114
At the barrel shifter 116 in response to the selection signal 307.
Output 218 from is selected and written to register 104 through data output 215.

The operation of the division process in the second embodiment will be described with reference to FIGS.

The processing of S101 to S104 in FIG.
The same procedure as in the above example is performed. However, in the first embodiment, the register 105 is used for counting the shift amount of the register 104, but in the second embodiment, the counter register 115 is used. The shift amount obtained in S103 is set as an initial value in the counter register 115.

If the value of the counter register 115 is less than or equal to zero, the data output 216 of the counter register 115 is selected by the selection signal 309, and the barrel shifter 11 is selected.
Input to 6 as shift amount. This allows register 10
The value of 4 is shifted (S105).

In the first embodiment, the value of each register is changed by using the common arithmetic resource, and S106 is used.
The processes from S111 to S111 are sequentially executed. On the other hand, in the second embodiment, the subtraction of the value of the register 103, the shift of the value of the register 104, and the update of the value of the counter register 115 can be executed independently. In addition, in the second embodiment, S106.
It is possible to omit the adding back processing when the subtraction result of is negative. Therefore, in the subtraction processing S106, the register 10
If it is guaranteed that the pre-shift value of 4 is input to the arithmetic unit 111, the processing from S106 to S111 is set to 1
Can be run in cycles. The details of this processing will be described below.

The value of the register 104 is subtracted from the value of the register 103 (S106). If the result is zero or more, the value of the subtraction result sent through the data outputs 211 and 202 is selected and written in the register 103. When the result of the subtraction is negative, the original value of the register 103 is selected and written in the register 103 again, so the value of the register 103 is saved. Therefore, it is not necessary to perform the addition process S108 for recovering the value of the register 103 to be positive.

At the same time, the value of the counter register 115 is incremented (S109) and the value of the register 104 is right-shifted by 1 bit (S111). Multiplexer 1
At 17, the data output 206 of the register 106, that is, “1” is selected and input to the barrel shifter 116 as a shift amount.

Regarding the determination of the end of loop iteration,
Since the processing may be ended at the time when the processing in the cycle next to the cycle in which the counter register 115 has become zero, the zero flag is set to "1" by referring to the zero flag 217 output from the counter register 115. In the next cycle, the processing of the last loop and the branch that exits the loop are performed at the same time.

[0048]

As described above, according to the present invention, in the remainder calculation, the processing for obtaining the shift amount of the divisor can be performed at one time. Therefore, the number of bits of the dividend and the divisor are used to obtain the shift amount. Processing time is shortened as compared with the conventional method in which it is necessary to repeat the processing by the difference of 1 or the difference of the number of bits + 1.

When drawing on a screen consisting of 1280 × 1024 pixels, the coordinate value as the dividend is 11 bits at maximum, and it is considered that the value of 8 to 10 bits is actually high. Also, if you want to fill the background of the window in the window system, etc.
It is often the case that a simple pattern of about × 4 or 8 × 8 pixels is repeated, and the value of the width / height of the pattern which is a divisor is 3
~ 4 bits.

When the dividend is 455 and the divisor is 10, in the conventional method, the first loop for obtaining the shift amount and the second loop for obtaining the remainder are each repeated 6 times. Since the first loop takes 4 cycles once and the second loop takes 5 cycles once (when no add back is performed), the execution time is as follows, corresponding to the processing shown in FIG.

S201 to S203 ... 3 cycles S204 to S207 (first loop) ... 4 × 6 + 2 cycles (plus 2 cycles for exiting the loop) S208 ... 1 cycle S209 to S214 (second cycle) Loop of 5 × 6 + 2 + 1 (addition return processing 2 cycles, loop exit determination 1 cycle is added) The above is 63 cycles in total.

When the arithmetic unit of the first embodiment of the present invention is used with the same dividend and divisor, the loop portion repeats 5 cycles of processing (when adding back is not performed) six times. The processing corresponding to the processing shown is as follows.

-S101 to S105 ... 5 cycles-S106 to S111 (loop) ... 5 x 6 + 2-1 cycles (2 cycles are added because the add-back processing is performed twice, and 1 cycle is negative because S111 is not executed in the last loop. In total, the number of cycles is 36 cycles, which is 57% of the processing time of the conventional example.

Furthermore, when the arithmetic unit of the second embodiment is used, the loop portion in the first embodiment can be executed once in one cycle, so that six loop iterations are six cycles and the total execution time is Is 11 cycles. This is 17% of the execution time of the conventional example, and the execution time is greatly reduced.

As described above, the time for obtaining the remainder is shortened, and as a result, the time for the filling process using the rectangular pattern can be shortened.

In the first embodiment, a common arithmetic unit and barrel shifter are used for manipulating register values.
Therefore, it is used when it is desired to realize with a relatively simple hardware configuration.

In the second embodiment, dedicated hardware is provided for manipulating the value of each register. This method is used when speed is more important than saving hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic unit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of remainder calculation in the first embodiment.

3A and 3B show the operation of the first embodiment, FIG. 3A is a diagram showing the output of the most significant bit position detector, and FIG. 3B is a change in the value of each register of the remainder calculation in the first embodiment. FIG.

FIG. 4 is a block diagram showing a configuration of an arithmetic unit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an arithmetic device in a conventional example.

FIG. 6 is a flowchart showing the operation of remainder calculation in the conventional example.

FIG. 7 is a diagram showing changes in the value of each register in the remainder calculation in the conventional example.

8A and 8B are diagrams showing a rectangular filling operation, FIG. 8A shows a filling result by a filling pattern, FIG. 8B shows a rectangular filling pattern, and FIG. 8C shows a bit image of the rectangular filling pattern.

Claims (1)

[Claims] 1. An arithmetic unit comprising: a first register for storing a dividend for division; a second register for storing a divisor; an arithmetic unit and a barrel shifter; each of the first register and the second register. And a value output by the most significant bit position detector connected to the first register and a most significant bit position detection connected to the second register. The difference from the value output by the calculator is calculated by the arithmetic unit, and the result is used as the shift amount to shift the value of the second register in the upper direction using the barrel shifter, and then the second register Of the division of the second register and the process of shifting the value of the second register by 1 bit in the lower direction are repeated to obtain the remainder of the division. Arithmetic unit.