JPH056680A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To eliminate difficulty of layout of a high voltage switch and a column switch and to obtain an EEPROM having a page mode writing function and adapted for a high integration. CONSTITUTION:A column switch and a high voltage switch connected to bit lines, are removed, and an address counter 26 and a data latch 27 are newly provided. A data latch 27 is disposed between an I/O buffer 19 and a Y gate 18. At the time of a program cycle, the counter 26 is activated, and transfer gates G1-Gm in the gate 18 are sequentially selected. Thus, a high voltage Vpp or 0V is periodically applied to the bit line in a memory cell array 11 according to write data stored in the latch 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device which can be electrically programmed / erased and in which a plurality of bytes can be programmed / erased collectively.

[0002]

2. Description of the Related Art FIG.
Erasable nonvolatile semiconductor memory device (hereinafter referred to as EEPRO
FIG. 20 shows voltage application conditions at the time of programming and erasing.

First, referring to FIG. 19, an EEPROM
An outline of the memory cell structure will be described. An N ⁺ type impurity region 2 is formed on the main surface of the P ⁻ type semiconductor substrate 1 at a predetermined interval.
3, 10 are formed. A gate electrode 4 is formed on a region between impurity region 2 and impurity region 3 with an insulating film made of an oxide film interposed therebetween. Thereby, the selection transistor 5 is formed.

A floating gate (floating gate) 7 is formed on the impurity region 3 via a very thin oxide film (tunnel oxide film) 6 having a thickness of about 100 Å, and is electrically insulated above the floating gate 7. The control gate 8 is formed through the film. As a result, a memory transistor (double-layer gate transistor) 9 having a double-layer gate structure is formed.

In the EEPROM, the selection transistor 5 and the memory transistor 9 form a 1-bit memory cell. The impurity region 2 is connected to the bit terminal BL,
Gate electrode 4 is connected to word terminal WL, and impurity region 10 is connected to source terminal SL. The control gate 8 is connected to the control gate terminal CG.

In an actual memory cell array, gate electrode 4 is connected to a word line for selecting in the row direction in the memory cell array, and impurity region 2 is connected to a bit line for selecting in the column direction. In addition, the impurity region 1
0 is connected to the source line.

Next, the operation of the memory cell of FIG. 19 will be described. A high voltage Vpp (usually about 12V) is applied to the bit terminal BL and the word terminal WL of this memory cell, 0V is applied to the control gate terminal CG, and the source terminal S
Make L high impedance. Then, a very strong electric field is applied to the oxide film 6 in the direction from the floating gate 7 to the impurity region 3, and electrons are extracted from the floating gate 7 to the impurity region 3 by the tunnel phenomenon. As a result, the potential of the floating gate 7 becomes positive, and the two-layer gate transistor 9 is turned on even if 0V is applied to the control gate 8. That is, the double-layer gate transistor 9 is depleted. This state is called a program state and corresponds to data "0".

A high voltage Vpp (normally 12V) is applied to the control gate terminal CG of this memory cell, 0V is applied to the bit terminal BL, and a high level signal is applied to the word terminal WL. 0 V is applied to the source terminal SL, or high impedance is set. Then, a very strong electric field is applied to the oxide film 6 from the impurity region 3 to the floating gate 7, and electrons are injected from the impurity region 3 to the floating gate 7 by the tunnel phenomenon. As a result, the potential of the floating gate 7 becomes negative, and when 0 V is applied to the control gate 8, the double-layer gate transistor 9 does not turn on. That is, the double-layer gate transistor 9 is enhanced. This state is called an erased state and corresponds to data "1".

The erase operation and program operation of the above memory cell are generically defined as writing.

In order to read the information (data) written in this memory cell, the potential of the word terminal WL is set to the high level, 0V is generally applied to the control gate terminal CG, and the bit terminals BL and It is detected whether or not a current flows between the source terminals SL.

FIG. 20 shows the relationship between the current Icell flowing between the bit terminal BL and the source terminal SL and the voltage VCG applied to the control gate terminal CG in the programmed state and the erased state. When a current flows in the state of VCG = 0V, it can be determined that the memory cell is in the programmed state, and when no current flows, it is in the erased state.

FIG. 21 is a block diagram showing a general EEPROM chip configuration, and FIG. 22 is a diagram showing a specific circuit configuration of a memory cell array and its periphery.

In FIG. 21, the memory cell array 11
Includes a plurality of memory cells arranged in a matrix. A plurality of word lines are arranged corresponding to a plurality of rows of memory cells, and a plurality of bit lines are arranged corresponding to a plurality of columns of memory cells. X-system address buffer 12 and Y
The system address buffer 13 receives an address signal for selecting an address in the memory cell array 11 from the address terminal A.
It is input via 0 to Ak. The X decoder 14 receives the output signal of the X system address buffer 12 and selects one word line from a plurality of word lines. The Y decoder 15 is
The output signal of the Y-system address buffer 13 is received, and a bit line for one data is selected from a plurality of bit lines.

Y gate 18 receives the output signal of Y decoder 15 and connects the selected bit line to write driver 16 and sense amplifier 17. I / O buffer 19
Inputs the input data given from the data input / output terminals D0 to D7 to the write driver 16 or outputs the output data given from the sense amplifier 17 to the data input / output terminals D0 to D7. The write driver 16 transfers the input data to the memory cell array 11 via the Y gate 18.
The data is transmitted to the bit line in the column latch group 20 via the transfer gate group 21. The sense amplifier 17 detects whether the selected memory cell is in the programmed state or the erased state.

The Vpp switch group 22 includes the memory cell array 1 according to the data latched by the column latch group 20.
A high voltage is applied to the bit line within 1. Charge pump 2
An external power source 3 generates a high voltage required for writing. Erase / program timing control circuit 24
Controls the timing of erase and program operations.

The output enable terminal / OE receives an output enable signal designating whether or not the output is possible, and the chip enable terminal / CE receives a chip enable signal designating whether or not the chip is in an active state and writes. The enable terminal / WE receives a write enable signal designating whether or not it is in the writable state. The write / read control circuit controls the mode of the chip in response to the output enable signal, the chip enable signal and the write enable signal.

Next, the circuit configuration of the memory cell array 11 and its peripherals will be described in detail with reference to FIG.

In memory cell array 11, a plurality of word lines WL1 to WLn are arranged corresponding to a plurality of rows of memory cells, and a plurality of bit lines are arranged corresponding to a plurality of columns of memory cells. Further, a plurality of control gates CG1 to CGn are arranged corresponding to a plurality of rows of memory cells. Each of the plurality of bit lines has eight bit lines B
It is classified into bytes 1 to m consisting of L0 to BL7.
All memory cells (memory cells of bytes 1 to m) connected to one word line are called a page.

The column latch group 20 includes a plurality of column latches 200, the transfer gate group 21 includes a plurality of transfer gates 210, and the Vpp switch group 2
2 includes a plurality of Vpp switches 220.

One column latch 200 and one Vpp switch 220 are connected to each bit line to enable batch erasing / programming in page units. Further, a Vpp switch 230 for applying a high voltage to the control gates CG1 to CGn is connected to the control gate active line CGA. The control gate active line CGA is arranged in parallel with the bit lines BL0 to BL7. The Y decoder 15 is connected to m Y gate lines Y1 to Ym corresponding to bytes 1 to m. Y gate 18
Includes m sets of transfer gates G1 to Gm corresponding to bytes 1 to m. The Y gate lines Y1 to Ym are connected to the transfer gates G1 to Gm, respectively.

Next, a series of erase / program operations of the EEPROMs of FIGS. 21 and 22 will be described with reference to the timing chart of FIG.

In FIG. 23, T1 indicates a write cycle for writing externally input write data into a predetermined column latch 200, and T2 indicates an erase state of all memory cells of a page selected by a word line. , T3 indicates a program cycle in which the memory cells in the page selected by the word line are collectively programmed according to the write data latched by the column latch 200.

(1) Write Cycle First, the Y decoder 15 sequentially selects the Y gate lines Y1 to Ym. The Y gate lines Y1 to Ym correspond to the bytes 1 to m, respectively. Write data is written by the write driver 16 into the column latch 200 of the selected byte. As a result, the write data of all memory cells (memory cells for one page) connected to one word line are latched by the column latch 200.

(2) Erase cycle Before entering the program cycle, the memory cell of the selected page is erased. Now, it is assumed that the memory cell connected to the word line WL1 (memory cell of page 1) is rewritten.

First, all memory cells of page 1 are erased. When the erase signal Erase shown in FIG. 22 becomes "H", the Vpp switch 230 is activated. Further, the potential of the word line WL1 rises to the high voltage Vpp. Therefore, the high voltage Vpp is applied to the control gates CG1 of all the memory cells of page 1 via the transistor S10, and all the memory cells of page 1 are erased.

(3) Program cycle When the erase cycle ends, the Vpp switch 220 connected to the bit lines BL0 to BL7 is activated according to the write data latched in the column latch 200. At this time, the potential of the word line WL1 also rises to the high voltage Vpp. Therefore, the high voltage Vpp or 0V is applied to the tunnel regions of the memory transistors M0 to M7 through the select transistors S0 to S7, and the memory cells in page 1 are collectively programmed.

In this case, if the write data is "0",
The bit line corresponding to the column latch 200 has a high voltage V
If the write data is "1", the bit line corresponding to the column latch 200 remains at 0V. The above writing method is generally called page mode writing.

[0028]

The conventional EEPROM is constructed as described above, and a Vpp switch and a column switch are provided for each bit line in order to perform batch writing in page units. In the generation in which the area of the memory cell itself is large, the layout of the Vpp switch can be relatively easily performed, but it becomes difficult to perform the layout of the Vpp switch according to the pitch of the memory cell as the integration of the memory becomes higher. Further, since the column switch must be laid out according to the pitch of each memory cell, the layout of the column switch becomes difficult like the Vpp switch.

An object of the present invention is to obtain an EEPROM which has a page mode writing function, can be easily laid out, and is suitable for high integration.

[0030]

A nonvolatile semiconductor memory device capable of electrically programming / erasing a plurality of bytes collectively according to a first aspect of the present invention is a plurality of bit lines and a plurality of bit lines connected to a plurality of bit lines. Memory cell, input buffer means for inputting write data given from the outside, data holding means for holding the write data input by the input buffer means, and write voltage according to the write data held in the data holding means. A write voltage generating means for generating and a selecting means are provided. The selecting means periodically and repeatedly selects each of the plurality of bit lines during programming, and connects the selected bit line to the write voltage generating means.

The selecting means periodically and repeatedly selects the plurality of transfer gate means connected between each of the plurality of bit lines and the write voltage generating means and each of the plurality of transfer gate means during programming. It may also include a counter means for turning on.

A nonvolatile semiconductor memory device capable of electrically programming / erasing a plurality of bytes collectively according to a second aspect of the present invention includes a plurality of bit lines, a plurality of memory cells connected to the plurality of bit lines, and a write operation. Write data supply means for giving data to each of a plurality of bit lines, a plurality of sets of write voltage determining means,
And selection means. Each of the plurality of sets of write voltage determining means includes a high voltage switch means and a latch means, and determines the write voltage according to the write data. Each of the plurality of sets of write voltage determining means is provided commonly to a plurality of predetermined bit lines. The selection means cyclically and repeatedly selects each of the plurality of bit lines during programming, and connects the selected bit line to the corresponding write voltage determination means.

The selecting means periodically repeats a plurality of transfer gate means connected between each of the plurality of bit lines and the corresponding write voltage determining means, and a plurality of transfer gate means at the time of programming. It may include counter means for selecting and turning on.

A nonvolatile semiconductor memory device according to the third invention capable of electrically programming / erasing a plurality of bytes at a time includes a plurality of bit lines, a plurality of memory cells connected to the plurality of bit lines, and a write operation. A plurality of latch means for holding data, a plurality of high voltage switch means, and a selection means are provided.

The plurality of latch means are provided corresponding to the plurality of bit lines. Each of the plurality of high voltage switch means is commonly provided to a plurality of predetermined bit lines. Each high voltage switch means and a corresponding plurality of predetermined latch means form a write voltage determining means that determines the write voltage according to the write data. The selection means periodically and repeatedly selects each of the plurality of bit lines and the corresponding latch means at the time of programming, and connects the selected bit line to the corresponding high voltage switch means and the selected latch means.

The selecting means includes a plurality of nodes respectively connected to the plurality of high voltage switch means, and a plurality of first transfer gate means respectively connected between each of the plurality of bit lines and a corresponding node. , A plurality of second transfer gate means connected between each of the plurality of latch means and the corresponding node, and a plurality of first transfer gate means and a plurality of second transfer gate means during programming. Counter means for periodically and repeatedly selecting and turning on each of the above.

According to a fourth aspect of the invention, a nonvolatile semiconductor memory device capable of electrically programming / erasing a plurality of bytes in a lump is a plurality of bit lines, a plurality of memory cells connected to a plurality of bit lines, and a plurality of memory cells. A latch means and a selection means are provided. The plurality of latch means are provided corresponding to the plurality of bit lines, and each hold a ground voltage or a high voltage according to write data. The selection means periodically and repeatedly selects each of the plurality of bit lines and the corresponding latch means at the time of programming, and connects the selected bit line to the selected latch means.

The selecting means is connected between a plurality of nodes each provided commonly to a plurality of predetermined bit lines and a plurality of predetermined latch means, and a node corresponding to each of the plurality of bit lines. A plurality of first transfer gate means, a plurality of second transfer gate means each connected between a node corresponding to each of the plurality of latch means, and a plurality of first transfer gate means at the time of programming; And a counter means for periodically repeatedly selecting and turning on each of the plurality of second transfer gate means.

[0039]

In the non-volatile semiconductor memory device according to the first aspect of the present invention, each of a plurality of bit lines is periodically and repeatedly selected at the time of programming, and the selected bit line is written by the data holding means. A write voltage is applied according to the data. Therefore, the write voltage can be supplied to each bit line for a sufficient time for writing to the memory cell.

In this nonvolatile semiconductor memory device,
It is not necessary to provide high voltage switches and column latches on each bit line. Further, the data holding means corresponding to the column latch can be arranged between the input buffer means and the bit line. Therefore, the difficulty of the pattern layout of the high voltage switch and the column latch is solved, and the element layout has a margin.

In the non-volatile semiconductor memory device according to the second invention, each of a plurality of bit lines is periodically and repeatedly selected at the time of programming, and the selected bit line is connected to the corresponding write voltage determining means. To be done. The write voltage determination means determines the write voltage according to the write data given to the connected bit line. Therefore, the write voltage can be supplied to each bit line for a sufficient time for writing to the memory cell.

In this nonvolatile semiconductor memory device,
Since each write voltage determining means is commonly provided for a plurality of predetermined bit lines, the number of high voltage switch means and latch means is greatly reduced. Therefore, the difficulty of the pattern layout of the high voltage switch means and the latch means is solved, and the element layout has a margin.

In the non-volatile semiconductor memory device according to the third aspect of the invention, each of the plurality of bit lines and the corresponding latch means are periodically and repeatedly selected at the time of programming,
The selected bit line is connected to the corresponding high voltage switch means and the selected latch means. Each high voltage switch means establishes the write voltage of the selected bit line according to the write data held in the selected latch means. Therefore, the write voltage can be supplied to each bit line for a sufficient time for writing to the memory cell.

In this nonvolatile semiconductor memory device,
Since each high-voltage switch means is commonly provided to a predetermined plurality of bit lines, the number of high-voltage switch means is significantly reduced. Also, a plurality of latch means can be arranged in the same direction as the bit lines. Therefore, the difficulty of the pattern layout of the high voltage switch means and the latch means is solved, and the element layout has a margin.

In the nonvolatile semiconductor memory device according to the fourth aspect of the present invention, each of the plurality of bit lines and the corresponding latch means are periodically and repeatedly selected at the time of programming,
The selected bit line is connected to the selected latch means. As a result, the ground voltage or high voltage held in each latch means is supplied to the selected bit line. Therefore, the write voltage can be supplied to each bit line for a sufficient time for writing to the memory cell.

In this nonvolatile semiconductor memory device,
It is not necessary to provide a high voltage switch for each bit line. Also, a plurality of latch means can be arranged in the same direction as the bit lines. Therefore, the difficulty of the pattern layout of the high voltage switch means and the latch means is eliminated,
Allows for element layout.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment FIG. 1 is a block diagram showing the structure of an EEPROM according to the first embodiment of the present invention.

The EEPROM of FIG. 1 is the conventional EE of FIG.
It differs from the PROM in the following points. 21 EEPR
The column latch group 20, the transfer gate group 21, and the Vpp switch group 22 in the OM are eliminated, and an address counter 26 and a data latch 27 are newly provided.

The address counter 26 is controlled by the erase / program timing control circuit 24a.
The output signal of the address counter 26 is given to the Y-system address buffer 13. The data latch 27 is arranged between the I / O buffer 19 and the Y gate 18. The data latch 27 receives the output signal of the Y decoder 15 and latches the write data input from the I / O buffer 19. The configuration of the other parts is similar to that shown in FIG.

FIG. 2 shows the memory cell array 1 shown in FIG.
1 is a circuit diagram showing 1 and its surroundings in detail. The configuration of memory cell array 11 is similar to that of memory cell array 11 shown in FIG.

Write driver 16 includes eight driver circuits WD0 to WD7. Each driver circuit includes a Vpp switch 161, an inverter 162, and an N-channel MOS.
It includes transistors 163 and 164. Data latch 27
The data Din0 to Din7 read from are supplied to the driver circuits WD0 to WD7 of the write driver 16, respectively.

Next, referring to FIG. 2, this EEPRO
A series of erase / program operations of M will be described. Figure 2 now
It is assumed that the memory cell of page 1 is rewritten.

(Write Cycle) First, write data input from the data input / output terminals D0 to D7 of FIG. 1 is applied to the data latch 27 through the I / O buffer 19 of FIG. This write data is stored in a predetermined address in the data latch 27 selected by the Y decoder 15.

After the write data corresponding to all the bytes 1 to m in page 1 are stored in the data latch 27, page 1
Erase all memory cells in

(Erase Cycle) The X decoder 14 raises the potential of the word line WL1 to the high voltage Vpp. Further, the erase signal Erase becomes "H". Thereby,
Control gate CG1 via transistor S10
The high voltage Vpp is transmitted to and all the memory cells of page 1 are erased. When the erase cycle ends, the program cycle starts.

(Program Cycle) FIG. 3 is a timing chart showing a program cycle. First, the erase / program timing control circuit 24 of FIG.
The address counter 26 is activated by a. The address counter 26 periodically and repeatedly selects the Y-system address from the start to the end of the program cycle.

First, in response to the output signal of the address counter 26, the Y decoder 15 selects the Y gate line Y1. As a result, the voltage of the Y gate line Y1 becomes high voltage Vpp.
Then, the transfer gate G1 is turned on.

At the same time, the Y decoder 15 selects the address corresponding to byte 1 of the data latch 27. Thereby, the write data corresponding to byte 1 stored in data latch 27 is transmitted to write driver 16. The driver circuits WD0 to WD7 of the write driver 16 generate the high voltage Vpp if the write data Din0 to Din7 from the data latch 27 indicate the programmed state, and generate 0V if the write data Din0 to Din7 indicate the erased state.

The output of the write driver 16 is transferred through the transfer gate G1 to the bit lines BL0 to BL7 of byte 1.
Be transmitted to. At this time, the word line W corresponding to page 1
The voltage of L1 has risen to the high voltage Vpp. Therefore, the select transistors S0 to S0 of the memory cells in byte 1 are
A write voltage of 0V or a high voltage Vpp is applied to the tunnel regions of the memory transistors M0 to M7 through S7.

As shown in FIG. 3, after a certain period of time, the address counter 26 (FIG. 1) is counted up and Y
The gate line Y2 is selected. In this case as well, the write driver 16 applies the write voltage to the bit lines BL0 to BL7 of the byte 2 in accordance with the data corresponding to the byte 2 in the data latch 27. Similarly, the Y gate lines Ym corresponding to the byte m are sequentially selected, and the write data is applied to the corresponding bit lines BL0 to BL7.

After the Y gate line Ym is selected, the Y gate line Y1 corresponding to the byte 1 is again selected, and similarly, the Y gate lines Ym corresponding to the byte m are sequentially selected. This operation is repeated during the program cycle determined by the erase / program timing control circuit 24a.

Generally, it takes several ms to program a memory cell by utilizing the tunnel effect. Therefore, the address counter 26 is activated during this period to sequentially apply the write voltage to the memory cells.

Here, if one selection period of each byte is, for example, 1 μs, since there are m bytes of memory cells in one page, the next byte is selected after m μs. . During this period, the supply source of the write voltage to the memory cell is cut off. However, the current flowing by the tunnel effect is about several tens pA to several nA,
The write voltage can be sufficiently supplied by the charges stored in the parasitic capacitance (generally 1 to 2 pF) of the bit line.

According to the first embodiment described above, the transfer gates G1 to G in the Y gate 18 are activated by activating the address counter 26 during the program cycle.
m is periodically and repeatedly selected, and the data latch circuit 2
Memory cell array 1 according to the write data stored in
A write voltage of 0 V or high voltage Vpp is periodically applied to the 1 bit line.

Therefore, the program type EEP without using the high voltage switch (Vpp switch) for the bit line.
A ROM can be realized, and a pattern layout can be performed with a sufficient margin even when high integration is advanced.

In the EEPROM of the first embodiment described above, the control gates of all memory cells in the same page are common, and the memory cells in the same page are always erased collectively. The present invention can also be applied to an EEPROM in which memory cells in the same page have individual control gates and can be independently erased.

(2) Second Embodiment FIG. 4 is a block diagram showing the structure of an EEPROM according to the second embodiment of the present invention. The EEPROM of FIG. 4 is shown in FIG.
1 is different from the conventional EEPROM in the following points.

A column latch group 30, a Vpp switch group 31 and a transfer gate group 32 are provided in place of the column latch group 20, the transfer gate group 21 and the Vpp switch group 22 in the EEPROM of FIG. 21, and further an address counter 26 and a data latch are provided. Two
7. Program refresh counter 28 and Vpp
A switch group 29 is provided.

The address counter 26 is controlled by the erase / program timing control circuit 24b. The output signal of the address counter 26 is input to the Y-system address buffer 13. The data latch 27 is an I / O
It is arranged between the buffer 19 and the Y gate 18. The data latch 27 receives the output signal of the Y decoder 15 and receives I
The write data input from the / O buffer 19 is latched.

The program refresh counter 28 is
During the program cycle, a clock signal is applied to the transfer gate group 32 through the Vpp switch group 29, and V
The connection between the Vpp switch in the pp switch group 31 and the bit line in the memory cell array 11 is switched. As a result, the write voltage is applied to the bit line from each Vpp switch. The configuration of the other parts is similar to that shown in FIG.

FIG. 5 shows the memory cell array 1 shown in FIG.
1 is a circuit diagram showing in detail the configuration of 1 and its periphery.

In FIG. 5, the column latch group 30 includes m column latches 300 corresponding to m bytes. The Vpp switch group 31 includes m Vpp switches 310 corresponding to m bytes. That is, one column latch 300 and one Vpp switch 310 are provided for each byte.

Transfer gate group 32 includes a plurality of transfer gates 320 to 327 corresponding to a plurality of bit lines BL0 to BL7. The column latch 300 and Vpp switch 310 of each byte are connected to the bit lines BL0 to BL7 in that byte via transfer gates 320 to 327, respectively.

The Vpp switch group 29 includes eight Vpp switches 290 to 297. Program refresh counter 28 supplies clock signals CLK0 to CLK7 to Vpp switches 290 to 297, respectively. Vpp
The outputs of the switches 290 to 297 are supplied to the transfer gates 320 to 327, respectively.

FIG. 6 shows a detailed circuit diagram of the column latch 300 and the Vpp switch 310. V shown in FIG.
The pp switch 310 is a generally used Vpp switch, and when a high-level potential is supplied to the node N1, the voltage of the node N1 is changed to Vpp by the clock signal φ.
Start up to the level. Further, the column latch 300 receives the potential of the bit line selected by the node N2 and generates the ground potential or the power supply potential.

Next, a series of erase / program operations of the EEPROM of FIGS. 4 and 5 will be described. Now, assume that the memory cell of page 1 in FIG. 5 is rewritten.

(Write Cycle) First, the write data input from the data input / output terminals D0 to D7 of FIG.
The data is input to the data latch 27 through the buffer 19 (FIG. 4). At this time, the Y decoder 15 selects a predetermined address in the data latch 27 in response to the Y-system address signal. Thereby, the write data is stored in the selected address in the data latch 27.

After the write data corresponding to all the bytes 1 to m in page 1 are stored in the data latch 27, page 1
Erase all memory cells in

(Erase Cycle) First, the X decoder 14 raises the voltage of the word line WL1 to the high voltage Vpp. Further, the erase signal Erase becomes "H". Thereby, the high voltage Vpp is applied to the control gate CG1 via the transistor S10, and all the memory cells of page 1 are erased. When the erase cycle ends, the program cycle starts.

(Program Cycle) FIG. 8 is a timing chart showing a program cycle. First, FIG.
Erase / program timing control circuit 24b
Thus, the address counter 26 is activated. When the program cycle starts, the address counter 26
The Y system address is sequentially selected.

First, in response to the output signal of the address counter 26, the Y decoder 15 selects the Y gate line Y1 and raises its voltage to the high voltage Vpp. As a result, the transfer gate G1 is turned on.

At the same time, the Y decoder 15 selects the address corresponding to byte 1 of the data latch 27. Thereby, the write data corresponding to byte 1 stored in data latch 27 is transmitted to write driver 16. The driver circuits WD0 to WD7 of the write driver 16 generate the high voltage Vpp if the write data Din0 to Din7 from the data latch 27 indicate the programmed state, and generate 0V if the write data Din0 to Din7 indicate the erased state.

As a result, the output of the write driver 16 is transferred to the bit line BL of byte 1 through the transfer gate G1.
0 to BL7 are transmitted. At this time, since the voltage of the word line WL1 corresponding to page 1 has risen to the high voltage Vpp, the select transistor S of the memory cell in byte 1 is selected.
A write voltage of 0V or a high voltage Vpp is applied to the tunnel regions of the memory transistors M0 to M7 through 0 to S7.

As shown in FIG. 8, after a certain period of time, the address counter 26 (FIG. 4) is counted up and Y
The gate line Y2 is selected. In this case as well, the write driver 16 applies the write voltage to the bit lines BL0 to BL7 of the byte 2 in accordance with the data corresponding to the byte 2 in the data latch 27. Similarly, the Y gate lines Ym corresponding to the byte m are sequentially selected, and the write voltage is applied to the corresponding bit lines BL0 to BL7.

By the above operation, the parasitic capacitances C _{BL0 to} C _BL7 of the bit lines _BL0 to _BL7 in each byte (see FIG. 6).
Are charged to a high voltage Vpp or discharged to 0V.

After the Y gate line Ym corresponding to the byte m is selected, the address count 26 becomes inactive, and then all the transfer gates G1 to Gm are turned off until the program cycle ends.

Next, refresh counter 28 is activated and clock signals CLK0 to CLK7 sequentially rise. As a result, the transfer gate 3 in each byte
20 to 327 are sequentially turned on, and the bit line BL in each byte
0 to BL7 are sequentially connected to the column latch 300 and the Vpp switch 310 existing in each byte.

As shown in FIG. 7, the clock signal CLK0
Reset signal RESET rises before rising. As a result, the node N1 of the Vpp switch 310 in FIG. 6 becomes 0V. After that, the clock signal CLK0 rises. As a result, the corresponding Vpp switch 290 is activated and the transfer gate 320 receives the high voltage Vp.
p is given. As a result, the bit line BL0 is connected to the corresponding column latch 300 and Vpp switch 310.

If the parasitic capacitance C _BL0 of the bit line BL 0 is charged with the high voltage Vpp, the Vpp switch 310 is activated. If the potential of the bit line BL0 is almost 0V, the Vpp switch 310 remains inactive.

Set signal SET rises after a delay time from the rise of clock signal CLK0. During this delay time, the column latch 300 receives the potential of the bit line BL0 and generates 0V or 5V (assuming that the external power supply potential is 5V) at the node N2. When the set signal SET rises, the voltage of the bit line BL0 is changed to the high voltage V
It can be set to pp or 0V.

Similarly, clock signals CLK1 to CL
K7 sequentially rises and bit lines BL1 to B in each byte
L7 is sequentially the column latch 300 and the Vpp switch 3
Connected to 10.

In this way, the clock signals CLK0 to CLK0
By periodically and repeatedly raising CLK7, the bit lines BL0 to BL7 in each byte are periodically connected to the column latch 300 and the Vpp switch 310.
As a result, the memory cell can be programmed.

As described above, generally, it takes several ms to program a memory cell by utilizing the tunnel effect. Therefore, the program refresh counter 28 is activated during this period to sequentially apply the write voltage to the memory cells.

Here, if one selection period of each bit line is, for example, 1 μs, the column latch 300 and the Vpp switch 310 are provided for each byte, so that bit line is selected next. 7μ
s later. During this period, the supply source of the write voltage to the memory cell is cut off. However, the write voltage can be sufficiently supplied by the charges stored in the parasitic capacitance (generally 1 to 2 pF) of the bit line. It is also considered that the bit line to which 0V is applied is also cut off from the supply source of the potential of 0V and the potential of the bit line gradually increases due to the influence of the peripheral memory cells. However, when the bit line is selected by the clock signal, the column latch 30
A potential of 0 V is supplied by 0, and stable operation can be obtained.

In the above description, the program refresh counter 28 is activated after the address counter 26 is deactivated, but as shown by the broken line in FIG. The clock signals CLK0 to CLK7 may be sequentially activated at a constant cycle until activated and the program cycle ends. The operation in this case will be described.

First, when the byte 1 is selected by the address counter 26 (FIG. 4), the clock signal CL
K0 rises. As a result, the bit line B in each byte
L0 is connected to the column latch 300 and the Vpp switch 310 via the transfer gate 320.

Next, when byte 2 is selected by address counter 26, clock signal CLK1 rises. As a result, the bit line BL1 in each byte is transferred to the column latch 300 via the transfer gate 321.
And Vpp switch 310.

In this way, when the byte 9 is selected by the address counter 26, the program refresh counter 28 outputs the clock signal CLK.
Start up 0. In this case, even in byte 1 to byte 8 to which the write voltage has already been applied by the write driver 16, the transfer gate 3 corresponding to the clock signal CLK0.
Since 20 is turned on, the bit line BL0 in each byte is the column latch 300 and Vpp switch 31 of each byte.
Connected to 0.

In this way, up to byte m are selected, and when the selection of byte m is completed, the address counter 2
6 stops and all transfer gates G1 to Gm
Turn off. However, the program refresh counter 28 periodically repeats the above operation for the program period determined by the erase / program timing control circuit 24b (FIG. 4). Thereby, the memory cell can be programmed.

In the second embodiment described above, a pair of column latch 300 and Vpp switch 310 are provided for one byte, and bit lines BL0 to B within each byte are provided.
L7 goes through transfer gates 320-327 to 1
It is connected to a pair of column latches 300 and Vpp switch 310. During the program cycle, the transfer gates 320 to 327 in each byte are periodically turned on by the clock signals CLK0 to CKL7 periodically generated by the program refresh counter 38.

Therefore, the number of column latches 300 and Vpp switches 310 required for each byte is the same as in the conventional EE.
It is one-eighth of PROM. As a result, there is a margin in the layout of elements, and an EEPROM compatible with high integration can be obtained.

Further, after the address counter 26 is deactivated, only the program refresh counter 28 operates and the parasitic capacitance C of the bit lines BL0 to BL7 in each byte.
_The Vpp switch 310 is activated by detecting the voltage of _BL0 to _CBL7 . As a result, the write voltage can be periodically refreshed to enhance the potential level of the bit line.

In the EEPROM of the second embodiment, the control gates of the memory cells in the same page are common, and the memory cells in the same page are always erased collectively. The present invention can also be applied to an EEPROM in which memory cells in the same page have individual control gates and can be independently erased.

(3) Third Embodiment FIG. 9 is a block diagram showing the structure of an EEPROM according to the third embodiment of the present invention. The EEPROM of FIG. 9 is shown in FIG.
1 is different from the conventional EEPROM in the following points.

A column latch group 35, a transfer gate group 36, a Vpp switch group 37 and a transfer gate group 38 are provided in place of the column latch group 20, the transfer gate group 21 and the Vpp switch group 22 in the EEPROM of FIG. Program refresh counter 33 and Vpp switch 34
Is provided.

The transfer gate group 36 transfers the data held in the column latch group 35 to the Vpp switch group 37.
Communicate to. The transfer gate group 38 connects the Vpp switch group 37 to the bit line in the memory cell array 11. The program refresh counter 33 is controlled by the erasing / program timing control circuit 24C, and the transfer gate groups 36 and 38 at the time of writing.
To control.

FIG. 10 is a circuit diagram showing in detail the configuration of memory cell array 11 shown in FIG. 9 and its peripherals.

The column latch group 35 includes a plurality of column latches 350 to 357. Eight column latches 350 to 357 are provided for each byte. The transfer gate group 36 includes a plurality of transfer gates 360 to 367.
including. 8 transfer gates per byte
60-367 are provided.

The Vpp switch group 37 includes m Vpp switches 370 corresponding to m bytes. The transfer gate group 38 includes a plurality of transfer gates 380 to 380.
Including 387. Eight transfer gates 380 to 387 are provided for each byte.

The program refresh counter 33 is
The clock signals ACLK0 to ACLK7 are applied to the transfer gates 360 to 367 of the respective bytes. Further, the program refresh counter 33 supplies clock signals BCLK0 to BCLK to the transfer gates 380 to 387 of each byte via the Vpp switch 34, respectively.
Give CLK7.

The X decoder 14 and the Y decoder 1
5 includes a Vpp switch. Next, a series of erase / program operations of the EEPROM of FIGS. 9 and 10 will be described. Now, assume that the memory cell of page 1 in FIG. 10 is rewritten.

(Write Cycle) FIG. 11 is a timing chart showing a write cycle. The write cycle is shown in FIG.
This corresponds to the period T1 in the conventional EEPROM timing chart shown in FIG.

First, write data input from the data input / output terminals D0 to D7 is transmitted to the write driver 16 through the I / O buffer 19. Further, the Y decoder 15 selects the Y gate line Y1. As a result, the transfer gate G1 is turned on.

At this time, the program refresh counter 33 operates to operate the clock signals ACLK0 to ACLK7.
And the clock signals BCLK0 to BCLK7 are sequentially raised.

For example, after a certain delay time from the rise of clock signal BCLK0, clock signal ACLK0
Rises. As a result, the transfer gate 380
And the transfer gate 360 is turned on. As a result, the write data DI0 output from the write driver 16
Are written to the byte 1 column latch 350 through the byte 1 bit line BL0.

After the writing to column latch 350 is completed, clock signal ACLK0 falls, and after a certain delay time, clock signal BCLK0 falls. As a result, the transfer gate 360 and the transfer gate 380 are turned off.

Next, the clock signal BCLK1 and the clock signal ACLK1 sequentially rise, and the write driver 16
The write data DI1 output from is written in the byte 1 column latch 351 via the byte 1 bit line BL1. In this way, the column latch 35 in byte 1
Write data DI0 to DI7 output from the write driver 16 are sequentially written to 0 to 357.

The Y decoder 15 sequentially selects the Y gate lines Y2 to Ym, and the write data is written in the column latches 350 to 357 of byte 2 to byte m in the same manner.

In the write cycle, Vpp switch 34 has not yet generated high voltage Vpp, and clock signal BC
LK0 to BCLK7 are power supply voltage levels (normally 5V).

After the storage of write data for all bytes 1 to m in page 1 is completed, all memory cells in page 1 are erased as in the conventional EEPROM.

(Erase Cycle) FIG. 12 is a timing chart showing the erase cycle. Figure 2 shows the erase cycle.
This corresponds to the period T2 in the timing chart of the conventional EEPROM shown in FIG.

X decoder 14 raises the voltage of word line WL1 to high voltage Vpp. Further, the erase signal Erase becomes "H". As a result, the Vpp switch 230 is activated, and the high voltage Vpp is transmitted to the control gate CG1 via the transistor S10. As a result, all memory cells in page 1 are erased. When the erase cycle ends, the program cycle starts.

(Program Cycle) FIG. 13 is a timing chart showing a program cycle. The program cycle corresponds to the period T3 in the timing chart of the conventional EEPROM shown in FIG.

Program refresh counter 33 operates and clock signals ACLK0-ACLK7 and clock signals BCLK0-BCLK7 sequentially rise.

First, the clock signal ACLK0 rises and the transfer gate 360 of each byte is turned on. As a result, the column latch 350 of each byte is set to Vp
It is connected to the p-switch 370. If the write data held in the column latch 350 is “0”, the corresponding Vpp
The switch 370 is activated, and if it is "1", the corresponding Vpp switch 370 is deactivated.

After each Vpp switch 370 becomes stable, clock signal BCLK0 rises and transfer gate 380 is turned on. At this time, the clock signal BCLK
0 becomes the high voltage Vpp level, so activated Vp
The high voltage Vpp is applied to the bit line BL0 connected to the p-switch 370.

Further, the voltage of the word line WL1 is the high voltage Vp.
Since it has risen to p, each bit line BL in page 1
A write voltage of 0V or a high voltage Vpp is applied to the tunnel region of the memory transistor M0 through the select transistor S0 of the memory cell connected to 0. After a certain time, the clock signal BCLK0 falls and the clock signal ACLK0 also falls.

Next, clock signal ACLK1 and clock signal BCLK1 rise, column latch 351 in each byte is connected to corresponding Vpp switch 370, and Vpp switch 370 is connected to corresponding bit line BL1.

In this way, the clock signal ACLK0
To ACLK7 and clock signals BCLK0 to BCLK
7 stands up in sequence. When the clock signals ACLK7 and BCLK7 fall, the clock ACL is restarted.
K0 and BCLK0 rise, and the above operation is repeated.

In this way, the clock signals ACLK0 to ACLK are
A memory cell can be programmed by periodically and repeatedly raising CLK7 and clock signals BCLK0 to BCLK7.

As described above, it generally takes several ms to program a memory cell by utilizing the tunnel effect. Therefore, the program refresh counter 33 is activated during this period, and the write voltage is sequentially applied to the memory cells.

Here, if one selection period (pulse width of clock signals BCLK0 to BCLK7) of each bit line is, for example, 1 μs, then that bit line is selected 7 μs later. During this period, the supply source of the write voltage to the memory cell is cut off. However, the current consumed by the tunnel effect is about several tens pA to several nA, and the parasitic capacitance of the bit line (generally 1-2 pA).
The write voltage can be sufficiently supplied by the electric charge charged in F).

As shown in FIG. 13, although the potential of the bit line slightly drops, the frequencies of the clock signals ACLK0 to ACLK7 and the clock signals BCLK0 to BCLK7 are set so as to maintain the potential enough to cause the tunnel phenomenon. It is possible to stably program the memory cell.

In FIG. 13, bit lines BL0 to BL
Of the seven states, only the state of the bit line BL0 is representatively described.

In the EEPROM of the above third embodiment,
Since the control gates of the memory cells in the same page are common and the memory cells in the same page are always erased collectively, the present invention allows the memory cells in the same page to be individually erased as shown in FIG. It can also be applied to an EEPROM having control gates, erasable independently, and having a page mode writing function.

In FIG. 14, a Vpp switch 230 and a column latch 400 are provided for each byte. The control gate of the memory cell is common to each byte in each page. Each column latch 400
Holds the data designating whether or not to rewrite the memory cell of the corresponding byte.

Further, in the embodiment of FIG. 10, when the write data is written in the column latches 350 to 357, the transfer gates 360 to 367 of the bytes not selected by the Y decoder 15 are also clock signals ACLK0 to ACK.
It is turned on by LK7. Therefore, as shown in FIG.
If the transfer gates 360 to 367 for only the bytes selected by the Y decoder 15 are turned on, more stable write data latching becomes possible.

In the example of FIG. 15, the above function is realized by the inverter 420 and the NOR gates 410 to 417. However, the P-channel transistor 43 is not limited to the NOR gate, but may be, for example, as shown in FIG.
1- and N-channel type transistors 432 may be used. In this case, the same function can be achieved with a small number of transistors.

Further, in the third embodiment, one Vpp switch 37 is provided for every eight bit lines (1 byte).
0 is provided, but V is set for each arbitrary plurality of bit lines.
The same effect can be obtained by providing the pp switch 370.

According to the third embodiment, 1 for each byte.
One Vpp switch 370 may be provided. Also, FIG.
As shown in 0, column latches 350 to 357 provided for each byte can be arranged in the direction along the bit lines BL0 to BL7. Therefore, even if the pitch of the memory cells becomes small, the layout of the column latch becomes easy.

(4) Fourth Embodiment FIG. 17 is a block diagram showing the structure of an EEPROM according to the fourth embodiment of the present invention. The EEPROM of FIG. 17 is different from the conventional EEPROM of FIG. 21 in the following points.

The Vpp switch group 22 in the EEPROM of FIG. 21 is eliminated. Also, the EEPR of FIG.
A column latch group 35, a transfer gate group 36, and a transfer gate group 38 instead of the column latch group 20 and the transfer gate group 21 in the OM.
Is provided, and the program refresh counter 3 is further provided.
3, Vpp switch 34 and Vpp switch 39 are provided.

The transfer gate groups 36 and 38 transmit the data held in the column latch group 35 to the bit lines of the memory cell array 11. The program refresh counter 33 is controlled by the erase / program timing control circuit 24d and controls the transfer gate groups 36 and 38 at the time of writing. Column latch group 35
The power of the above is supplied from the charge pump 23.

FIG. 18 is a circuit diagram showing in detail the structure of memory cell array 11 shown in FIG. 17 and its peripherals.

The column latch group 35 includes a plurality of column latches 350 to 357. Eight column latches 350 to 357 are provided for each byte. The transfer gate group 36 includes a plurality of transfer gates 360 to 3
Including 67. Eight transfer gates 360 to 367 are provided for each byte. The transfer gate group 38 includes a plurality of transfer gates 380 to 38.
Including 7. Eight transfer gates 380 to 387 are provided for each byte.

The column latches 350 to 357 for each byte are connected to the node N3 via transfer gates 360 to 367, respectively. Bit line BL0 in each byte
~ BL7 are transfer gates 380 to 38, respectively
7 to the corresponding node N3.

The program refresh counter 33 is
Transfer gate 36 via Vpp switch 39
0 to 367 to clock signals ACLK0 to ACL respectively
Give K7. Further, the program refresh counter 33 supplies clock signals BCLK0 to transfer gates 380 to 387 via the Vpp switch 34, respectively.
~ Give BCLK7.

Next, the EEPROM of FIG. 17 and FIG.
The erase / program operation will be described in detail. now,
It is assumed that the memory cell of page 1 in FIG. 18 is rewritten.

(Write Cycle) First, write data input from the data input / output terminals D0 to D7 is transmitted to the write driver 16 through the I / O buffer 19. Also, Y
The decoder 15 selects the Y gate line Y1. At this time, the program refresh counter 33 operates,
Clock signals ACLK0 to ACLK7 and clock signals BCLK0 to BCLK7 are sequentially raised.

First, clock signal ACLK0 rises after a certain delay time from the rise of clock signal BCLK0. Therefore, the write data DI0 output from the write driver 16 is written into the byte 1 column latch 350 through the byte 1 bit line BL0. The clock signal ACLK0 falls after the writing to the column latch 350 ends, and the clock signal BCLK0 falls after a certain delay time.

Next, clock signals BCLK1 and AC
LK1 rises, and the write data DI1 output from the write driver 16 is written in the byte 1 column latch 351. In this way, when writing to all the column latches 350 to 357 in the byte 1 is completed, similarly, the column latches 350 to
Writing to 357 is performed. At this time, the charge pump 23 in FIG. 17 is not yet operating, and the outputs of the column latches 350 to 357 are at the power supply voltage level (normally 5
V).

(Erase Cycle) After storage of write data for all bytes 1 to m in page 1 is completed, charge pump 35 is activated and all memories in page 1 are activated in the same manner as the conventional EEPROM. The cell is erased.

X decoder 15 raises the voltage of word line WL1 to high voltage Vpp. Further, the erase signal Erase becomes "H". As a result, the Vpp switch 230 is activated, and the high voltage Vpp is transmitted to the control gate CG1 via the transistor S10. As a result, all memory cells in page 1 are erased. When the erase cycle ends, the program cycle starts.

(Program Cycle) The program refresh counter 33 operates again, and the clock signal ACL
K0 to ACLK7 and clock signals BCLK0 to BC
LK7 is launched sequentially.

First, clock signals ACLK0 and BC
LK0 rises. Thereby, the column latch 350 in each byte is simultaneously connected to the bit line BL0 in the same byte. At this time, the power supply of the column latch group 35 is the high voltage Vpp, and the clock signal BCLK0 is also at the high voltage Vpp level. Therefore, 0V or high voltage Vpp is applied to the bit line BL0 in each byte according to the write data.

The voltage of the word line WL1 is also the high voltage Vp.
Since it has risen to p, bit line BL0 in each page
A write voltage of 0 V or a high voltage Vpp is applied to the tunnel region of the memory transistor M0 through the selection transistor S0 of the memory cell connected to the memory cell. After a certain time, clock signals ACLK0 and BCLK0 fall.

Next, clock signal ACLK1 and clock signal BCLK1 rise, and column latch 351 in each byte is connected to bit line BL1 in the same byte.

In this way, the clock signal ACLK0
To ACLK7 and clock signals BCLK0 to BCLK
7 stands up in sequence. When the clock signals ACLK7 and BCLK7 fall, the clock signal A
CLK0 and clock signal BCLK0 rise. By repeating the above operation periodically, the memory cell can be programmed.

As described above, it generally takes several ms to program a memory cell by utilizing the tunnel effect. Therefore, the program refresh counter 33 is activated during this period, and the write voltage is sequentially applied to the memory cells.

Here, if one selection period of each bit line (pulse width of clock signals BCLK0 to BCLK7) is, for example, 1 μs, then that bit line is selected 7 μs later. During this period, the supply source of the write voltage to the memory cell is cut off. However, the current consumed by the tunnel effect is about several tens pA to several nA, and the parasitic capacitance of the bit line (generally 1-2 pA).
The write voltage can be sufficiently supplied by the electric charge charged in F).

In the EEPROM of the above fourth embodiment,
The control gates of the memory cells in the same page are common, and the memory cells in the same page are always erased collectively. However, in the present invention, the memory cells in the same page have individual control gates. Also, the present invention can be applied to an EEPROM having a structure that can be independently erased.

According to the fourth embodiment, V for each byte
There is no need to provide a pp switch. In addition, as shown in FIG. 18, a column latch 350 provided for each byte.
.About.357 can be arranged in the direction along the bit lines BL0 to BL7. Therefore, even if the pitch of the memory cells becomes small, the layout of the column latch becomes easy.

[0163]

According to the first aspect of the present invention, it is not necessary to provide a high voltage switch and a column latch for each bit line, and the layout of the data holding means corresponding to the column latch can be performed with a margin. Therefore, the pattern layout is facilitated, and a nonvolatile semiconductor memory device having a page mode writing function and suitable for high integration can be obtained.

According to the second invention, the number of high voltage switch means and latch means connected to each bit line is significantly reduced. Therefore, the pattern layout is facilitated, and a nonvolatile semiconductor memory device having a page mode writing function and suitable for high integration can be obtained.

According to the third invention, the number of high voltage switch means is significantly reduced, and the pattern layout of a plurality of latch means is facilitated. Therefore, it is possible to obtain a nonvolatile semiconductor memory device having a page mode writing function and suitable for high integration.

According to the fourth invention, it is not necessary to provide a high voltage switch for each bit line, and the pattern layout of a plurality of latch means becomes easy. Therefore, a semiconductor memory device having a page mode writing function and suitable for high integration can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an EEPROM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a main part of the EEPROM of FIG.

FIG. 3 is a timing chart for explaining a program cycle of the EEPROM of the first embodiment.

FIG. 4 is a block diagram showing a configuration of an EEPROM according to a second embodiment of the present invention.

5 is a circuit diagram showing in detail a configuration of a main part of the EEPROM of FIG.

FIG. 6 is a circuit diagram showing a configuration of a column latch and a Vpp switch.

FIG. 7 is a timing chart for explaining operations of a column latch and a Vpp switch.

FIG. 8 is a timing chart for explaining a program cycle of the EEPROM of the second embodiment.

FIG. 9 is a block diagram showing a configuration of an EEPROM according to a third embodiment of the present invention.

10 is a circuit diagram showing in detail a configuration of a main part of the EEPROM of FIG.

FIG. 11 is a timing chart for explaining a writing cycle of the EEPROM of the third embodiment.

FIG. 12 is a timing chart for explaining an erase cycle of the EEPROM of the third embodiment.

FIG. 13 is a timing chart for explaining a program cycle of the EEPROM of the third embodiment.

FIG. 14 is a circuit diagram showing another example of the configuration of the main part of the EEPROM of the third embodiment.

FIG. 15 is a circuit diagram showing still another example of the configuration of the main part of the EEPROM of the third embodiment.

16 is a circuit diagram showing a configuration example used in place of the NOR gate of FIG.

FIG. 17 is an EEPROM according to the fourth embodiment of the present invention.
3 is a block diagram showing the configuration of FIG.

FIG. 18 is a circuit diagram showing in detail a configuration of a main part of the EEPROM of FIG.

FIG. 19 is a sectional view of a memory cell of a general EEPROM.

20 is a diagram showing operating characteristics of the memory cell of the EEPROM of FIG.

FIG. 21 is a block diagram showing a configuration of a conventional EEPROM.

22 is a circuit diagram showing in detail the configuration of a main part of the EEPROM of FIG. 21. FIG.

FIG. 23 is a timing chart for explaining the erase / program operation of the conventional EEPROM.

[Explanation of symbols]

11 memory cell array 12 X system address buffer 13 Y system address buffer 14 X decoder 15 Y decoder 16 write driver 17 sense amplifier 18 Y gate 19 I / O buffer 23 charge pumps 24a, 24b, 24c, 24d erase / program timing control circuit 25 write / read control circuit 26 address counter 27 data latch 28, 33 program refresh counter 29, 31, 37 Vpp switch group 30, 35 column latch group 32, 36, 38 transfer gate group Or shows a considerable part.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical display location H01L 29/792 8225-4M H01L 29/78 371 (72) Inventor Yoshikazu Miyawaki Mizuhara, Itami City, Hyogo Prefecture 4-chome Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Tomoshi Futatsuya 4-chome, Mizuhara, Itami City, Hyogo Prefecture 4-1-1 Mitsubishi Electric Co., Ltd.

Claims (8)

[Claims] 1. A non-volatile semiconductor memory device capable of electrically programming / erasing a plurality of bytes collectively, comprising a plurality of bit lines, a plurality of memory cells connected to the plurality of bit lines, and an external device. Input buffer means for inputting write data given from the data holding means, data holding means for holding the write data input by the input buffer means, and a write voltage generated according to the write data held by the data holding means A non-volatile write voltage generating means for selecting a plurality of bit lines and a selecting means for periodically selecting each of the plurality of bit lines and connecting the selected bit line to the write voltage generating means during programming. Semiconductor memory device. 2. The selecting means includes a plurality of transfer gate means connected between each of the plurality of bit lines and the write voltage generating means, and a cycle of each of the plurality of transfer gate means during programming. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising: a counter unit that repeatedly repeatedly selects and turns on. 3. A non-volatile semiconductor memory device capable of electrically programming / erasing a plurality of bytes collectively, comprising a plurality of bit lines and a plurality of memory cells connected to the plurality of bit lines. Write data supply means for giving the embedded data to each of the plurality of bit lines, and a plurality of sets of write voltage determining means each comprising a high voltage switch means and a latch means for determining the write voltage according to the write data. Equipped with
Each of the plurality of sets of write voltage determining means is provided commonly to a plurality of predetermined bit lines, and each of the plurality of bit lines is periodically and repeatedly selected at the time of programming to correspond to the selected bit line. A non-volatile semiconductor memory device further comprising selection means connected to write voltage determination means. 4. The selecting means includes a plurality of transfer gate means connected between each of the plurality of bit lines and a corresponding write voltage determining means, and each of the plurality of transfer gate means during programming. 4. The non-volatile semiconductor memory device according to claim 3, further comprising: a counter unit that periodically and repeatedly selects and turns on. 5. A non-volatile semiconductor memory device capable of electrically programming / erasing a plurality of bytes collectively, comprising a plurality of bit lines, a plurality of memory cells connected to the plurality of bit lines, and A plurality of latch means provided corresponding to a plurality of bit lines, each holding write data;
A plurality of high voltage switch means each provided commonly to a plurality of predetermined bit lines, and each high voltage switch means and a corresponding plurality of predetermined latch means determine a write voltage according to write data. Constitutes a write voltage determination means,
When programming, each of the plurality of bit lines and the corresponding latch means is periodically and repeatedly selected, and a selection means for connecting the selected bit line to the corresponding high voltage switch means and the selected latch means is further provided. , Non-volatile semiconductor memory device. 6. The selection means includes a plurality of first nodes respectively connected between a plurality of nodes respectively connected to the plurality of high voltage switch means and a node corresponding to each of the plurality of bit lines. Transfer gate means of
A plurality of second transfer gate means respectively connected between each of the plurality of latch means and a corresponding node, and each of the plurality of first transfer gate means and the plurality of second transfer during programming. 6. The non-volatile semiconductor memory device according to claim 5, further comprising counter means for periodically and repeatedly selecting and turning on each of the gate means. 7. A non-volatile semiconductor memory device capable of electrically programming / erasing a plurality of bytes collectively, comprising a plurality of bit lines, a plurality of memory cells connected to the plurality of bit lines, and A plurality of latch means provided corresponding to a plurality of bit lines, each holding a ground voltage or a predetermined high voltage according to write data, and at the time of programming,
A non-volatile semiconductor memory device comprising: a selection unit that repeatedly and repeatedly selects each of the plurality of bit lines and a corresponding latch unit and connects the selected bit line to the selected latch unit. 8. The selection means is provided between a plurality of nodes, each of which is commonly provided for a plurality of predetermined bit lines and a plurality of predetermined latch means, and a node corresponding to each of the plurality of bit lines. A plurality of first transfer gate means connected to each other, a plurality of second transfer gate means connected to each of the plurality of latch means and a corresponding node, and the plurality of first transfer gate means at the time of programming. 8. The non-volatile semiconductor memory device according to claim 7, further comprising: counter means for cyclically repeatedly selecting and turning on each of the transfer gate means and each of the plurality of second transfer gate means.