JPH056664A - Memory refresh control system - Google Patents

Abstract

PURPOSE:To reduce an operating current at the time of refreshing at one time and to prevent an erroneous operation by supplying a refresh control signal having a different timing at each memory block to a RAS terminal. CONSTITUTION:Refresh control signals RAS1-n having different timings corresponding to memory blocks 1-n, are supplied from a refresh timing generator 1 via a shift register 6 in a memory controller 2 according to a REFO signal. Thus, since refreshing power refreshes the respective blocks at the different timings, it is distributed to be reduced. Accordingly, consumed current concentrated at one time is suppressed to prevent an erroneous operation upon variation in a power source.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory refresh control system.

[0002]

2. Description of the Related Art Since the information stored in DRAM is dynamic and transient, it is necessary to refresh it at regular intervals. Conventionally, in this type of memory device, all memory elements are refreshed at once. Figure 3
(Block diagram) and FIG. 4 (waveform diagram).

As shown in FIG. 3, in the memory blocks 3 to n, which are DRAM-based memory devices, RAS signals are simultaneously supplied to all RAS terminals for refreshing. In refreshing at that time, as shown in FIG. 4, the current consumption is concentrated at a temporary point and has a very large peak value, so that a momentary fluctuation of the power supply voltage or noise is generated, which easily causes a malfunction. Was to reduce the reliability of the.

[0004]

In the conventional memory refresh control system, the current consumption is concentrated at a temporary point and has a very large peak value, so that an instantaneous power supply voltage fluctuation or noise is generated. There is a drawback in that malfunctions are likely to occur and the reliability of the device is reduced.

The object of the present invention is to remedy the above-mentioned drawbacks,
This is to reduce the peak current consumption during refreshing, thereby suppressing fluctuations in power supply, preventing malfunctions, and improving device reliability.

[0006]

The memory refresh control system of the present invention is a DRAM divided into a plurality of blocks.
A memory controller configured to time-division the RAS signal for performing refresh control of the memory configured as described above and supplying the RAS signal to each of the divided memory blocks at different timings by the number of blocks, and accessing in accordance with the increase in memory blocks at the refresh timing. And a refresh timing generation circuit for extending a signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining its operation. 1, a memory block 1, a memory block 2, ..., A memory block n indicate each memory block by dividing all memory elements into n pieces.
In response to the 0 signal, the memory controller 2 uses the shift register 6 to perform control signals RAS1, RAS for refreshing the memory blocks 1, memory blocks 2, ...
2, ..., RASn are supplied to the RAS terminals.

The signal waveform at that time is the signal R as shown in FIG.
AS1, RAS2, ... RASn is T _1, T ₂ respectively for each memory block, so that ... T _n and the refresh cycle is deviated. By doing so, the power for refreshing is such that by refreshing each block at different timings, the current consumption at that time is dispersed at timings T ₁ , T ₂ , ... T _n as shown in FIG. It can be seen that a small value occurs at the point of. As a result, current consumption concentrated at a temporary point is suppressed, so that malfunction due to power supply fluctuation can be prevented and the reliability of the device can be improved.

In the above description, the case where the block 1, the block 2, ..., The block n is always mounted has been described. However, when the block m (m <n) and the subsequent blocks are not standardly mounted due to the handling of the additional memory, At the time of power-on of the device, the presence / absence of the additional memory is determined, and the information is set in the shift register 6 of the memory controller 2 to set the CPU at the time t ₁ when the refresh cycle of the block 2 is completed.
The access stop request signal to the memory can be withdrawn and access to the memory can be permitted.

[0010]

As described above, according to the present invention, by supplying the control signal for performing refresh at different timings to each memory block to the RAS terminal, the operating current at the time of refresh at the time of refresh is reduced and the power supply fluctuation is suppressed. This has the effect of preventing erroneous pressing operations and increasing the reliability of the entire device.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram of FIG.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a waveform diagram of FIG.

[Explanation of symbols]

1 refresh timing generation circuit 2 memory controller 3, 4 n memory block 6 shift register REF0 timing signal for refreshing RAS1, RAS2, ... RASn RAS signal of each memory block

Claims (1)

Claim: What is claimed is: 1. A RAS signal for performing refresh control of a memory composed of DRAM divided into a plurality of blocks is time-divided, and each divided memory block is divided into blocks by the number of blocks at different timings. A memory refresh control method comprising: a memory controller that supplies a RAS signal; and a refresh timing generation circuit that extends an access stop signal according to an increase in memory blocks at a refresh timing.