JPH056657A - Semiconductor memory elements - Google Patents

Abstract

PURPOSE:To enable the number of terminals to be reduced and a cycle time to be improved for multiple-bit configuration and multiple-bank configuration accompanied by increase in capacity of a semiconductor memory element by operating a plurality memory arrays independently. CONSTITUTION:A title item is provided with a plurality of address registers 1 and 2 with a common input, one write data register 3, and memory arrays 4 and 5 corresponding to each of a plurality of address registers 1 and 2. Also, an output of the write data register 3 is connected to memory arrays 4 and 5 commonly and the memory arrays 5 are provided with control terminals 101-111 so that data can be read and written independently. These are housed on a same substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to
The present invention relates to a semiconductor memory element which is composed of a plurality of memory blocks and can be independently read and written.

[0002]

2. Description of the Related Art A conventional semiconductor memory has a general-purpose function and structure, and has a data bit width of n bits and an address of m bits.
It has a structure of n bits × m words consisting of words.
The n bits can be read and written at the same time. Generally, each bit cannot operate independently. As the storage capacity increases according to the trend, the address increases. However, in small and medium-sized devices, the storage capacity at the system level has not necessarily expanded four times in three years, so the increase in the storage capacity of semiconductor memory elements should be used to reduce the number of elements. In that case, the data width bit n must be expanded.

Further, since there is a great demand for improving the memory performance accompanying the improvement in the performance of the processor, the memory device has dealt with by introducing interleaving. In that case, however, the basic unit configuration becomes larger depending on the number of interleaving, so that the basic configuration is increased. Storage capacity will increase. In the future, it is inevitable that the structure will be complicated, and the conventional general-purpose RAM will not meet the requirements.

[0004]

As described above, when the conventional semiconductor memory device is applied to the device as the memory capacity increases, the basic memory capacity unit becomes large and the performance is not effective. There is a drawback that.

[0005]

The semiconductor memory device of the present invention has a plurality of address registers having a common input, one write data register, and a memory array corresponding to each of the plurality of address registers. The outputs of the write data registers are commonly connected to the plurality of memory arrays, and the plurality of memory arrays are provided with control terminals so that they can be independently read and written, and are housed on the same substrate. And a driver circuit for transmitting the output of the selection circuit to the input signal line of the write data register, the read data register including a plurality of read data registers corresponding to each memory array, Driver having read data from the plurality of memory arrays for each of the plurality of memory arrays Type the road, select driver circuit consists of output to the read data signal line.

[0006]

1 is a block diagram showing a first embodiment of the present invention. 1 is the address register bank 0 (address R
EG B0), 2 is an address register bank 1 (address REG B1), 3 is a write data register (write data REG), 4 is a RAM array (RAM) of bank 0
Arrays 0), 5 are RAM arrays of bank 1 (RAM array 1), 6 are read data register bank 0 (read data REGB0), 7 is read data register bank 1
(Read data REG B1), 8 is a read data selection circuit, and 101 to 111 are terminals of the semiconductor memory device. However, the power supply and ground terminals are omitted.
101 is a bank selection 0 signal (B50) 102 is a bank selection 1 signal (BS1), 103 is an address signal (AD
D), 104 are bank 0 chip select signals (CE0), 1
Reference numeral 05 is a bank 1 chip selection signal (CE1), 106 is a bank 0 write signal (WE0), 107 is a bank 1 write signal (WE1), 108 is a ride data signal (WD),
109 is a read data signal (RD) 110 is a read data selection signal (RD5), 111 is a clock (CLK)
Is.

Regarding the RAM array, even in the DRAM,
An SRAM may be used, but a 4 Mb (megabit) DRAM is used for convenience of description. 4 RAM arrays 0 and 5 RA
The M array 1 is composed of 8 bits × 256 kw and can operate independently. Therefore 2 Mb DRA
Two sets of M are mounted on the same substrate.

The address signal 103 is shared by bank 0 and bank 1 in order to save the number of terminals of the device. A clock signal 111 (CLK) is applied to this chip and applied to each register. There is one write data REG3 shared by bank 0 and bank 1. The present memory device has a multi-bit structure and a high-speed cycle time, which is difficult to realize when a general-purpose DRAM is used.

The RAM array (0) 4 and the RAM array (1) 5 have chip enables independently so that they can be activated independently. DRA with such a configuration
In the case of M, the memory device has a limited package size, for example, 16 PIN, 18 PIN DIP or 26 PIN SO.
It is considered that the address multiplex for loading on J is not always necessary. Therefore, the address multiplex is not adopted in this example. Chip enable C
It becomes operable by turning on E0 104 and CE1 105. Since the RAM arrays are independent of each other, they can be accessed at any time, but normally, by interleaving the two RAM arrays, the cycle time as a chip can be improved.

An address to be accessed is sent to the ADD signal 103 every clock cycle. The sent address is held in the address REG B0 1 by the bank selection 0 signal (BS0). The chip enable 0 signal (CE0) 104 is added according to the timing when the address is held and propagated to the RAM array (0) 4, and R is added.
AM access is performed. In the case of reading, the read data is held in the read data REG B06 after a predetermined time. The address signal sent via the ADD signal 103 after one clock is the bank selection 1 signal (B
It is held at the address REG B12 by S1).

A chip enable 1 signal (CE1) 105 is added according to the timing at which the address is held and propagated to the RAM array 15, and RAM access is performed. When reading, read data RE after a predetermined time
The read data is held in GB17. In the case of writing, the data is held in the write data REG3, but since the data for the bank to be written is guaranteed for only one clock, the write pulse (WE0) 106 or the write pulse (WE0) 106 is matched with the write data during one clock. WE1) 107 is input and writing is performed. The read data is sent to the read data signal path 109 every clock by the read data selection circuit 8 and the read data selection signal (RDS) 110.

The first embodiment can supply a memory device capable of interleaved operation without increasing the number of input / output pins and the address direction for a DRAM having a multi-bit structure which does not address multiplex. It is in.

FIG. 2 is a block diagram showing a second embodiment of the present invention. Address corresponding to bank REG B0
11, address REG B1 12, RAM array 0
14, RAM array 115, read data REG B
0 16 and read data REG B1 17, read data selection circuit 18, write data REG1 common to banks
3, composed of a gate circuit 19.

The difference from the first embodiment is that the read data output is connected to the write data signal input line via the driver circuit 19 and is bidirectional. At the time of reading, the output control signal (OEN) 209 is turned on to enable the gate circuit 19 and the read data is transmitted. Output control signal (OEN) 109 during writing
Is turned off and the output of the driver circuit 19 is set to high impedance to disconnect the driver circuit 19 and input write data. Other operations are the same as those in the first embodiment.

FIG. 3 is a block diagram showing a third embodiment of the present invention. Address corresponding to bank REG B0
21 and address REG B1 22, RAM array 0
24, RAM array 125, write data REG 23 common to banks, and driver circuits 26 and 27 for outputting read data from the RAM array.

The difference from the first embodiment is that the data read from the RAM array (0) 24 and the RAM array (1) 25 corresponding to the bank is output to the read data signal RD 311 via the gate circuits 26 and 27. In RAM
When reading from the array (0) 24, the driver circuit 2
6 is turned on by the enable signal B0E 309, while the driver circuit 27 is turned off by the enable signal B1E 310, the output becomes high impedance.
Conversely, when reading from the RAM array (1) 25, the driver circuit 26 outputs the enable signal B0E 309
The output is set to high impedance with FF, and the driver circuit 27 turns on the enable signal B1E310.

Although only the two-bank configuration has been described in this embodiment, the same configuration can be applied to two or more banks.

[0018]

As described above, the present invention provides a semiconductor memory device that is convenient in device design by reducing the number of terminals and improving the cycle time in a multi-bit configuration and a multi-bank configuration that accompanies an increase in the capacity of a semiconductor memory device. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

[Explanation of symbols]

1 Address register B0 2 Address register B1 3 Write data register 4 RAM array (0) 5 RAM array (1) 6 Read data register B0 7 Read data register B1 8 Read data selection circuit 11 Address register B0 12 Address register B1 13 Read data register B0 14 RAM array (0) 15 RAM array (1) 16 Read data register B0 17 Read data register B1 18 Read data selection circuit 19 Driver circuit 21 Address Register B0 22 Address register B1 23 Write Data Register 24 RAM array (0) 25 RAM array (1) 26,27 driver circuit

Claims (3)

[Claims] 1. A plurality of address registers having a common input, a write data register consisting of one and a memory array corresponding to each of the plurality of address registers, and the outputs of the write data registers are commonly provided. A semiconductor memory device, wherein the plurality of memory arrays are sent to the memory array, and the plurality of memory arrays are provided with control terminals so that they can operate independently and are accommodated on the same substrate. 2. A plurality of read data registers for holding read data from the plurality of memory arrays, a selection circuit for selecting one of the plurality of read registers, and an output of the selection circuit. 2. The semiconductor memory device according to claim 1, further comprising a driver circuit for transmitting the data to the input signal line of the write data register, wherein the data signal terminal is bidirectional. 3. The read data of the plurality of memory arrays is input to a driver circuit provided for each of the plurality of memory arrays, and is selected and output to a read data signal line. Semiconductor memory device.