JPH0566029B2 - - Google Patents
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- Publication number
- JPH0566029B2 JPH0566029B2 JP11630980A JP11630980A JPH0566029B2 JP H0566029 B2 JPH0566029 B2 JP H0566029B2 JP 11630980 A JP11630980 A JP 11630980A JP 11630980 A JP11630980 A JP 11630980A JP H0566029 B2 JPH0566029 B2 JP H0566029B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate electrode
- substrate
- silicon substrate
- type silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 description 6
- -1 boron ions Chemical class 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に係り、特に絶縁ゲート電
界効果トランジスタ（以下IGFETと略す）の構
成に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of an insulated gate field effect transistor (hereinafter abbreviated as IGFET).
従来よりIGFETは集積回路の構成素子として
大量に製造されて来た。又、高性能集積回路の製
造即ち高速動作、低消費電力、高集積度をはかる
ためには回路を構成するIGFETの小型化が有効
であり様々な努力が払われてきた。IGFETの小
型化は、比例縮小則に従うのが一般的でつまり、
比較的寸法の大きな素子を基準として、各寸法を
比例縮小すると共に、基板の不純物濃度を逆に比
例増大させるものである。しかし、近年、
IGFETの高集積化が著しく進み、IGFETのチヤ
ネル長が1μm近くなると、前記比例縮小則に従つ
てもいわゆる短チヤネル効果が顕著になり、しき
い値電圧の低下（ゲート長が短いことが原因）や
ホツトエレクトロントラツピングによる不安定性
が問題になる。 Traditionally, IGFETs have been manufactured in large quantities as components of integrated circuits. Furthermore, in order to manufacture high-performance integrated circuits, that is, to achieve high-speed operation, low power consumption, and high degree of integration, it is effective to miniaturize the IGFETs that constitute the circuits, and various efforts have been made. Miniaturization of IGFETs generally follows the proportional reduction law, that is,
Based on an element having relatively large dimensions, each dimension is proportionally reduced, and the impurity concentration of the substrate is proportionally increased. However, in recent years,
As the integration of IGFETs increases significantly and the channel length of IGFETs approaches 1 μm, the so-called short channel effect becomes noticeable even if the proportional reduction law is followed, and the threshold voltage decreases (caused by the short gate length). Instability due to hot electron trapping is a problem.
本発明者らはこの対策として比例縮小則で与え
られるよりも、遥かに薄いゲート絶縁膜を採用す
ることが有効であることを見い出している。 The present inventors have found that it is effective to employ a gate insulating film that is much thinner than that given by the proportional reduction law as a countermeasure to this problem.
（International Solid−State Circuits
Conpenence Digest op Technical Paper，Vol.
XXP74，1980）
ところが、そのような比例縮小則で与えられる
よりも遥に薄いゲート絶縁膜、或いは比較的薄く
且つ誘電率の大きなゲート絶縁膜を用いると、し
きい値電圧の著しい低下が問題になる。このしき
い値電圧の著しい低下は、ゲート長の長さにかか
わらず、しきい値の絶対値が全体的に低下するこ
とによるものである。このしきい値電圧の著しい
低下を補正するためには以下の手法が考えられ
る。 (International Solid-State Circuits
Compensation Digest op Technical Paper, Vol.
XXP74, 1980) However, when using a gate insulating film that is much thinner than that given by the proportional reduction law, or a gate insulating film that is relatively thin and has a high dielectric constant, a significant drop in threshold voltage becomes a problem. Become. This significant decrease in threshold voltage is due to the overall decrease in the absolute value of the threshold, regardless of the gate length. In order to correct this significant drop in threshold voltage, the following method can be considered.
(i) 基板の不純物濃度を高くする。(i) Increase the impurity concentration of the substrate.
(ii) チヤネルイオン注入等により、素子動作に係
る基板表面近傍の不純物濃度を高くする。(ii) Increase the impurity concentration near the substrate surface related to device operation by channel ion implantation or the like.
(i)の方法では、IGFETのソース、ドレイン領
域と基板との間の寄性容量の増大を伴い好ましく
ない。そこで本発明では(ii)の方法による補正を試
みた。 The method (i) is undesirable because it increases the parasitic capacitance between the source and drain regions of the IGFET and the substrate. Therefore, in the present invention, correction using method (ii) was attempted.
第１図(ii)の方法を実施した場合のボロンイオン
注入量（単位、cm-2）とIGFETの相互コンダク
タンス（単位、mmho）の関係を示したものであ
る。第１図はＰ型基板上に作成したｎチヤネル
IGFETの場合で、ボロンイオンは50KeVのエネ
ルギーで注入し、イオン注入後の熱処理を十分に
行なつたものである。注入量が５×1012（cm-2）
以上になると相互コンダクタンスは急激に低下
し、該値以上のボロンイオンの注入は好ましくな
い事を示している。 This figure shows the relationship between the boron ion implantation amount (unit, cm -2 ) and the mutual conductance of IGFET (unit, mmho) when the method shown in FIG. 1(ii) is carried out. Figure 1 shows an n-channel created on a P-type substrate.
In the case of an IGFET, boron ions are implanted with an energy of 50 KeV, and a sufficient heat treatment is performed after ion implantation. Injection volume is 5×10 12 (cm -2 )
Above this value, the mutual conductance decreases rapidly, indicating that implantation of boron ions exceeding this value is not desirable.
本発明は十分な相互コンダクタンスを確保した
上で注入可能なボロンイオンの最大値５×1012
（cm-2）で基板にイオン注入を行ない、従来実施
可能とされていた厚さ以下の薄いゲート絶縁膜、
又は従来に比べ膜厚薄く且つ誘電率の大きなゲー
ト絶縁膜を、ゲート電極を選択することにより、
使用可能とし、従来作成の困難であつたチヤネル
長約1μm近傍あるいはそれ以下のIGFETを提供
するものである。 The present invention provides a maximum implantable boron ion amount of 5×10 12 while ensuring sufficient mutual conductance.
By implanting ions into the substrate at
Or, by selecting a gate insulating film that is thinner and has a higher dielectric constant than conventional gate electrodes,
The present invention provides an IGFET with a channel length of about 1 μm or less, which has been difficult to create in the past.
本発明の実施が可能である理由を以下に示す。 The reason why the present invention can be implemented is shown below.
表面反転層をチヤネルとするIGFETのしきい
値電圧VTHは式の様に表すことができる。 The threshold voltage V TH of an IGFET with a surface inversion layer as a channel can be expressed as in the following equation.
VTH＝VFB＋2ψB＋１／Ci√4S A B
（ただし VFB＝φM−φS＋QfS／Ci）
ここでVFBはフラツトバンド電圧、ψBは基板の
フエルミレベル、Ciはゲート絶縁膜容量、εsは基
体の誘電率、ｑは電子電荷、NAは基板の不純物
濃度、QfSは表面準位電荷、φM，φSはそれぞれゲ
ート電極、半導体基板の仕事関数である。ただし
ここで仕事関数φM，φSは絶縁膜の伝導帯のバン
ド端とゲート電極のフエルミレベル又は半導体基
板のフエルミレベルとのエネルギー差（単位、
eV）で定義される値である。 V TH = V FB +2ψ B +1/Ci√4 S A B (where V FB =φ M −φ S +Q fS /Ci) Here, V FB is the flat band voltage, ψ B is the fermi level of the substrate, and Ci is the gate insulating film. Capacitance, εs is the dielectric constant of the substrate, q is the electronic charge, N A is the impurity concentration of the substrate, Q fS is the surface state charge, and φ M and φ S are the work functions of the gate electrode and the semiconductor substrate, respectively. However, here, the work functions φ M and φ S are the energy difference (unit:
eV).
今、半導体基板をシリコンと仮定し前述の通り
十分なる相互コンダクタンスを確保した上で注入
可能なポロンイオンの最大値５×1012（cm2-2）を
50（KeV）のエネルギーで基板にイオン注入を行
ない、不純物の広がりが基板表面から約3000Å程
度になつているとする。以上の条件により、基板
表面近傍での不純物濃度NA＝1.67×1017（cm-3）、
フラツトバンド電圧ψB＝0.42（eV）、基板の仕事
関数ψS＝4.22（eV）基体の誘電率εS＝1.04×10-12
（Ｆ／cm）を得る。電子電荷ｑ＝1.6×10-19(C)と
して、前記の各値を式に代入すると、
VTH＝φM−3.38＋QfS／Ci＋（１／Ci）×2.16×
10-7
となる。ここで表面準位電荷QfSは、製造プロセ
スの清浄化により十分小さくでき、又本発明に於
いてゲート絶縁膜は膜厚の非常に薄いものを用い
ているためゲート絶縁膜容量Ciの値は十分大きく
なつているので、QfS／Ciの項は無視できるとす
る。 Now, assuming that the semiconductor substrate is silicon and ensuring sufficient mutual conductance as described above, the maximum amount of poron ions that can be implanted is 5×10 12 (cm 2-2 ).
Suppose that ions are implanted into the substrate at an energy of 50 (KeV), and the impurity spreads to about 3000 Å from the substrate surface. Under the above conditions, the impurity concentration near the substrate surface N A = 1.67×10 17 (cm -3 ),
Flat band voltage ψ B = 0.42 (eV), substrate work function ψ S = 4.22 (eV), substrate dielectric constant ε S = 1.04×10 -12
(F/cm) is obtained. Assuming electronic charge q=1.6×10 -19 (C) and substituting each value above into the formula, V TH =φ M −3.38+Q fS /Ci+(1/Ci)×2.16×
10 -7 . Here, the surface state charge Q fS can be made sufficiently small by cleaning the manufacturing process, and since the gate insulating film used in the present invention is very thin, the value of the gate insulating film capacitance Ci is It is assumed that the term Q fS /Ci can be ignored because it is sufficiently large.
一方、しきい値電圧VTHに対する要求は、現在
一般的に用いられている場合の値として、TTL
（Transistor＜couplecl＞Transistor Logic）の
低レベルの値0.4(V)に素子作成上の技術的に不確
定な要素のマージン±20（％）を確保し偏差を±
0.1(V)認める場合
VTH±0.1≧0.4×1.2
VTH≧0.58
従つてVTH≧0.6(V)を与えれば十分である。 On the other hand, the requirement for threshold voltage V TH is TTL
(Transistor<couplecl>Transistor Logic) low level value 0.4(V), ensure a margin of ±20(%) for technically uncertain elements in device creation, and reduce the deviation to ±20(%).
If 0.1(V) is allowed, V TH ±0.1≧0.4×1.2 V TH ≧0.58 Therefore, it is sufficient to provide V TH ≧0.6(V).
又、サブスレシヨールドに関しては、その傾き
を現在一般的に用いられているMOSトランジス
タの値80（mv／decado）とすれば0.6(V)／80（mv）
＝7.5であり、ゲート電圧が、０(V)からしきい値
電圧VTH≧0.6になるまで電流の変化量は少なくと
も７桁の変化が見込めるため、前述の通りVTH≧
0.6(V)を与えれば十分である。 Regarding the sub-threshold, if the slope is 80 (mv/decado) of the currently commonly used MOS transistor, it is 0.6 (V)/80 (mv).
= 7.5, and the amount of change in current is expected to change by at least 7 orders of magnitude until the gate voltage reaches the threshold voltage V TH ≧0.6 from 0 (V), so as mentioned above, V TH ≧
It is sufficient to give 0.6(V).
式にQfs／Ci≒０、並びにVTH≧0.6(V)を適用
すると
φM≧3.98−2.16×10-7×１／Ci
の条件を得る。 Applying Qfs/Ci≒0 and V TH ≧0.6(V) to the equation, we obtain the condition φ M ≧3.98−2.16×10 −7 ×1/Ci.
ここでゲート絶縁膜の膜厚をdi、誘電率をεiと
するとゲート絶縁膜容量CiはCi＝εi／di（Ｆ／cm2）
で表わされるので式は以下の様に書き直す事が
出来る。 Here, if the film thickness of the gate insulating film is di and the dielectric constant is εi, the gate insulating film capacitance Ci is Ci=εi/di (F/cm 2 )
Therefore, the formula can be rewritten as follows.
φM≧3.98−2.16×10-7×di／si
従来のIGFETの構造では、ゲート絶縁膜とし
て主に二酸化シリコン（SiO2）を用い、その膜
厚は数100Åである。又、ゲート電極としては、
通常のｎチヤネル素子ではn+に不純物をドープ
した多結晶シリコンが用いられている。n+型多
結晶シリコンの仕事関数φMは約3.25（eV）、SiO2
の誘電率εiは約3.27×10-13（Ｆ／cm）であるいで、
これを式に代入して
di／εi≧3.38×106（cm2／Ｆ）
di≧110.68(A)
を得る。つまり従来のIGFETではdi／εi≧3.38×
106（cm2／Ｆ）を必須条件とし、ゲートSiO2膜の膜
厚は110.68（Å）以上必要であつた。 φ M ≧3.98−2.16×10 −7 ×di/si In the conventional IGFET structure, silicon dioxide (SiO 2 ) is mainly used as the gate insulating film, and the film thickness is several hundred Å. Also, as a gate electrode,
A typical n-channel device uses polycrystalline silicon doped with n + impurities. The work function φ M of n + type polycrystalline silicon is approximately 3.25 (eV), SiO 2
The dielectric constant εi of is about 3.27×10 -13 (F/cm),
Substituting this into the equation, di/εi≧3.38×10 6 (cm 2 /F) di≧110.68(A) is obtained. In other words, in the conventional IGFET, di/εi≧3.38×
The essential condition was 10 6 (cm 2 /F), and the thickness of the gate SiO 2 film was required to be 110.68 (Å) or more.
本発明は、従来の製造工程では実現されなかつ
た新規の構造を有するIGFETを提供とするもの
である。即ち、本発明では特に薄いゲート絶縁膜
を用いた時、しきい値電圧VTHの値を実用可能な
ものとするもので、ｎチヤネル素子の場合、
di／εi＜3.38×106（cm2／Ｆ）の範囲で
φM≧3.98−2.16×10-7×di／εi（eV）
の条件を満たす仕事関数φMのゲート電極を有す
ることを特徴とする。 The present invention provides an IGFET having a novel structure that has not been realized through conventional manufacturing processes. That is, in the present invention, when a particularly thin gate insulating film is used, the value of the threshold voltage V TH is made practical, and in the case of an n-channel device, di/εi<3.38×10 6 (cm 2 /F) and has a gate electrode with a work function φ M that satisfies the condition φ M ≧3.98−2.16×10 -7 ×di/εi (eV).
本発明により提供されるIGFETに用いられる
ゲート電極の仕事関数φMの範囲は第２図直線１
並びに破線２で挾まれる斜線部領域で示される。 The range of the work function φ M of the gate electrode used in the IGFET provided by the present invention is the straight line 1 in Figure 2.
This is also indicated by a diagonally shaded area surrounded by broken lines 2.
本発明の実施例としてゲート絶縁膜として例え
ば膜厚70Åのシリコン熱窒化膜を用いた場合につ
いて説明する。 As an embodiment of the present invention, a case will be described in which a silicon thermal nitride film having a thickness of, for example, 70 Å is used as the gate insulating film.
この場合シリコン熱窒化膜の誘電率εi＝5.3×
10-13（Ｆ／cm）di＝70×10-8（cm）であるので
di／εi≒1.32×106（cm2／Ｆ）
を得る。前記di／εiの値を式に代入すると、
φM≧3.69（eV）
であるためゲート電極としてタングステン（φM
＝3.69（eV）を用いることにより、実用可能な値
のしきい値電圧を有するIGFETを実現出来る。 In this case, the dielectric constant of silicon thermal nitride film εi=5.3×
10 -13 (F/cm) Since di=70×10 -8 (cm), we obtain di/εi≒1.32×10 6 (cm 2 /F). Substituting the value of di/εi into the equation, φ M ≧ 3.69 (eV), so tungsten (φ M
By using =3.69 (eV), it is possible to realize an IGFET with a practically usable threshold voltage.
その製造については通常のIGFETと同様に以
下の工程で行なう。始めにシリコン基板表面を直
接熱窒化して約70（Å）の熱窒化膜を形成した後
50（KeV）のエネルギーでボロンを５／1012（cm
-2）打ち込む。ついでゲート電極としてタングス
テンを電子ビーム蒸着により約5000（Å）付着せ
しめパターン形成する。完成したIGFETはしき
い値電圧VTH≒0.6(V)を得るが、gmが非常に大き
く特性の勝れたものを得ることが出来る。 Its manufacture is carried out in the same way as for ordinary IGFETs, using the following steps. First, the silicon substrate surface is directly thermally nitrided to form a thermal nitride film of approximately 70 (Å) thick.
Boron is 5/10 12 (cm
-2 ) Type. Next, tungsten is deposited to a thickness of about 5000 (Å) as a gate electrode by electron beam evaporation and patterned. The completed IGFET has a threshold voltage V TH ≈0.6 (V), but has a very large gm and excellent characteristics.
以上、本発明の説明ではQfS／Ciを無視したが、
これがたとえ存在したとしても通常QfS／Ciの値
は負の値をとるので、式によるゲート電極の仕
事関数φM領域は満足する値となる。 In the above explanation of the present invention, Q fS /Ci was ignored, but
Even if this exists, the value of Q fS /Ci usually takes a negative value, so the work function φ M region of the gate electrode according to the formula has a value that satisfies the value.
又、ここではｎチヤネル素子について説明した
が、ｐチヤネルのIGFETについても同様の範囲
が設定される。ｐチヤネルIGFETでは例えばり
んイオンの注入を行ない、素子動作に係る基板表
面近傍の不純物濃度が約1.67×1017（cm-3）以下の
ｎ型シリコン基板を用いて
di／εi＜4.5×106（cm2／Ｆ）の範囲で
φM≦3.38＋2.16×10-7×di／εi（単位、eV）
の条件を満たす必要がある。 Further, although an n-channel element has been described here, a similar range is set for a p-channel IGFET. In p-channel IGFETs, for example, phosphorus ions are implanted, and di/εi<4.5×10 6 using an n-type silicon substrate where the impurity concentration near the substrate surface related to device operation is approximately 1.67×10 17 (cm -3 ) or less. It is necessary to satisfy the condition φ M ≦3.38+2.16×10 −7 ×di/εi (unit, eV) within the range of (cm 2 /F).
第１図はボロンイオン注入による相互コンダク
タンスの低下を示す実験値で、第２図は本発明に
よるゲート電極の仕事関数値の範囲を示すもので
ある。第２図に於いて直線１は発明の詳細な説明
中式によるもので、破線２は同じく式による
ものである。
FIG. 1 shows experimental values showing the reduction in mutual conductance due to boron ion implantation, and FIG. 2 shows the range of work function values of the gate electrode according to the present invention. In FIG. 2, the straight line 1 is based on the formula in the detailed description of the invention, and the broken line 2 is also based on the formula.
Claims (1)
ゲート電極を形成した電界効果型半導体装置にお
いて、 ゲート電極の下の絶縁膜との界面近傍のチヤネ
ル領域となるべき領域が1.67×1017cm-3以下の不
純物濃度の前記シリコン基板と、 該シリコン基板の上に、その厚さdi（cm）とそ
の誘電率εi（Ｆ／cm）が、 di／εi＜3.38×106（cm2／Ｆ） であるような前記絶縁膜と、 該絶縁膜の上に、その仕事関数φMが φM ≧3.98−√4S A B×di／εi（eV） であるような金属、または不純物をドープした半
導体からなる前記ゲート電極とを有し、そのしき
い値電圧が0.6V以上になるように構成されて成
る電界効果型半導体装置。 ただし、εS；前記ｐ型シリコン基板の誘電率 ；電子電荷 NA；前記ｐ型シリコンの前記チヤネル領域の不
純物濃度 ψB；前記ｐ型シリコン基板のフエルミレベル[Claims] 1. In a field effect semiconductor device in which a gate electrode is formed on an insulating film formed on a p-type silicon substrate, a region to be a channel region near the interface with the insulating film under the gate electrode. The silicon substrate has an impurity concentration of 1.67×10 17 cm -3 or less, and the thickness di (cm) and the dielectric constant εi (F/cm) of 10 6 (cm 2 /F), and on the insulating film, a metal whose work function φM is φM ≧3.98−√4 S A B ×di/εi (eV). or the gate electrode made of a semiconductor doped with impurities, and the field effect semiconductor device is configured such that the threshold voltage thereof is 0.6V or more. However, ε S ; dielectric constant of the p-type silicon substrate; electron charge N A ; impurity concentration of the channel region of the p-type silicon ψ B : Fermi level of the p-type silicon substrate
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11630980A JPS5740978A (en) | 1980-08-22 | 1980-08-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11630980A JPS5740978A (en) | 1980-08-22 | 1980-08-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5740978A JPS5740978A (en) | 1982-03-06 |
| JPH0566029B2 true JPH0566029B2 (en) | 1993-09-20 |
Family
ID=14683808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11630980A Granted JPS5740978A (en) | 1980-08-22 | 1980-08-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5740978A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59134655U (en) * | 1983-02-28 | 1984-09-08 | タキゲン製造株式会社 | Temporary locking device for refrigerators, etc. that can be unlocked inside the refrigerator |
-
1980
- 1980-08-22 JP JP11630980A patent/JPS5740978A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5740978A (en) | 1982-03-06 |
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