JPH0564073A - Image processing control system - Google Patents

Image processing control system

Info

Publication number
JPH0564073A
JPH0564073A JP21770891A JP21770891A JPH0564073A JP H0564073 A JPH0564073 A JP H0564073A JP 21770891 A JP21770891 A JP 21770891A JP 21770891 A JP21770891 A JP 21770891A JP H0564073 A JPH0564073 A JP H0564073A
Authority
JP
Japan
Prior art keywords
image processing
memory
control
data
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21770891A
Other languages
Japanese (ja)
Other versions
JP3125344B2 (en
Inventor
Hideki Jinno
英樹 神野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP03217708A priority Critical patent/JP3125344B2/en
Publication of JPH0564073A publication Critical patent/JPH0564073A/en
Application granted granted Critical
Publication of JP3125344B2 publication Critical patent/JP3125344B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Processing Of Color Television Signals (AREA)
  • Studio Circuits (AREA)

Abstract

PURPOSE:To reduce the number of data memories storing image processing control data corresponding to the video signal of plural TV camera apparatuses. CONSTITUTION:The memory selecting parts 13 and 23 of processing blocks 10 and 20 generates memory selecting signals S1 and S2 specifying the corresponding data memory from information included in control information C1 and C2 to send them to a memory centralized control part 31, which allocates the data memories 41-4m in accordance with the memory selecting signals S1 and S2 to send allocating information W. Synthetic control signal generating part 12 and 22 generates synthetic control signals M1 and M2 based on control informations C1, C2 and allocating information W. Chromakey signal generating parts 11 and 21 image-processes the video signals V1-Vn in accordance with the synthetic control signals M1, M2 from the synthetic control signal generating parts 12, 22 and image processing control data K1-Km from the data memory 41-4m.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は画像処理制御システムに
関し、特に、複数のテレビカメラ装置からの映像信号を
含む入力映像信号の画像処理を複数の処理ブロックによ
りそれぞれ行う画像処理制御システムに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing control system, and more particularly to an image processing control system which performs image processing of an input video signal including video signals from a plurality of television camera devices by a plurality of processing blocks.

【0002】[0002]

【従来の技術】従来の画像処理制御システムは、図2に
示すように、複数の処理ブロック50,60を有し、制
御情報C1,C2に応じて、複数の映像信号V1〜Vn
の画像処理をそれぞれ行っている。ここで、n個の映像
信号V1〜Vnの内m個(m≦n)はm台のテレビカメ
ラ装置(図示せず)からの映像信号である。また、各処
理ブロック50,60には、複数の映像信号V1〜Vn
を受けて画像処理を行うクロマキー信号生成部51,6
1がそれぞれ設けられている。
2. Description of the Related Art A conventional image processing control system has a plurality of processing blocks 50 and 60, as shown in FIG. 2, and a plurality of video signals V1 to Vn according to control information C1 and C2.
Image processing of each. Here, among the n video signals V1 to Vn, m video signals (m ≦ n) are video signals from m television camera devices (not shown). Further, each of the processing blocks 50 and 60 has a plurality of video signals V1 to Vn.
Receiving the image processing, the chroma key signal generation units 51, 6
1 are provided respectively.

【0003】ところで、テレビカメラ装置の出力映像信
号は装置毎に色特性が相違している。このため、クロマ
キー信号生成部51,61を制御する画像処理制御デー
タは、テレビカメラ装置の出力映像信号に適合したデー
タに設定する必要があるので、各テレビカメラ装置毎の
画像処理制御データをデータメモリ501〜50m,6
01〜60mにそれぞれ記憶させている。
By the way, the output video signal of the television camera device has different color characteristics from device to device. For this reason, the image processing control data for controlling the chroma key signal generation units 51 and 61 needs to be set to the data suitable for the output video signal of the television camera device. Memories 501-50m, 6
It is stored in each of 01 to 60 m.

【0004】クロマキー信号生成部51,61は、処理
対象の映像信号を指定する合成制御信号M1,M2、お
よびデータメモリ501〜50m,601〜60mから
の画像処理制御データK11〜K1m,K21〜K2m
に応じてそれぞれ画像処理を行う。合成制御信号生成部
52,62は、制御情報C1,C2から合成制御信号M
1,M2を生成する。メモリ選択部53,63は、制御
情報C1,C2に含まれる情報により、該当するテレビ
カメラ装置に対応するデータメモリを選択している。
The chroma key signal generators 51 and 61 are composed control signals M1 and M2 designating a video signal to be processed, and image processing control data K11 to K1m and K21 to K2m from the data memories 501 to 50m and 601 to 60m.
Image processing is performed in accordance with each. The synthesis control signal generators 52 and 62 generate the synthesis control signal M from the control information C1 and C2.
1 and M2 are generated. The memory selection units 53 and 63 select the data memory corresponding to the corresponding TV camera device based on the information included in the control information C1 and C2.

【0005】[0005]

【発明が解決しようとする課題】上述した従来の画像処
理制御システムでは、複数の処理ブロックが、複数のテ
レビカメラ装置からの映像信号の画像処理をそれぞれ行
うために、各処理ブロックにはテレビカメラ装置に対応
する複数のデータメモリをそれぞれ配設している。この
ため、システム全体として多数のデータメモリが必要と
なり、構成が複雑化するという問題点を有している。
In the above-mentioned conventional image processing control system, since a plurality of processing blocks respectively perform image processing of video signals from a plurality of television camera devices, each processing block has a television camera. A plurality of data memories corresponding to the devices are provided respectively. For this reason, a large number of data memories are required for the entire system, and the configuration becomes complicated.

【0006】本発明の目的は、データメモリを共有する
ことにより、構成を簡素化できる画像処理制御システム
を提供することにある。
An object of the present invention is to provide an image processing control system which can simplify the configuration by sharing a data memory.

【0007】[0007]

【課題を解決するための手段】本発明の画像処理制御シ
ステムは、複数のテレビカメラ装置からの映像信号を含
む入力映像信号の画像処理を複数の処理ブロックにより
それぞれ行う画像処理制御システムにおいて、前記複数
のテレビカメラ装置のそれぞれの映像信号に対応する画
像処理制御データをそれぞれ記憶する複数のメモリと、
前記複数の処理ブロックからのメモリ選択信号を受けて
前記複数のメモリを割付けるメモリ管理手段とを備えて
構成される。また、前記複数の処理ブロックは、外部か
ら入力する制御情報および前記メモリ管理手段が割付け
たメモリ割付情報を受けて合成制御信号を生成する手段
と、前記制御情報に応じて該当するメモリを指定する前
記メモリ選択信号を生成する手段と、前記合成制御信号
および前記該当するメモリからの前記画像処理制御デー
タに応じて前記入力映像信号の画像処理を行う手段とを
具備して構成される。
An image processing control system according to the present invention is an image processing control system in which image processing of an input video signal including video signals from a plurality of television camera devices is performed by a plurality of processing blocks. A plurality of memories respectively storing image processing control data corresponding to respective video signals of the plurality of television camera devices,
Memory management means for allocating the plurality of memories in response to memory selection signals from the plurality of processing blocks. The plurality of processing blocks specify a means for receiving a control information inputted from the outside and a memory allocation information allocated by the memory management means to generate a composite control signal, and a corresponding memory according to the control information. It comprises a unit for generating the memory selection signal, and a unit for performing image processing of the input video signal according to the combination control signal and the image processing control data from the corresponding memory.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0009】図1は本発明の一実施例を示すブロック図
であり、2つの処理ブロック10,20を備えた場合を
示している。なお、処理ブロックが3以上であってもよ
い。ここで、図2に示した従来の場合と同様に、処理ブ
ロック10,20は制御情報C1,C2に応じて、複数
の映像信号V1〜Vnの画像処理をそれぞれ行うが、n
個の映像信号V1〜Vnの内m個(m≦n)はm台のテ
レビカメラ装置(図示せず)からの映像信号である。
FIG. 1 is a block diagram showing an embodiment of the present invention and shows a case where two processing blocks 10 and 20 are provided. The number of processing blocks may be three or more. Here, as in the conventional case shown in FIG. 2, the processing blocks 10 and 20 respectively perform image processing of a plurality of video signals V1 to Vn according to the control information C1 and C2, but n
Of the video signals V1 to Vn, m video signals (m ≦ n) are video signals from m TV camera devices (not shown).

【0010】各処理ブロック10,20に設けられたク
ロマキー信号生成部11,21は、合成制御信号生成部
12,22からの合成制御信号M1,M2、およびデー
タメモリ41〜4mからの画像処理制御データK1〜K
mにより制御されて、複数の映像信号V1〜Vnの画像
処理をそれぞれ行う。
The chroma key signal generators 11 and 21 provided in the respective processing blocks 10 and 20 are composed control signals M1 and M2 from the composition control signal generators 12 and 22, and image processing control from the data memories 41 to 4m. Data K1-K
The image processing of each of the plurality of video signals V1 to Vn is performed under the control of m.

【0011】ところで、テレビカメラ装置の映像信号に
対応した画像処理制御データを記憶しているデータメモ
リ41〜4mは、処理ブロック10,20が共用するよ
うにしている。このため、メモリ集中管理部31を設
け、データメモリ41〜4mの割付けを行うと共に、デ
ータメモリの割付け結果を割付情報Wとして各処理ブロ
ックへ送出している。
By the way, the data memories 41 to 4m storing the image processing control data corresponding to the video signal of the television camera device are shared by the processing blocks 10 and 20. For this reason, the memory centralized management unit 31 is provided to allocate the data memories 41 to 4m, and the allocation result of the data memory is sent to each processing block as allocation information W.

【0012】合成制御信号生成部12,22は、制御情
報C1,C2および割付情報Wに基づき合成制御信号M
1,M2を生成する。またメモリ選択部13,23は、
制御情報C1,C2に含まれる情報により、該当するテ
レビカメラ装置の映像信号に対応するデータメモリを指
定するメモリ選択信号S1,S2をメモリ集中管理部3
1へ送出する。メモリ集中管理部31は、メモリ選択部
13,23からメモリ選択信号S1,S2を受けてデー
タメモリ41〜4mの割付けを行って割付情報Wを送出
する。割付けられたデータメモリは、記憶している画像
処理制御データを送出する。このようにして、データメ
モリ41〜4mを処理ブロック10,20が共用する。
The synthesis control signal generators 12 and 22 generate a synthesis control signal M based on the control information C1 and C2 and the allocation information W.
1 and M2 are generated. In addition, the memory selection units 13 and 23
Based on the information included in the control information C1 and C2, the memory centralized management unit 3 outputs the memory selection signals S1 and S2 that specify the data memory corresponding to the video signal of the corresponding TV camera device.
Send to 1. The memory centralized management unit 31 receives the memory selection signals S1 and S2 from the memory selection units 13 and 23, allocates the data memories 41 to 4m, and sends allocation information W. The allocated data memory sends out the stored image processing control data. In this way, the processing blocks 10 and 20 share the data memories 41 to 4m.

【0013】[0013]

【発明の効果】以上説明したように本発明は、複数のデ
ータメモリの割付け管理を行うメモリ集中管理部を設け
ることにより、各処理ブロックはデータメモリを共用で
きるので、従来のように各処理ブロックにそれぞれデー
タメモリを備える必要はなく、データメモリを削減でき
て構成が簡素化できる。
As described above, according to the present invention, each processing block can share a data memory by providing a memory centralized management unit for managing allocation of a plurality of data memories. It is not necessary to provide each with a data memory, and the data memory can be reduced and the configuration can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】従来の画像処理制御システムの一例を示すブロ
ック図である。
FIG. 2 is a block diagram showing an example of a conventional image processing control system.

【符号の説明】[Explanation of symbols]

10,20 処理ブロック 11,21 クロマキー信号生成部 12,22 合成制御信号生成部 13,23 メモリ選択部 31 メモリ集中管理部 41〜4m データメモリ C1,C2 制御情報 K1〜Km 画像処理制御データ M1,M2 合成制御信号 S1,S2 メモリ選択信号 W 割付情報 10, 20 Processing block 11, 21 Chroma key signal generation unit 12, 22 Composite control signal generation unit 13, 23 Memory selection unit 31 Memory centralized management unit 41-4m Data memory C1, C2 Control information K1-Km Image processing control data M1, M2 Composite control signal S1, S2 Memory selection signal W Allocation information

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数のテレビカメラ装置からの映像信号
を含む入力映像信号の画像処理を複数の処理ブロックに
よりそれぞれ行う画像処理制御システムにおいて、前記
複数のテレビカメラ装置のそれぞれの映像信号に対応す
る画像処理制御データをそれぞれ記憶する複数のメモリ
と、前記複数の処理ブロックからのメモリ選択信号を受
けて前記複数のメモリを割付けるメモリ管理手段とを備
えることを特徴とする画像処理制御システム。
1. An image processing control system for performing image processing of an input video signal including video signals from a plurality of television camera devices by a plurality of processing blocks, which corresponds to each video signal of the plurality of television camera devices. An image processing control system comprising: a plurality of memories that respectively store image processing control data; and a memory management unit that receives the memory selection signals from the plurality of processing blocks and allocates the plurality of memories.
【請求項2】 前記複数の処理ブロックは、外部から入
力する制御情報および前記メモリ管理手段が割付けたメ
モリ割付情報を受けて合成制御信号を生成する手段と、
前記制御情報に応じて該当するメモリを指定する前記メ
モリ選択信号を生成する手段と、前記合成制御信号およ
び前記該当するメモリからの前記画像処理制御データに
応じて前記入力映像信号の画像処理を行う手段とを具備
することを特徴とする請求項1記載の画像処理制御シス
テム。
2. The plurality of processing blocks receive control information input from the outside and memory allocation information allocated by the memory management means, and generate a combined control signal.
Means for generating the memory selection signal for designating a corresponding memory according to the control information, and image processing of the input video signal according to the composite control signal and the image processing control data from the corresponding memory The image processing control system according to claim 1, further comprising:
JP03217708A 1991-08-29 1991-08-29 Image processing control system Expired - Fee Related JP3125344B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03217708A JP3125344B2 (en) 1991-08-29 1991-08-29 Image processing control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03217708A JP3125344B2 (en) 1991-08-29 1991-08-29 Image processing control system

Publications (2)

Publication Number Publication Date
JPH0564073A true JPH0564073A (en) 1993-03-12
JP3125344B2 JP3125344B2 (en) 2001-01-15

Family

ID=16708494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03217708A Expired - Fee Related JP3125344B2 (en) 1991-08-29 1991-08-29 Image processing control system

Country Status (1)

Country Link
JP (1) JP3125344B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07256171A (en) * 1993-03-26 1995-10-09 Daishinku Co Ultrasonic vibrator and atomizer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07256171A (en) * 1993-03-26 1995-10-09 Daishinku Co Ultrasonic vibrator and atomizer

Also Published As

Publication number Publication date
JP3125344B2 (en) 2001-01-15

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